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arm64: dts: Add ARM PMUv3 DT node in NS2 DT

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The NS2 SoC has Cortex-A57 CPUs which support ARM PMUv3 so,
lets enable ARM PMUv3 in NS2 DT.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Vikram Prakash <vikramp@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit is contained in:
Anup Patel 2015-10-02 23:24:21 +05:30 committed by Florian Fainelli
parent 5b467c3b2d
commit 5b31d8759b
1 changed files with 16 additions and 4 deletions
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20
arch/arm64/boot/dts/broadcom/ns2.dtsi
View file

@ -44,7 +44,7 @@ cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
A57_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 0>;
@ -53,7 +53,7 @@ cpu@0 {
next-level-cache = <&CLUSTER0_L2>;
};
cpu@1 {
A57_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 1>;
@ -62,7 +62,7 @@ cpu@1 {
next-level-cache = <&CLUSTER0_L2>;
};
cpu@2 {
A57_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 2>;
@ -71,7 +71,7 @@ cpu@2 {
next-level-cache = <&CLUSTER0_L2>;
};
cpu@3 {
A57_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
reg = <0 3>;
@ -97,6 +97,18 @@ IRQ_TYPE_EDGE_RISING)>,
IRQ_TYPE_EDGE_RISING)>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&A57_0>,
<&A57_1>,
<&A57_2>,
<&A57_3>;
};
soc: soc {
compatible = "simple-bus";
#address-cells = <1>;