Merge tag 'master-2014-09-08' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next

John W. Linville says:

====================
pull request: wireless-next 2014-09-08

Please pull this batch of updates intended for the 3.18 stream...

For the mac80211 bits, Johannes says:

"Not that much content this time. Some RCU cleanups, crypto
performance improvements, and various patches all over,
rather than listing them one might as well look into the
git log instead."

For the Bluetooth bits, Gustavo says:

"The changes consists of:

        - Coding style fixes to HCI drivers
        - Corrupted ack value fix for the H5 HCI driver
        - A couple of Enhanced L2CAP fixes
        - Conversion of SMP code to use common L2CAP channel API
        - Page scan optimizations when using the kernel-side whitelist
        - Various mac802154 and and ieee802154 6lowpan cleanups
        - One new Atheros USB ID"

For the iwlwifi bits, Emmanuel says:

"We have a new big thing coming up which is called Dynamic Queue
Allocation (or DQA).  This is a completely new way to work with the
Tx queues and it requires major refactoring.  This is being done by
Johannes and Avri.  Besides this, Johannes disables U-APSD by default
because of APs that would disable A-MPDU if the association supports
U-ASPD.  Luca contributed to the power area which he was cleaning
up on the way while working on CSA.  A few more random things here
and there."

For the Atheros bits, Kalle says:

"For ath6kl we had two small fixes and a new SDIO device id.

For ath10k the bigger changes are:

 * support for new firmware version 10.2 (Michal)

 * spectral scan support (Simon, Sven & Mathias)

 * export a firmware crash dump file (Ben & me)

 * cleaning up of pci.c (Michal)

 * print pci id in all messages, which causes most of the churn (Michal)"

Beyond that, we have the usual collection of various updates to ath9k,
b43, mwifiex, and wil6210, as well as a few other bits here and there.

Please let me know if there are problems!
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2014-09-08 16:43:58 -07:00
commit 5b4c314575
213 changed files with 8881 additions and 4613 deletions

View File

@ -152,8 +152,8 @@ F: drivers/scsi/53c700*
6LOWPAN GENERIC (BTLE/IEEE 802.15.4)
M: Alexander Aring <alex.aring@gmail.com>
L: linux-zigbee-devel@lists.sourceforge.net (moderated for non-subscribers)
L: linux-bluetooth@vger.kernel.org
L: linux-wpan@vger.kernel.org
S: Maintained
F: net/6lowpan/
F: include/net/6lowpan.h
@ -4597,13 +4597,14 @@ F: drivers/idle/i7300_idle.c
IEEE 802.15.4 SUBSYSTEM
M: Alexander Aring <alex.aring@gmail.com>
L: linux-zigbee-devel@lists.sourceforge.net (moderated for non-subscribers)
W: http://apps.sourceforge.net/trac/linux-zigbee
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lowpan/lowpan.git
L: linux-wpan@vger.kernel.org
W: https://github.com/linux-wpan
T: git git://github.com/linux-wpan/linux-wpan-next.git
S: Maintained
F: net/ieee802154/
F: net/mac802154/
F: drivers/net/ieee802154/
F: Documentation/networking/ieee802154.txt
IGUANAWORKS USB IR TRANSCEIVER
M: Sean Young <sean@mess.org>
@ -6373,7 +6374,7 @@ M: Lauro Ramos Venancio <lauro.venancio@openbossa.org>
M: Aloisio Almeida Jr <aloisio.almeida@openbossa.org>
M: Samuel Ortiz <sameo@linux.intel.com>
L: linux-wireless@vger.kernel.org
L: linux-nfc@lists.01.org (moderated for non-subscribers)
L: linux-nfc@lists.01.org (subscribers-only)
S: Supported
F: net/nfc/
F: include/net/nfc/

View File

@ -21,6 +21,14 @@
#include <linux/serial_reg.h>
#include <linux/time.h>
enum bcma_boot_dev {
BCMA_BOOT_DEV_UNK = 0,
BCMA_BOOT_DEV_ROM,
BCMA_BOOT_DEV_PARALLEL,
BCMA_BOOT_DEV_SERIAL,
BCMA_BOOT_DEV_NAND,
};
static const char * const part_probes[] = { "bcm47xxpart", NULL };
static struct physmap_flash_data bcma_pflash_data = {
@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips *mcore)
}
EXPORT_SYMBOL(bcma_cpu_clock);
static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
{
struct bcma_drv_cc *cc = &bus->drv_cc;
u8 cc_rev = cc->core->id.rev;
if (cc_rev == 42) {
struct bcma_device *core;
core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
if (core) {
switch (bcma_aread32(core, BCMA_IOST) &
BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
return BCMA_BOOT_DEV_SERIAL;
case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
return BCMA_BOOT_DEV_NAND;
case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
default:
return BCMA_BOOT_DEV_ROM;
}
}
} else {
if (cc_rev == 38) {
if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
return BCMA_BOOT_DEV_NAND;
else if (cc->status & BIT(5))
return BCMA_BOOT_DEV_ROM;
}
if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
BCMA_CC_FLASHT_PARA)
return BCMA_BOOT_DEV_PARALLEL;
else
return BCMA_BOOT_DEV_SERIAL;
}
return BCMA_BOOT_DEV_SERIAL;
}
static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
{
struct bcma_bus *bus = mcore->core->bus;
struct bcma_drv_cc *cc = &bus->drv_cc;
struct bcma_pflash *pflash = &cc->pflash;
enum bcma_boot_dev boot_dev;
switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
case BCMA_CC_FLASHT_STSER:
@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
bcma_nflash_init(cc);
}
}
/* Determine flash type this SoC boots from */
boot_dev = bcma_boot_dev(bus);
switch (boot_dev) {
case BCMA_BOOT_DEV_PARALLEL:
case BCMA_BOOT_DEV_SERIAL:
/* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
break;
case BCMA_BOOT_DEV_NAND:
/* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
break;
default:
break;
}
}
void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)

View File

@ -134,12 +134,16 @@ static void bcma_host_soc_block_write(struct bcma_device *core,
static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
{
if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
return ~0;
return readl(core->io_wrap + offset);
}
static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
u32 value)
{
if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
return;
writel(value, core->io_wrap + offset);
}

View File

@ -421,10 +421,13 @@ static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
if (!core->io_addr)
return -ENOMEM;
core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
if (!core->io_wrap) {
iounmap(core->io_addr);
return -ENOMEM;
if (core->wrap) {
core->io_wrap = ioremap_nocache(core->wrap,
BCMA_CORE_SIZE);
if (!core->io_wrap) {
iounmap(core->io_addr);
return -ENOMEM;
}
}
}
return 0;

View File

@ -88,6 +88,7 @@ static const struct usb_device_id ath3k_table[] = {
{ USB_DEVICE(0x04CA, 0x300b) },
{ USB_DEVICE(0x0930, 0x0219) },
{ USB_DEVICE(0x0930, 0x0220) },
{ USB_DEVICE(0x0930, 0x0227) },
{ USB_DEVICE(0x0b05, 0x17d0) },
{ USB_DEVICE(0x0CF3, 0x0036) },
{ USB_DEVICE(0x0CF3, 0x3004) },
@ -138,6 +139,7 @@ static const struct usb_device_id ath3k_blist_tbl[] = {
{ USB_DEVICE(0x04ca, 0x300b), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0930, 0x0219), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0930, 0x0220), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0930, 0x0227), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0b05, 0x17d0), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0CF3, 0x0036), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0cf3, 0x3004), .driver_info = BTUSB_ATH3012 },

View File

@ -61,7 +61,7 @@ MODULE_LICENSE("GPL");
/* ======================== Local structures ======================== */
typedef struct bluecard_info_t {
struct bluecard_info {
struct pcmcia_device *p_dev;
struct hci_dev *hdev;
@ -78,7 +78,7 @@ typedef struct bluecard_info_t {
unsigned char ctrl_reg;
unsigned long hw_state; /* Status of the hardware and LED control */
} bluecard_info_t;
};
static int bluecard_config(struct pcmcia_device *link);
@ -157,7 +157,7 @@ static void bluecard_detach(struct pcmcia_device *p_dev);
static void bluecard_activity_led_timeout(u_long arg)
{
bluecard_info_t *info = (bluecard_info_t *)arg;
struct bluecard_info *info = (struct bluecard_info *)arg;
unsigned int iobase = info->p_dev->resource[0]->start;
if (!test_bit(CARD_HAS_PCCARD_ID, &(info->hw_state)))
@ -173,7 +173,7 @@ static void bluecard_activity_led_timeout(u_long arg)
}
static void bluecard_enable_activity_led(bluecard_info_t *info)
static void bluecard_enable_activity_led(struct bluecard_info *info)
{
unsigned int iobase = info->p_dev->resource[0]->start;
@ -215,7 +215,7 @@ static int bluecard_write(unsigned int iobase, unsigned int offset, __u8 *buf, i
}
static void bluecard_write_wakeup(bluecard_info_t *info)
static void bluecard_write_wakeup(struct bluecard_info *info)
{
if (!info) {
BT_ERR("Unknown device");
@ -368,7 +368,8 @@ static int bluecard_read(unsigned int iobase, unsigned int offset, __u8 *buf, in
}
static void bluecard_receive(bluecard_info_t *info, unsigned int offset)
static void bluecard_receive(struct bluecard_info *info,
unsigned int offset)
{
unsigned int iobase;
unsigned char buf[31];
@ -497,7 +498,7 @@ static void bluecard_receive(bluecard_info_t *info, unsigned int offset)
static irqreturn_t bluecard_interrupt(int irq, void *dev_inst)
{
bluecard_info_t *info = dev_inst;
struct bluecard_info *info = dev_inst;
unsigned int iobase;
unsigned char reg;
@ -562,7 +563,7 @@ static irqreturn_t bluecard_interrupt(int irq, void *dev_inst)
static int bluecard_hci_set_baud_rate(struct hci_dev *hdev, int baud)
{
bluecard_info_t *info = hci_get_drvdata(hdev);
struct bluecard_info *info = hci_get_drvdata(hdev);
struct sk_buff *skb;
/* Ericsson baud rate command */
@ -611,7 +612,7 @@ static int bluecard_hci_set_baud_rate(struct hci_dev *hdev, int baud)
static int bluecard_hci_flush(struct hci_dev *hdev)
{
bluecard_info_t *info = hci_get_drvdata(hdev);
struct bluecard_info *info = hci_get_drvdata(hdev);
/* Drop TX queue */
skb_queue_purge(&(info->txq));
@ -622,7 +623,7 @@ static int bluecard_hci_flush(struct hci_dev *hdev)
static int bluecard_hci_open(struct hci_dev *hdev)
{
bluecard_info_t *info = hci_get_drvdata(hdev);
struct bluecard_info *info = hci_get_drvdata(hdev);
if (test_bit(CARD_HAS_PCCARD_ID, &(info->hw_state)))
bluecard_hci_set_baud_rate(hdev, DEFAULT_BAUD_RATE);
@ -643,7 +644,7 @@ static int bluecard_hci_open(struct hci_dev *hdev)
static int bluecard_hci_close(struct hci_dev *hdev)
{
bluecard_info_t *info = hci_get_drvdata(hdev);
struct bluecard_info *info = hci_get_drvdata(hdev);
if (!test_and_clear_bit(HCI_RUNNING, &(hdev->flags)))
return 0;
@ -663,7 +664,7 @@ static int bluecard_hci_close(struct hci_dev *hdev)
static int bluecard_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
{
bluecard_info_t *info = hci_get_drvdata(hdev);
struct bluecard_info *info = hci_get_drvdata(hdev);
switch (bt_cb(skb)->pkt_type) {
case HCI_COMMAND_PKT:
@ -691,7 +692,7 @@ static int bluecard_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
/* ======================== Card services HCI interaction ======================== */
static int bluecard_open(bluecard_info_t *info)
static int bluecard_open(struct bluecard_info *info)
{
unsigned int iobase = info->p_dev->resource[0]->start;
struct hci_dev *hdev;
@ -806,7 +807,7 @@ static int bluecard_open(bluecard_info_t *info)
}
static int bluecard_close(bluecard_info_t *info)
static int bluecard_close(struct bluecard_info *info)
{
unsigned int iobase = info->p_dev->resource[0]->start;
struct hci_dev *hdev = info->hdev;
@ -833,7 +834,7 @@ static int bluecard_close(bluecard_info_t *info)
static int bluecard_probe(struct pcmcia_device *link)
{
bluecard_info_t *info;
struct bluecard_info *info;
/* Create new info device */
info = devm_kzalloc(&link->dev, sizeof(*info), GFP_KERNEL);
@ -857,7 +858,7 @@ static void bluecard_detach(struct pcmcia_device *link)
static int bluecard_config(struct pcmcia_device *link)
{
bluecard_info_t *info = link->priv;
struct bluecard_info *info = link->priv;
int i, n;
link->config_index = 0x20;
@ -897,7 +898,7 @@ failed:
static void bluecard_release(struct pcmcia_device *link)
{
bluecard_info_t *info = link->priv;
struct bluecard_info *info = link->priv;
bluecard_close(info);

View File

@ -67,7 +67,7 @@ MODULE_FIRMWARE("BT3CPCC.bin");
/* ======================== Local structures ======================== */
typedef struct bt3c_info_t {
struct bt3c_info {
struct pcmcia_device *p_dev;
struct hci_dev *hdev;
@ -80,7 +80,7 @@ typedef struct bt3c_info_t {
unsigned long rx_state;
unsigned long rx_count;
struct sk_buff *rx_skb;
} bt3c_info_t;
};
static int bt3c_config(struct pcmcia_device *link);
@ -175,7 +175,7 @@ static int bt3c_write(unsigned int iobase, int fifo_size, __u8 *buf, int len)
}
static void bt3c_write_wakeup(bt3c_info_t *info)
static void bt3c_write_wakeup(struct bt3c_info *info)
{
if (!info) {
BT_ERR("Unknown device");
@ -214,7 +214,7 @@ static void bt3c_write_wakeup(bt3c_info_t *info)
}
static void bt3c_receive(bt3c_info_t *info)
static void bt3c_receive(struct bt3c_info *info)
{
unsigned int iobase;
int size = 0, avail;
@ -336,7 +336,7 @@ static void bt3c_receive(bt3c_info_t *info)
static irqreturn_t bt3c_interrupt(int irq, void *dev_inst)
{
bt3c_info_t *info = dev_inst;
struct bt3c_info *info = dev_inst;
unsigned int iobase;
int iir;
irqreturn_t r = IRQ_NONE;
@ -388,7 +388,7 @@ static irqreturn_t bt3c_interrupt(int irq, void *dev_inst)
static int bt3c_hci_flush(struct hci_dev *hdev)
{
bt3c_info_t *info = hci_get_drvdata(hdev);
struct bt3c_info *info = hci_get_drvdata(hdev);
/* Drop TX queue */
skb_queue_purge(&(info->txq));
@ -418,7 +418,7 @@ static int bt3c_hci_close(struct hci_dev *hdev)
static int bt3c_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
{
bt3c_info_t *info = hci_get_drvdata(hdev);
struct bt3c_info *info = hci_get_drvdata(hdev);
unsigned long flags;
switch (bt_cb(skb)->pkt_type) {
@ -451,7 +451,8 @@ static int bt3c_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
/* ======================== Card services HCI interaction ======================== */
static int bt3c_load_firmware(bt3c_info_t *info, const unsigned char *firmware,
static int bt3c_load_firmware(struct bt3c_info *info,
const unsigned char *firmware,
int count)
{
char *ptr = (char *) firmware;
@ -536,7 +537,7 @@ error:
}
static int bt3c_open(bt3c_info_t *info)
static int bt3c_open(struct bt3c_info *info)
{
const struct firmware *firmware;
struct hci_dev *hdev;
@ -603,7 +604,7 @@ error:
}
static int bt3c_close(bt3c_info_t *info)
static int bt3c_close(struct bt3c_info *info)
{
struct hci_dev *hdev = info->hdev;
@ -620,7 +621,7 @@ static int bt3c_close(bt3c_info_t *info)
static int bt3c_probe(struct pcmcia_device *link)
{
bt3c_info_t *info;
struct bt3c_info *info;
/* Create new info device */
info = devm_kzalloc(&link->dev, sizeof(*info), GFP_KERNEL);
@ -683,7 +684,7 @@ static int bt3c_check_config_notpicky(struct pcmcia_device *p_dev,
static int bt3c_config(struct pcmcia_device *link)
{
bt3c_info_t *info = link->priv;
struct bt3c_info *info = link->priv;
int i;
unsigned long try;
@ -724,7 +725,7 @@ failed:
static void bt3c_release(struct pcmcia_device *link)
{
bt3c_info_t *info = link->priv;
struct bt3c_info *info = link->priv;
bt3c_close(info);

View File

@ -62,7 +62,7 @@ MODULE_LICENSE("GPL");
/* ======================== Local structures ======================== */
typedef struct btuart_info_t {
struct btuart_info {
struct pcmcia_device *p_dev;
struct hci_dev *hdev;
@ -75,7 +75,7 @@ typedef struct btuart_info_t {
unsigned long rx_state;
unsigned long rx_count;
struct sk_buff *rx_skb;
} btuart_info_t;
};
static int btuart_config(struct pcmcia_device *link);
@ -127,7 +127,7 @@ static int btuart_write(unsigned int iobase, int fifo_size, __u8 *buf, int len)
}
static void btuart_write_wakeup(btuart_info_t *info)
static void btuart_write_wakeup(struct btuart_info *info)
{
if (!info) {
BT_ERR("Unknown device");
@ -172,7 +172,7 @@ static void btuart_write_wakeup(btuart_info_t *info)
}
static void btuart_receive(btuart_info_t *info)
static void btuart_receive(struct btuart_info *info)
{
unsigned int iobase;
int boguscount = 0;
@ -286,7 +286,7 @@ static void btuart_receive(btuart_info_t *info)
static irqreturn_t btuart_interrupt(int irq, void *dev_inst)
{
btuart_info_t *info = dev_inst;
struct btuart_info *info = dev_inst;
unsigned int iobase;
int boguscount = 0;
int iir, lsr;
@ -340,7 +340,8 @@ static irqreturn_t btuart_interrupt(int irq, void *dev_inst)
}
static void btuart_change_speed(btuart_info_t *info, unsigned int speed)
static void btuart_change_speed(struct btuart_info *info,
unsigned int speed)
{
unsigned long flags;
unsigned int iobase;
@ -397,7 +398,7 @@ static void btuart_change_speed(btuart_info_t *info, unsigned int speed)
static int btuart_hci_flush(struct hci_dev *hdev)
{
btuart_info_t *info = hci_get_drvdata(hdev);
struct btuart_info *info = hci_get_drvdata(hdev);
/* Drop TX queue */
skb_queue_purge(&(info->txq));
@ -427,7 +428,7 @@ static int btuart_hci_close(struct hci_dev *hdev)
static int btuart_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
{
btuart_info_t *info = hci_get_drvdata(hdev);
struct btuart_info *info = hci_get_drvdata(hdev);
switch (bt_cb(skb)->pkt_type) {
case HCI_COMMAND_PKT:
@ -455,7 +456,7 @@ static int btuart_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
/* ======================== Card services HCI interaction ======================== */
static int btuart_open(btuart_info_t *info)
static int btuart_open(struct btuart_info *info)
{
unsigned long flags;
unsigned int iobase = info->p_dev->resource[0]->start;
@ -521,7 +522,7 @@ static int btuart_open(btuart_info_t *info)
}
static int btuart_close(btuart_info_t *info)
static int btuart_close(struct btuart_info *info)
{
unsigned long flags;
unsigned int iobase = info->p_dev->resource[0]->start;
@ -550,7 +551,7 @@ static int btuart_close(btuart_info_t *info)
static int btuart_probe(struct pcmcia_device *link)
{
btuart_info_t *info;
struct btuart_info *info;
/* Create new info device */
info = devm_kzalloc(&link->dev, sizeof(*info), GFP_KERNEL);
@ -613,7 +614,7 @@ static int btuart_check_config_notpicky(struct pcmcia_device *p_dev,
static int btuart_config(struct pcmcia_device *link)
{
btuart_info_t *info = link->priv;
struct btuart_info *info = link->priv;
int i;
int try;
@ -654,7 +655,7 @@ failed:
static void btuart_release(struct pcmcia_device *link)
{
btuart_info_t *info = link->priv;
struct btuart_info *info = link->priv;
btuart_close(info);

View File

@ -165,6 +165,7 @@ static const struct usb_device_id blacklist_table[] = {
{ USB_DEVICE(0x04ca, 0x300b), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0930, 0x0219), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0930, 0x0220), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0930, 0x0227), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0b05, 0x17d0), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0cf3, 0x0036), .driver_info = BTUSB_ATH3012 },
{ USB_DEVICE(0x0cf3, 0x3004), .driver_info = BTUSB_ATH3012 },

View File

@ -62,7 +62,7 @@ MODULE_LICENSE("GPL");
/* ======================== Local structures ======================== */
typedef struct dtl1_info_t {
struct dtl1_info {
struct pcmcia_device *p_dev;
struct hci_dev *hdev;
@ -78,7 +78,7 @@ typedef struct dtl1_info_t {
unsigned long rx_state;
unsigned long rx_count;
struct sk_buff *rx_skb;
} dtl1_info_t;
};
static int dtl1_config(struct pcmcia_device *link);
@ -94,11 +94,11 @@ static int dtl1_config(struct pcmcia_device *link);
#define RECV_WAIT_DATA 1
typedef struct {
struct nsh {
u8 type;
u8 zero;
u16 len;
} __packed nsh_t; /* Nokia Specific Header */
} __packed; /* Nokia Specific Header */
#define NSHL 4 /* Nokia Specific Header Length */
@ -126,7 +126,7 @@ static int dtl1_write(unsigned int iobase, int fifo_size, __u8 *buf, int len)
}
static void dtl1_write_wakeup(dtl1_info_t *info)
static void dtl1_write_wakeup(struct dtl1_info *info)
{
if (!info) {
BT_ERR("Unknown device");
@ -176,7 +176,7 @@ static void dtl1_write_wakeup(dtl1_info_t *info)
}
static void dtl1_control(dtl1_info_t *info, struct sk_buff *skb)
static void dtl1_control(struct dtl1_info *info, struct sk_buff *skb)
{
u8 flowmask = *(u8 *)skb->data;
int i;
@ -199,10 +199,10 @@ static void dtl1_control(dtl1_info_t *info, struct sk_buff *skb)
}
static void dtl1_receive(dtl1_info_t *info)
static void dtl1_receive(struct dtl1_info *info)
{
unsigned int iobase;
nsh_t *nsh;
struct nsh *nsh;
int boguscount = 0;
if (!info) {
@ -227,7 +227,7 @@ static void dtl1_receive(dtl1_info_t *info)
}
*skb_put(info->rx_skb, 1) = inb(iobase + UART_RX);
nsh = (nsh_t *)info->rx_skb->data;
nsh = (struct nsh *)info->rx_skb->data;
info->rx_count--;
@ -287,7 +287,7 @@ static void dtl1_receive(dtl1_info_t *info)
static irqreturn_t dtl1_interrupt(int irq, void *dev_inst)
{
dtl1_info_t *info = dev_inst;
struct dtl1_info *info = dev_inst;
unsigned int iobase;
unsigned char msr;
int boguscount = 0;
@ -365,7 +365,7 @@ static int dtl1_hci_open(struct hci_dev *hdev)
static int dtl1_hci_flush(struct hci_dev *hdev)
{
dtl1_info_t *info = hci_get_drvdata(hdev);
struct dtl1_info *info = hci_get_drvdata(hdev);
/* Drop TX queue */
skb_queue_purge(&(info->txq));
@ -387,9 +387,9 @@ static int dtl1_hci_close(struct hci_dev *hdev)
static int dtl1_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
{
dtl1_info_t *info = hci_get_drvdata(hdev);
struct dtl1_info *info = hci_get_drvdata(hdev);
struct sk_buff *s;
nsh_t nsh;
struct nsh nsh;
switch (bt_cb(skb)->pkt_type) {
case HCI_COMMAND_PKT:
@ -436,7 +436,7 @@ static int dtl1_hci_send_frame(struct hci_dev *hdev, struct sk_buff *skb)
/* ======================== Card services HCI interaction ======================== */
static int dtl1_open(dtl1_info_t *info)
static int dtl1_open(struct dtl1_info *info)
{
unsigned long flags;
unsigned int iobase = info->p_dev->resource[0]->start;
@ -505,7 +505,7 @@ static int dtl1_open(dtl1_info_t *info)
}
static int dtl1_close(dtl1_info_t *info)
static int dtl1_close(struct dtl1_info *info)
{
unsigned long flags;
unsigned int iobase = info->p_dev->resource[0]->start;
@ -534,7 +534,7 @@ static int dtl1_close(dtl1_info_t *info)
static int dtl1_probe(struct pcmcia_device *link)
{
dtl1_info_t *info;
struct dtl1_info *info;
/* Create new info device */
info = devm_kzalloc(&link->dev, sizeof(*info), GFP_KERNEL);
@ -552,7 +552,7 @@ static int dtl1_probe(struct pcmcia_device *link)
static void dtl1_detach(struct pcmcia_device *link)
{
dtl1_info_t *info = link->priv;
struct dtl1_info *info = link->priv;
dtl1_close(info);
pcmcia_disable_device(link);
@ -571,7 +571,7 @@ static int dtl1_confcheck(struct pcmcia_device *p_dev, void *priv_data)
static int dtl1_config(struct pcmcia_device *link)
{
dtl1_info_t *info = link->priv;
struct dtl1_info *info = link->priv;
int ret;
/* Look for a generic full-sized window */

View File

@ -237,7 +237,7 @@ static void h5_pkt_cull(struct h5 *h5)
break;
to_remove--;
seq = (seq - 1) % 8;
seq = (seq - 1) & 0x07;
}
if (seq != h5->rx_ack)

View File

@ -261,6 +261,7 @@ enum ATH_DEBUG {
ATH_DBG_MCI = 0x00008000,
ATH_DBG_DFS = 0x00010000,
ATH_DBG_WOW = 0x00020000,
ATH_DBG_CHAN_CTX = 0x00040000,
ATH_DBG_ANY = 0xffffffff
};

View File

@ -25,6 +25,7 @@ config ATH10K_DEBUG
config ATH10K_DEBUGFS
bool "Atheros ath10k debugfs support"
depends on ATH10K
select RELAY
---help---
Enabled debugfs support

View File

@ -10,6 +10,7 @@ ath10k_core-y += mac.o \
wmi.o \
bmi.o
ath10k_core-$(CONFIG_ATH10K_DEBUGFS) += spectral.o
ath10k_core-$(CONFIG_ATH10K_TRACING) += trace.o
obj-$(CONFIG_ATH10K_PCI) += ath10k_pci.o

View File

@ -22,7 +22,7 @@
void ath10k_bmi_start(struct ath10k *ar)
{
ath10k_dbg(ATH10K_DBG_BMI, "bmi start\n");
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi start\n");
ar->bmi.done_sent = false;
}
@ -33,10 +33,10 @@ int ath10k_bmi_done(struct ath10k *ar)
u32 cmdlen = sizeof(cmd.id) + sizeof(cmd.done);
int ret;
ath10k_dbg(ATH10K_DBG_BMI, "bmi done\n");
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi done\n");
if (ar->bmi.done_sent) {
ath10k_dbg(ATH10K_DBG_BMI, "bmi skipped\n");
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi skipped\n");
return 0;
}
@ -45,7 +45,7 @@ int ath10k_bmi_done(struct ath10k *ar)
ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, cmdlen, NULL, NULL);
if (ret) {
ath10k_warn("unable to write to the device: %d\n", ret);
ath10k_warn(ar, "unable to write to the device: %d\n", ret);
return ret;
}
@ -61,10 +61,10 @@ int ath10k_bmi_get_target_info(struct ath10k *ar,
u32 resplen = sizeof(resp.get_target_info);
int ret;
ath10k_dbg(ATH10K_DBG_BMI, "bmi get target info\n");
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi get target info\n");
if (ar->bmi.done_sent) {
ath10k_warn("BMI Get Target Info Command disallowed\n");
ath10k_warn(ar, "BMI Get Target Info Command disallowed\n");
return -EBUSY;
}
@ -72,12 +72,12 @@ int ath10k_bmi_get_target_info(struct ath10k *ar,
ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, cmdlen, &resp, &resplen);
if (ret) {
ath10k_warn("unable to get target info from device\n");
ath10k_warn(ar, "unable to get target info from device\n");
return ret;
}
if (resplen < sizeof(resp.get_target_info)) {
ath10k_warn("invalid get_target_info response length (%d)\n",
ath10k_warn(ar, "invalid get_target_info response length (%d)\n",
resplen);
return -EIO;
}
@ -97,11 +97,11 @@ int ath10k_bmi_read_memory(struct ath10k *ar,
u32 rxlen;
int ret;
ath10k_dbg(ATH10K_DBG_BMI, "bmi read address 0x%x length %d\n",
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi read address 0x%x length %d\n",
address, length);
if (ar->bmi.done_sent) {
ath10k_warn("command disallowed\n");
ath10k_warn(ar, "command disallowed\n");
return -EBUSY;
}
@ -115,7 +115,7 @@ int ath10k_bmi_read_memory(struct ath10k *ar,
ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, cmdlen,
&resp, &rxlen);
if (ret) {
ath10k_warn("unable to read from the device (%d)\n",
ath10k_warn(ar, "unable to read from the device (%d)\n",
ret);
return ret;
}
@ -137,11 +137,11 @@ int ath10k_bmi_write_memory(struct ath10k *ar,
u32 txlen;
int ret;
ath10k_dbg(ATH10K_DBG_BMI, "bmi write address 0x%x length %d\n",
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi write address 0x%x length %d\n",
address, length);
if (ar->bmi.done_sent) {
ath10k_warn("command disallowed\n");
ath10k_warn(ar, "command disallowed\n");
return -EBUSY;
}
@ -159,7 +159,7 @@ int ath10k_bmi_write_memory(struct ath10k *ar,
ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, hdrlen + txlen,
NULL, NULL);
if (ret) {
ath10k_warn("unable to write to the device (%d)\n",
ath10k_warn(ar, "unable to write to the device (%d)\n",
ret);
return ret;
}
@ -183,11 +183,11 @@ int ath10k_bmi_execute(struct ath10k *ar, u32 address, u32 param, u32 *result)
u32 resplen = sizeof(resp.execute);
int ret;
ath10k_dbg(ATH10K_DBG_BMI, "bmi execute address 0x%x param 0x%x\n",
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi execute address 0x%x param 0x%x\n",
address, param);
if (ar->bmi.done_sent) {
ath10k_warn("command disallowed\n");
ath10k_warn(ar, "command disallowed\n");
return -EBUSY;
}
@ -197,19 +197,19 @@ int ath10k_bmi_execute(struct ath10k *ar, u32 address, u32 param, u32 *result)
ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, cmdlen, &resp, &resplen);
if (ret) {
ath10k_warn("unable to read from the device\n");
ath10k_warn(ar, "unable to read from the device\n");
return ret;
}
if (resplen < sizeof(resp.execute)) {
ath10k_warn("invalid execute response length (%d)\n",
ath10k_warn(ar, "invalid execute response length (%d)\n",
resplen);
return -EIO;
}
*result = __le32_to_cpu(resp.execute.result);
ath10k_dbg(ATH10K_DBG_BMI, "bmi execute result 0x%x\n", *result);
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi execute result 0x%x\n", *result);
return 0;
}
@ -221,11 +221,11 @@ int ath10k_bmi_lz_data(struct ath10k *ar, const void *buffer, u32 length)
u32 txlen;
int ret;
ath10k_dbg(ATH10K_DBG_BMI, "bmi lz data buffer 0x%p length %d\n",
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi lz data buffer 0x%p length %d\n",
buffer, length);
if (ar->bmi.done_sent) {
ath10k_warn("command disallowed\n");
ath10k_warn(ar, "command disallowed\n");
return -EBUSY;
}
@ -241,7 +241,7 @@ int ath10k_bmi_lz_data(struct ath10k *ar, const void *buffer, u32 length)
ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, hdrlen + txlen,
NULL, NULL);
if (ret) {
ath10k_warn("unable to write to the device\n");
ath10k_warn(ar, "unable to write to the device\n");
return ret;
}
@ -258,11 +258,11 @@ int ath10k_bmi_lz_stream_start(struct ath10k *ar, u32 address)
u32 cmdlen = sizeof(cmd.id) + sizeof(cmd.lz_start);
int ret;
ath10k_dbg(ATH10K_DBG_BMI, "bmi lz stream start address 0x%x\n",
ath10k_dbg(ar, ATH10K_DBG_BMI, "bmi lz stream start address 0x%x\n",
address);
if (ar->bmi.done_sent) {
ath10k_warn("command disallowed\n");
ath10k_warn(ar, "command disallowed\n");
return -EBUSY;
}
@ -271,7 +271,7 @@ int ath10k_bmi_lz_stream_start(struct ath10k *ar, u32 address)
ret = ath10k_hif_exchange_bmi_msg(ar, &cmd, cmdlen, NULL, NULL);
if (ret) {
ath10k_warn("unable to Start LZ Stream to the device\n");
ath10k_warn(ar, "unable to Start LZ Stream to the device\n");
return ret;
}
@ -286,7 +286,7 @@ int ath10k_bmi_fast_download(struct ath10k *ar,
u32 trailer_len = length - head_len;
int ret;
ath10k_dbg(ATH10K_DBG_BMI,
ath10k_dbg(ar, ATH10K_DBG_BMI,
"bmi fast download address 0x%x buffer 0x%p length %d\n",
address, buffer, length);

View File

@ -284,13 +284,9 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
int ret = 0;
if (nbytes > ce_state->src_sz_max)
ath10k_warn("%s: send more we can (nbytes: %d, max: %d)\n",
ath10k_warn(ar, "%s: send more we can (nbytes: %d, max: %d)\n",
__func__, nbytes, ce_state->src_sz_max);
ret = ath10k_pci_wake(ar);
if (ret)
return ret;
if (unlikely(CE_RING_DELTA(nentries_mask,
write_index, sw_index - 1) <= 0)) {
ret = -ENOSR;
@ -325,7 +321,6 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
src_ring->write_index = write_index;
exit:
ath10k_pci_sleep(ar);
return ret;
}
@ -390,49 +385,57 @@ int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe)
return delta;
}
int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
void *per_recv_context,
u32 buffer)
int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe)
{
struct ath10k_ce_ring *dest_ring = ce_state->dest_ring;
u32 ctrl_addr = ce_state->ctrl_addr;
struct ath10k *ar = ce_state->ar;
struct ath10k *ar = pipe->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce_ring *dest_ring = pipe->dest_ring;
unsigned int nentries_mask = dest_ring->nentries_mask;
unsigned int write_index;
unsigned int sw_index;
unsigned int write_index = dest_ring->write_index;
unsigned int sw_index = dest_ring->sw_index;
lockdep_assert_held(&ar_pci->ce_lock);
return CE_RING_DELTA(nentries_mask, write_index, sw_index - 1);
}
int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)
{
struct ath10k *ar = pipe->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce_ring *dest_ring = pipe->dest_ring;
unsigned int nentries_mask = dest_ring->nentries_mask;
unsigned int write_index = dest_ring->write_index;
unsigned int sw_index = dest_ring->sw_index;
struct ce_desc *base = dest_ring->base_addr_owner_space;
struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index);
u32 ctrl_addr = pipe->ctrl_addr;
lockdep_assert_held(&ar_pci->ce_lock);
if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) == 0)
return -EIO;
desc->addr = __cpu_to_le32(paddr);
desc->nbytes = 0;
dest_ring->per_transfer_context[write_index] = ctx;
write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
dest_ring->write_index = write_index;
return 0;
}
int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr)
{
struct ath10k *ar = pipe->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
int ret;
spin_lock_bh(&ar_pci->ce_lock);
write_index = dest_ring->write_index;
sw_index = dest_ring->sw_index;
ret = ath10k_pci_wake(ar);
if (ret)
goto out;
if (CE_RING_DELTA(nentries_mask, write_index, sw_index - 1) > 0) {
struct ce_desc *base = dest_ring->base_addr_owner_space;
struct ce_desc *desc = CE_DEST_RING_TO_DESC(base, write_index);
/* Update destination descriptor */
desc->addr = __cpu_to_le32(buffer);
desc->nbytes = 0;
dest_ring->per_transfer_context[write_index] =
per_recv_context;
/* Update Destination Ring Write Index */
write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
ath10k_ce_dest_ring_write_index_set(ar, ctrl_addr, write_index);
dest_ring->write_index = write_index;
ret = 0;
} else {
ret = -EIO;
}
ath10k_pci_sleep(ar);
out:
ret = __ath10k_ce_rx_post_buf(pipe, ctx, paddr);
spin_unlock_bh(&ar_pci->ce_lock);
return ret;
@ -588,7 +591,6 @@ static int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
unsigned int sw_index = src_ring->sw_index;
struct ce_desc *sdesc, *sbase;
unsigned int read_index;
int ret;
if (src_ring->hw_index == sw_index) {
/*
@ -599,18 +601,12 @@ static int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
* value of the HW index has become stale.
*/
ret = ath10k_pci_wake(ar);
if (ret)
return ret;
read_index = ath10k_ce_src_ring_read_index_get(ar, ctrl_addr);
if (read_index == 0xffffffff)
return -ENODEV;
read_index &= nentries_mask;
src_ring->hw_index = read_index;
ath10k_pci_sleep(ar);
}
read_index = src_ring->hw_index;
@ -731,11 +727,6 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
u32 ctrl_addr = ce_state->ctrl_addr;
int ret;
ret = ath10k_pci_wake(ar);
if (ret)
return;
spin_lock_bh(&ar_pci->ce_lock);
@ -760,7 +751,6 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
ath10k_ce_engine_int_status_clear(ar, ctrl_addr, CE_WATERMARK_MASK);
spin_unlock_bh(&ar_pci->ce_lock);
ath10k_pci_sleep(ar);
}
/*
@ -771,13 +761,9 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
void ath10k_ce_per_engine_service_any(struct ath10k *ar)
{
int ce_id, ret;
int ce_id;
u32 intr_summary;
ret = ath10k_pci_wake(ar);
if (ret)
return;
intr_summary = CE_INTERRUPT_SUMMARY(ar);
for (ce_id = 0; intr_summary && (ce_id < CE_COUNT); ce_id++) {
@ -789,8 +775,6 @@ void ath10k_ce_per_engine_service_any(struct ath10k *ar)
ath10k_ce_per_engine_service(ar, ce_id);
}
ath10k_pci_sleep(ar);
}
/*
@ -800,16 +784,11 @@ void ath10k_ce_per_engine_service_any(struct ath10k *ar)
*
* Called with ce_lock held.
*/
static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state,
int disable_copy_compl_intr)
static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state)
{
u32 ctrl_addr = ce_state->ctrl_addr;
struct ath10k *ar = ce_state->ar;
int ret;
ret = ath10k_pci_wake(ar);
if (ret)
return;
bool disable_copy_compl_intr = ce_state->attr_flags & CE_ATTR_DIS_INTR;
if ((!disable_copy_compl_intr) &&
(ce_state->send_cb || ce_state->recv_cb))
@ -818,17 +797,11 @@ static void ath10k_ce_per_engine_handler_adjust(struct ath10k_ce_pipe *ce_state,
ath10k_ce_copy_complete_intr_disable(ar, ctrl_addr);
ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
ath10k_pci_sleep(ar);
}
int ath10k_ce_disable_interrupts(struct ath10k *ar)
{
int ce_id, ret;
ret = ath10k_pci_wake(ar);
if (ret)
return ret;
int ce_id;
for (ce_id = 0; ce_id < CE_COUNT; ce_id++) {
u32 ctrl_addr = ath10k_ce_base_address(ce_id);
@ -838,34 +811,16 @@ int ath10k_ce_disable_interrupts(struct ath10k *ar)
ath10k_ce_watermark_intr_disable(ar, ctrl_addr);
}
ath10k_pci_sleep(ar);
return 0;
}
void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
void (*send_cb)(struct ath10k_ce_pipe *),
int disable_interrupts)
void ath10k_ce_enable_interrupts(struct ath10k *ar)
{
struct ath10k *ar = ce_state->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
int ce_id;
spin_lock_bh(&ar_pci->ce_lock);
ce_state->send_cb = send_cb;
ath10k_ce_per_engine_handler_adjust(ce_state, disable_interrupts);
spin_unlock_bh(&ar_pci->ce_lock);
}
void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
void (*recv_cb)(struct ath10k_ce_pipe *))
{
struct ath10k *ar = ce_state->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
spin_lock_bh(&ar_pci->ce_lock);
ce_state->recv_cb = recv_cb;
ath10k_ce_per_engine_handler_adjust(ce_state, 0);
spin_unlock_bh(&ar_pci->ce_lock);
for (ce_id = 0; ce_id < CE_COUNT; ce_id++)
ath10k_ce_per_engine_handler_adjust(&ar_pci->ce_states[ce_id]);
}
static int ath10k_ce_init_src_ring(struct ath10k *ar,
@ -898,7 +853,7 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar,
ath10k_ce_src_ring_lowmark_set(ar, ctrl_addr, 0);
ath10k_ce_src_ring_highmark_set(ar, ctrl_addr, nentries);
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"boot init ce src ring id %d entries %d base_addr %p\n",
ce_id, nentries, src_ring->base_addr_owner_space);
@ -932,7 +887,7 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
ath10k_ce_dest_ring_lowmark_set(ar, ctrl_addr, 0);
ath10k_ce_dest_ring_highmark_set(ar, ctrl_addr, nentries);
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"boot ce dest ring id %d entries %d base_addr %p\n",
ce_id, nentries, dest_ring->base_addr_owner_space);
@ -1067,7 +1022,9 @@ ath10k_ce_alloc_dest_ring(struct ath10k *ar, unsigned int ce_id,
* initialized by software/firmware.
*/
int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
const struct ce_attr *attr)
const struct ce_attr *attr,
void (*send_cb)(struct ath10k_ce_pipe *),
void (*recv_cb)(struct ath10k_ce_pipe *))
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ath10k_ce_pipe *ce_state = &ar_pci->ce_states[ce_id];
@ -1084,39 +1041,37 @@ int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
BUILD_BUG_ON(2*TARGET_10X_NUM_MSDU_DESC >
(CE_HTT_H2T_MSG_SRC_NENTRIES - 1));
ret = ath10k_pci_wake(ar);
if (ret)
return ret;
spin_lock_bh(&ar_pci->ce_lock);
ce_state->ar = ar;
ce_state->id = ce_id;
ce_state->ctrl_addr = ath10k_ce_base_address(ce_id);
ce_state->attr_flags = attr->flags;
ce_state->src_sz_max = attr->src_sz_max;
if (attr->src_nentries)
ce_state->send_cb = send_cb;
if (attr->dest_nentries)
ce_state->recv_cb = recv_cb;
spin_unlock_bh(&ar_pci->ce_lock);
if (attr->src_nentries) {
ret = ath10k_ce_init_src_ring(ar, ce_id, attr);
if (ret) {
ath10k_err("Failed to initialize CE src ring for ID: %d (%d)\n",
ath10k_err(ar, "Failed to initialize CE src ring for ID: %d (%d)\n",
ce_id, ret);
goto out;
return ret;
}
}
if (attr->dest_nentries) {
ret = ath10k_ce_init_dest_ring(ar, ce_id, attr);
if (ret) {
ath10k_err("Failed to initialize CE dest ring for ID: %d (%d)\n",
ath10k_err(ar, "Failed to initialize CE dest ring for ID: %d (%d)\n",
ce_id, ret);
goto out;
return ret;
}
}
out:
ath10k_pci_sleep(ar);
return ret;
return 0;
}
static void ath10k_ce_deinit_src_ring(struct ath10k *ar, unsigned int ce_id)
@ -1140,16 +1095,8 @@ static void ath10k_ce_deinit_dest_ring(struct ath10k *ar, unsigned int ce_id)
void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id)
{
int ret;
ret = ath10k_pci_wake(ar);
if (ret)
return;
ath10k_ce_deinit_src_ring(ar, ce_id);
ath10k_ce_deinit_dest_ring(ar, ce_id);
ath10k_pci_sleep(ar);
}
int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
@ -1163,7 +1110,7 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
ce_state->src_ring = ath10k_ce_alloc_src_ring(ar, ce_id, attr);
if (IS_ERR(ce_state->src_ring)) {
ret = PTR_ERR(ce_state->src_ring);
ath10k_err("failed to allocate copy engine source ring %d: %d\n",
ath10k_err(ar, "failed to allocate copy engine source ring %d: %d\n",
ce_id, ret);
ce_state->src_ring = NULL;
return ret;
@ -1175,7 +1122,7 @@ int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
attr);
if (IS_ERR(ce_state->dest_ring)) {
ret = PTR_ERR(ce_state->dest_ring);
ath10k_err("failed to allocate copy engine destination ring %d: %d\n",
ath10k_err(ar, "failed to allocate copy engine destination ring %d: %d\n",
ce_id, ret);
ce_state->dest_ring = NULL;
return ret;

View File

@ -162,30 +162,13 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
void ath10k_ce_send_cb_register(struct ath10k_ce_pipe *ce_state,
void (*send_cb)(struct ath10k_ce_pipe *),
int disable_interrupts);
int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
/*==================Recv=======================*/
/*
* Make a buffer available to receive. The buffer must be at least of a
* minimal size appropriate for this copy engine (src_sz_max attribute).
* ce - which copy engine to use
* per_transfer_recv_context - context passed back to caller's recv_cb
* buffer - address of buffer in CE space
* Returns 0 on success; otherwise an error status.
*
* Implemenation note: Pushes a buffer to Dest ring.
*/
int ath10k_ce_recv_buf_enqueue(struct ath10k_ce_pipe *ce_state,
void *per_transfer_recv_context,
u32 buffer);
void ath10k_ce_recv_cb_register(struct ath10k_ce_pipe *ce_state,
void (*recv_cb)(struct ath10k_ce_pipe *));
int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
int __ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr);
int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx, u32 paddr);
/* recv flags */
/* Data is byte-swapped */
@ -214,7 +197,9 @@ int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
/*==================CE Engine Initialization=======================*/
int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
const struct ce_attr *attr);
const struct ce_attr *attr,
void (*send_cb)(struct ath10k_ce_pipe *),
void (*recv_cb)(struct ath10k_ce_pipe *));
void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
const struct ce_attr *attr);
@ -245,6 +230,7 @@ int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
void ath10k_ce_per_engine_service_any(struct ath10k *ar);
void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
int ath10k_ce_disable_interrupts(struct ath10k *ar);
void ath10k_ce_enable_interrupts(struct ath10k *ar);
/* ce_attr.flags values */
/* Use NonSnooping PCIe accesses? */

View File

@ -53,7 +53,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
static void ath10k_send_suspend_complete(struct ath10k *ar)
{
ath10k_dbg(ATH10K_DBG_BOOT, "boot suspend complete\n");
ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
complete(&ar->target_suspend);
}
@ -67,14 +67,14 @@ static int ath10k_init_configure_target(struct ath10k *ar)
ret = ath10k_bmi_write32(ar, hi_app_host_interest,
HTC_PROTOCOL_VERSION);
if (ret) {
ath10k_err("settings HTC version failed\n");
ath10k_err(ar, "settings HTC version failed\n");
return ret;
}
/* set the firmware mode to STA/IBSS/AP */
ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
if (ret) {
ath10k_err("setting firmware mode (1/2) failed\n");
ath10k_err(ar, "setting firmware mode (1/2) failed\n");
return ret;
}
@ -93,14 +93,14 @@ static int ath10k_init_configure_target(struct ath10k *ar)
ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
if (ret) {
ath10k_err("setting firmware mode (2/2) failed\n");
ath10k_err(ar, "setting firmware mode (2/2) failed\n");
return ret;
}
/* We do all byte-swapping on the host */
ret = ath10k_bmi_write32(ar, hi_be, 0);
if (ret) {
ath10k_err("setting host CPU BE mode failed\n");
ath10k_err(ar, "setting host CPU BE mode failed\n");
return ret;
}
@ -108,7 +108,7 @@ static int ath10k_init_configure_target(struct ath10k *ar)
ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
if (ret) {
ath10k_err("setting FW data/desc swap flags failed\n");
ath10k_err(ar, "setting FW data/desc swap flags failed\n");
return ret;
}
@ -146,11 +146,12 @@ static int ath10k_push_board_ext_data(struct ath10k *ar)
ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
if (ret) {
ath10k_err("could not read board ext data addr (%d)\n", ret);
ath10k_err(ar, "could not read board ext data addr (%d)\n",
ret);
return ret;
}
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"boot push board extended data addr 0x%x\n",
board_ext_data_addr);
@ -158,7 +159,7 @@ static int ath10k_push_board_ext_data(struct ath10k *ar)
return 0;
if (ar->board_len != (board_data_size + board_ext_data_size)) {
ath10k_err("invalid board (ext) data sizes %zu != %d+%d\n",
ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
ar->board_len, board_data_size, board_ext_data_size);
return -EINVAL;
}
@ -167,14 +168,15 @@ static int ath10k_push_board_ext_data(struct ath10k *ar)
ar->board_data + board_data_size,
board_ext_data_size);
if (ret) {
ath10k_err("could not write board ext data (%d)\n", ret);
ath10k_err(ar, "could not write board ext data (%d)\n", ret);
return ret;
}
ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
(board_ext_data_size << 16) | 1);
if (ret) {
ath10k_err("could not write board ext data bit (%d)\n", ret);
ath10k_err(ar, "could not write board ext data bit (%d)\n",
ret);
return ret;
}
@ -189,13 +191,13 @@ static int ath10k_download_board_data(struct ath10k *ar)
ret = ath10k_push_board_ext_data(ar);
if (ret) {
ath10k_err("could not push board ext data (%d)\n", ret);
ath10k_err(ar, "could not push board ext data (%d)\n", ret);
goto exit;
}
ret = ath10k_bmi_read32(ar, hi_board_data, &address);
if (ret) {
ath10k_err("could not read board data addr (%d)\n", ret);
ath10k_err(ar, "could not read board data addr (%d)\n", ret);
goto exit;
}
@ -203,13 +205,13 @@ static int ath10k_download_board_data(struct ath10k *ar)
min_t(u32, board_data_size,
ar->board_len));
if (ret) {
ath10k_err("could not write board data (%d)\n", ret);
ath10k_err(ar, "could not write board data (%d)\n", ret);
goto exit;
}
ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
if (ret) {
ath10k_err("could not write board data bit (%d)\n", ret);
ath10k_err(ar, "could not write board data bit (%d)\n", ret);
goto exit;
}
@ -225,30 +227,30 @@ static int ath10k_download_and_run_otp(struct ath10k *ar)
/* OTP is optional */
if (!ar->otp_data || !ar->otp_len) {
ath10k_warn("Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n",
ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n",
ar->otp_data, ar->otp_len);
return 0;
}
ath10k_dbg(ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
address, ar->otp_len);
ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len);
if (ret) {
ath10k_err("could not write otp (%d)\n", ret);
ath10k_err(ar, "could not write otp (%d)\n", ret);
return ret;
}
ret = ath10k_bmi_execute(ar, address, 0, &result);
if (ret) {
ath10k_err("could not execute otp (%d)\n", ret);
ath10k_err(ar, "could not execute otp (%d)\n", ret);
return ret;
}
ath10k_dbg(ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
if (result != 0) {
ath10k_err("otp calibration failed: %d", result);
ath10k_err(ar, "otp calibration failed: %d", result);
return -EINVAL;
}
@ -265,7 +267,7 @@ static int ath10k_download_fw(struct ath10k *ar)
ret = ath10k_bmi_fast_download(ar, address, ar->firmware_data,
ar->firmware_len);
if (ret) {
ath10k_err("could not write fw (%d)\n", ret);
ath10k_err(ar, "could not write fw (%d)\n", ret);
goto exit;
}
@ -302,12 +304,12 @@ static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar)
int ret = 0;
if (ar->hw_params.fw.fw == NULL) {
ath10k_err("firmware file not defined\n");
ath10k_err(ar, "firmware file not defined\n");
return -EINVAL;
}
if (ar->hw_params.fw.board == NULL) {
ath10k_err("board data file not defined");
ath10k_err(ar, "board data file not defined");
return -EINVAL;
}
@ -316,7 +318,7 @@ static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar)
ar->hw_params.fw.board);
if (IS_ERR(ar->board)) {
ret = PTR_ERR(ar->board);
ath10k_err("could not fetch board data (%d)\n", ret);
ath10k_err(ar, "could not fetch board data (%d)\n", ret);
goto err;
}
@ -328,7 +330,7 @@ static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar)
ar->hw_params.fw.fw);
if (IS_ERR(ar->firmware)) {
ret = PTR_ERR(ar->firmware);
ath10k_err("could not fetch firmware (%d)\n", ret);
ath10k_err(ar, "could not fetch firmware (%d)\n", ret);
goto err;
}
@ -344,7 +346,7 @@ static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar)
ar->hw_params.fw.otp);
if (IS_ERR(ar->otp)) {
ret = PTR_ERR(ar->otp);
ath10k_err("could not fetch otp (%d)\n", ret);
ath10k_err(ar, "could not fetch otp (%d)\n", ret);
goto err;
}
@ -369,7 +371,7 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
/* first fetch the firmware file (firmware-*.bin) */
ar->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, name);
if (IS_ERR(ar->firmware)) {
ath10k_err("could not fetch firmware file '%s/%s': %ld\n",
ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
ar->hw_params.fw.dir, name, PTR_ERR(ar->firmware));
return PTR_ERR(ar->firmware);
}
@ -381,14 +383,14 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
if (len < magic_len) {
ath10k_err("firmware file '%s/%s' too small to contain magic: %zu\n",
ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
ar->hw_params.fw.dir, name, len);
ret = -EINVAL;
goto err;
}
if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
ath10k_err("invalid firmware magic\n");
ath10k_err(ar, "invalid firmware magic\n");
ret = -EINVAL;
goto err;
}
@ -410,7 +412,7 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
data += sizeof(*hdr);
if (len < ie_len) {
ath10k_err("invalid length for FW IE %d (%zu < %zu)\n",
ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
ie_id, len, ie_len);
ret = -EINVAL;
goto err;
@ -424,7 +426,7 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
memcpy(ar->hw->wiphy->fw_version, data, ie_len);
ar->hw->wiphy->fw_version[ie_len] = '\0';
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"found fw version %s\n",
ar->hw->wiphy->fw_version);
break;
@ -434,11 +436,11 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
timestamp = (__le32 *)data;
ath10k_dbg(ATH10K_DBG_BOOT, "found fw timestamp %d\n",
ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
le32_to_cpup(timestamp));
break;
case ATH10K_FW_IE_FEATURES:
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"found firmware features ie (%zd B)\n",
ie_len);
@ -450,19 +452,19 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
break;
if (data[index] & (1 << bit)) {
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"Enabling feature bit: %i\n",
i);
__set_bit(i, ar->fw_features);
}
}
ath10k_dbg_dump(ATH10K_DBG_BOOT, "features", "",
ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
ar->fw_features,
sizeof(ar->fw_features));
break;
case ATH10K_FW_IE_FW_IMAGE:
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"found fw image ie (%zd B)\n",
ie_len);
@ -471,7 +473,7 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
break;
case ATH10K_FW_IE_OTP_IMAGE:
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"found otp image ie (%zd B)\n",
ie_len);
@ -480,7 +482,7 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
break;
default:
ath10k_warn("Unknown FW IE: %u\n",
ath10k_warn(ar, "Unknown FW IE: %u\n",
le32_to_cpu(hdr->id));
break;
}
@ -493,15 +495,22 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
}
if (!ar->firmware_data || !ar->firmware_len) {
ath10k_warn("No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
ar->hw_params.fw.dir, name);
ret = -ENOMEDIUM;
goto err;
}
if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features) &&
!test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
ret = -EINVAL;
goto err;
}
/* now fetch the board file */
if (ar->hw_params.fw.board == NULL) {
ath10k_err("board data file not defined");
ath10k_err(ar, "board data file not defined");
ret = -EINVAL;
goto err;
}
@ -511,7 +520,7 @@ static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
ar->hw_params.fw.board);
if (IS_ERR(ar->board)) {
ret = PTR_ERR(ar->board);
ath10k_err("could not fetch board data '%s/%s' (%d)\n",
ath10k_err(ar, "could not fetch board data '%s/%s' (%d)\n",
ar->hw_params.fw.dir, ar->hw_params.fw.board,
ret);
goto err;
@ -531,22 +540,29 @@ static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
{
int ret;
ar->fw_api = 3;
ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE);
if (ret == 0)
goto success;
ar->fw_api = 2;
ath10k_dbg(ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE);
if (ret == 0)
goto success;
ar->fw_api = 1;
ath10k_dbg(ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
ret = ath10k_core_fetch_firmware_api_1(ar);
if (ret)
return ret;
success:
ath10k_dbg(ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
return 0;
}
@ -557,19 +573,19 @@ static int ath10k_init_download_firmware(struct ath10k *ar)
ret = ath10k_download_board_data(ar);
if (ret) {
ath10k_err("failed to download board data: %d\n", ret);
ath10k_err(ar, "failed to download board data: %d\n", ret);
return ret;
}
ret = ath10k_download_and_run_otp(ar);
if (ret) {
ath10k_err("failed to run otp: %d\n", ret);
ath10k_err(ar, "failed to run otp: %d\n", ret);
return ret;
}
ret = ath10k_download_fw(ar);
if (ret) {
ath10k_err("failed to download firmware: %d\n", ret);
ath10k_err(ar, "failed to download firmware: %d\n", ret);
return ret;
}
@ -586,7 +602,7 @@ static int ath10k_init_uart(struct ath10k *ar)
*/
ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
if (ret) {
ath10k_warn("could not disable UART prints (%d)\n", ret);
ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
return ret;
}
@ -595,24 +611,24 @@ static int ath10k_init_uart(struct ath10k *ar)
ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, 7);
if (ret) {
ath10k_warn("could not enable UART prints (%d)\n", ret);
ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
return ret;
}
ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
if (ret) {
ath10k_warn("could not enable UART prints (%d)\n", ret);
ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
return ret;
}
/* Set the UART baud rate to 19200. */
ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
if (ret) {
ath10k_warn("could not set the baud rate (%d)\n", ret);
ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
return ret;
}
ath10k_info("UART prints enabled\n");
ath10k_info(ar, "UART prints enabled\n");
return 0;
}
@ -629,14 +645,14 @@ static int ath10k_init_hw_params(struct ath10k *ar)
}
if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
ath10k_err("Unsupported hardware version: 0x%x\n",
ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
ar->target_version);
return -EINVAL;
}
ar->hw_params = *hw_params;
ath10k_dbg(ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
ar->hw_params.name, ar->target_version);
return 0;
@ -651,14 +667,14 @@ static void ath10k_core_restart(struct work_struct *work)
switch (ar->state) {
case ATH10K_STATE_ON:
ar->state = ATH10K_STATE_RESTARTING;
del_timer_sync(&ar->scan.timeout);
ath10k_reset_scan((unsigned long)ar);
ath10k_hif_stop(ar);
ath10k_scan_finish(ar);
ieee80211_restart_hw(ar->hw);
break;
case ATH10K_STATE_OFF:
/* this can happen if driver is being unloaded
* or if the crash happens during FW probing */
ath10k_warn("cannot restart a device that hasn't been started\n");
ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
break;
case ATH10K_STATE_RESTARTING:
/* hw restart might be requested from multiple places */
@ -667,7 +683,7 @@ static void ath10k_core_restart(struct work_struct *work)
ar->state = ATH10K_STATE_WEDGED;
/* fall through */
case ATH10K_STATE_WEDGED:
ath10k_warn("device is wedged, will not restart\n");
ath10k_warn(ar, "device is wedged, will not restart\n");
break;
}
@ -700,7 +716,7 @@ int ath10k_core_start(struct ath10k *ar)
status = ath10k_htc_init(ar);
if (status) {
ath10k_err("could not init HTC (%d)\n", status);
ath10k_err(ar, "could not init HTC (%d)\n", status);
goto err;
}
@ -710,90 +726,91 @@ int ath10k_core_start(struct ath10k *ar)
status = ath10k_wmi_attach(ar);
if (status) {
ath10k_err("WMI attach failed: %d\n", status);
ath10k_err(ar, "WMI attach failed: %d\n", status);
goto err;
}
status = ath10k_htt_init(ar);
if (status) {
ath10k_err("failed to init htt: %d\n", status);
ath10k_err(ar, "failed to init htt: %d\n", status);
goto err_wmi_detach;
}
status = ath10k_htt_tx_alloc(&ar->htt);
if (status) {
ath10k_err("failed to alloc htt tx: %d\n", status);
ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
goto err_wmi_detach;
}
status = ath10k_htt_rx_alloc(&ar->htt);
if (status) {
ath10k_err("failed to alloc htt rx: %d\n", status);
ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
goto err_htt_tx_detach;
}
status = ath10k_hif_start(ar);
if (status) {
ath10k_err("could not start HIF: %d\n", status);
ath10k_err(ar, "could not start HIF: %d\n", status);
goto err_htt_rx_detach;
}
status = ath10k_htc_wait_target(&ar->htc);
if (status) {
ath10k_err("failed to connect to HTC: %d\n", status);
ath10k_err(ar, "failed to connect to HTC: %d\n", status);
goto err_hif_stop;
}
status = ath10k_htt_connect(&ar->htt);
if (status) {
ath10k_err("failed to connect htt (%d)\n", status);
ath10k_err(ar, "failed to connect htt (%d)\n", status);
goto err_hif_stop;
}
status = ath10k_wmi_connect(ar);
if (status) {
ath10k_err("could not connect wmi: %d\n", status);
ath10k_err(ar, "could not connect wmi: %d\n", status);
goto err_hif_stop;
}
status = ath10k_htc_start(&ar->htc);
if (status) {
ath10k_err("failed to start htc: %d\n", status);
ath10k_err(ar, "failed to start htc: %d\n", status);
goto err_hif_stop;
}
status = ath10k_wmi_wait_for_service_ready(ar);
if (status <= 0) {
ath10k_warn("wmi service ready event not received");
ath10k_warn(ar, "wmi service ready event not received");
status = -ETIMEDOUT;
goto err_htc_stop;
goto err_hif_stop;
}
ath10k_dbg(ATH10K_DBG_BOOT, "firmware %s booted\n",
ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
ar->hw->wiphy->fw_version);
status = ath10k_wmi_cmd_init(ar);
if (status) {
ath10k_err("could not send WMI init command (%d)\n", status);
goto err_htc_stop;
ath10k_err(ar, "could not send WMI init command (%d)\n",
status);
goto err_hif_stop;
}
status = ath10k_wmi_wait_for_unified_ready(ar);
if (status <= 0) {
ath10k_err("wmi unified ready event not received\n");
ath10k_err(ar, "wmi unified ready event not received\n");
status = -ETIMEDOUT;
goto err_htc_stop;
goto err_hif_stop;
}
status = ath10k_htt_setup(&ar->htt);
if (status) {
ath10k_err("failed to setup htt: %d\n", status);
goto err_htc_stop;
ath10k_err(ar, "failed to setup htt: %d\n", status);
goto err_hif_stop;
}
status = ath10k_debug_start(ar);
if (status)
goto err_htc_stop;
goto err_hif_stop;
if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features))
ar->free_vdev_map = (1 << TARGET_10X_NUM_VDEVS) - 1;
@ -802,28 +819,8 @@ int ath10k_core_start(struct ath10k *ar)
INIT_LIST_HEAD(&ar->arvifs);
if (!test_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags)) {
ath10k_info("%s (0x%08x, 0x%08x) fw %s api %d htt %d.%d\n",
ar->hw_params.name,
ar->target_version,
ar->chip_id,
ar->hw->wiphy->fw_version,
ar->fw_api,
ar->htt.target_version_major,
ar->htt.target_version_minor);
ath10k_info("debug %d debugfs %d tracing %d dfs %d\n",
config_enabled(CONFIG_ATH10K_DEBUG),
config_enabled(CONFIG_ATH10K_DEBUGFS),
config_enabled(CONFIG_ATH10K_TRACING),
config_enabled(CONFIG_ATH10K_DFS_CERTIFIED));
}
__set_bit(ATH10K_FLAG_FIRST_BOOT_DONE, &ar->dev_flags);
return 0;
err_htc_stop:
ath10k_htc_stop(&ar->htc);
err_hif_stop:
ath10k_hif_stop(ar);
err_htt_rx_detach:
@ -845,14 +842,14 @@ int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
if (ret) {
ath10k_warn("could not suspend target (%d)\n", ret);
ath10k_warn(ar, "could not suspend target (%d)\n", ret);
return ret;
}
ret = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
if (ret == 0) {
ath10k_warn("suspend timed out - target pause event never came\n");
ath10k_warn(ar, "suspend timed out - target pause event never came\n");
return -ETIMEDOUT;
}
@ -868,7 +865,6 @@ void ath10k_core_stop(struct ath10k *ar)
ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
ath10k_debug_stop(ar);
ath10k_htc_stop(&ar->htc);
ath10k_hif_stop(ar);
ath10k_htt_tx_free(&ar->htt);
ath10k_htt_rx_free(&ar->htt);
@ -887,14 +883,14 @@ static int ath10k_core_probe_fw(struct ath10k *ar)
ret = ath10k_hif_power_up(ar);
if (ret) {
ath10k_err("could not start pci hif (%d)\n", ret);
ath10k_err(ar, "could not start pci hif (%d)\n", ret);
return ret;
}
memset(&target_info, 0, sizeof(target_info));
ret = ath10k_bmi_get_target_info(ar, &target_info);
if (ret) {
ath10k_err("could not get target info (%d)\n", ret);
ath10k_err(ar, "could not get target info (%d)\n", ret);
ath10k_hif_power_down(ar);
return ret;
}
@ -904,14 +900,14 @@ static int ath10k_core_probe_fw(struct ath10k *ar)
ret = ath10k_init_hw_params(ar);
if (ret) {
ath10k_err("could not get hw params (%d)\n", ret);
ath10k_err(ar, "could not get hw params (%d)\n", ret);
ath10k_hif_power_down(ar);
return ret;
}
ret = ath10k_core_fetch_firmware_files(ar);
if (ret) {
ath10k_err("could not fetch firmware files (%d)\n", ret);
ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
ath10k_hif_power_down(ar);
return ret;
}
@ -920,13 +916,14 @@ static int ath10k_core_probe_fw(struct ath10k *ar)
ret = ath10k_core_start(ar);
if (ret) {
ath10k_err("could not init core (%d)\n", ret);
ath10k_err(ar, "could not init core (%d)\n", ret);
ath10k_core_free_firmware_files(ar);
ath10k_hif_power_down(ar);
mutex_unlock(&ar->conf_mutex);
return ret;
}
ath10k_print_driver_info(ar);
ath10k_core_stop(ar);
mutex_unlock(&ar->conf_mutex);
@ -939,7 +936,7 @@ static int ath10k_core_check_chip_id(struct ath10k *ar)
{
u32 hw_revision = MS(ar->chip_id, SOC_CHIP_ID_REV);
ath10k_dbg(ATH10K_DBG_BOOT, "boot chip_id 0x%08x hw_revision 0x%x\n",
ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot chip_id 0x%08x hw_revision 0x%x\n",
ar->chip_id, hw_revision);
/* Check that we are not using hw1.0 (some of them have same pci id
@ -947,7 +944,7 @@ static int ath10k_core_check_chip_id(struct ath10k *ar)
* due to missing hw1.0 workarounds. */
switch (hw_revision) {
case QCA988X_HW_1_0_CHIP_ID_REV:
ath10k_err("ERROR: qca988x hw1.0 is not supported\n");
ath10k_err(ar, "ERROR: qca988x hw1.0 is not supported\n");
return -EOPNOTSUPP;
case QCA988X_HW_2_0_CHIP_ID_REV:
@ -955,7 +952,7 @@ static int ath10k_core_check_chip_id(struct ath10k *ar)
return 0;
default:
ath10k_warn("Warning: hardware revision unknown (0x%x), expect problems\n",
ath10k_warn(ar, "Warning: hardware revision unknown (0x%x), expect problems\n",
ar->chip_id);
return 0;
}
@ -970,25 +967,33 @@ static void ath10k_core_register_work(struct work_struct *work)
status = ath10k_core_probe_fw(ar);
if (status) {
ath10k_err("could not probe fw (%d)\n", status);
ath10k_err(ar, "could not probe fw (%d)\n", status);
goto err;
}
status = ath10k_mac_register(ar);
if (status) {
ath10k_err("could not register to mac80211 (%d)\n", status);
ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
goto err_release_fw;
}
status = ath10k_debug_create(ar);
if (status) {
ath10k_err("unable to initialize debugfs\n");
ath10k_err(ar, "unable to initialize debugfs\n");
goto err_unregister_mac;
}
status = ath10k_spectral_create(ar);
if (status) {
ath10k_err(ar, "failed to initialize spectral\n");
goto err_debug_destroy;
}
set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
return;
err_debug_destroy:
ath10k_debug_destroy(ar);
err_unregister_mac:
ath10k_mac_unregister(ar);
err_release_fw:
@ -1008,7 +1013,7 @@ int ath10k_core_register(struct ath10k *ar, u32 chip_id)
status = ath10k_core_check_chip_id(ar);
if (status) {
ath10k_err("Unsupported chip id 0x%08x\n", ar->chip_id);
ath10k_err(ar, "Unsupported chip id 0x%08x\n", ar->chip_id);
return status;
}
@ -1025,6 +1030,12 @@ void ath10k_core_unregister(struct ath10k *ar)
if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
return;
/* Stop spectral before unregistering from mac80211 to remove the
* relayfs debugfs file cleanly. Otherwise the parent debugfs tree
* would be already be free'd recursively, leading to a double free.
*/
ath10k_spectral_destroy(ar);
/* We must unregister from mac80211 before we stop HTC and HIF.
* Otherwise we will fail to submit commands to FW and mac80211 will be
* unhappy about callback failures. */
@ -1036,12 +1047,12 @@ void ath10k_core_unregister(struct ath10k *ar)
}
EXPORT_SYMBOL(ath10k_core_unregister);
struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
const struct ath10k_hif_ops *hif_ops)
{
struct ath10k *ar;
ar = ath10k_mac_create();
ar = ath10k_mac_create(priv_size);
if (!ar)
return NULL;
@ -1051,7 +1062,6 @@ struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
ar->p2p = !!ath10k_p2p;
ar->dev = dev;
ar->hif.priv = hif_priv;
ar->hif.ops = hif_ops;
init_completion(&ar->scan.started);
@ -1062,7 +1072,7 @@ struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
init_completion(&ar->install_key_done);
init_completion(&ar->vdev_setup_done);
setup_timer(&ar->scan.timeout, ath10k_reset_scan, (unsigned long)ar);
INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
ar->workqueue = create_singlethread_workqueue("ath10k_wq");
if (!ar->workqueue)

View File

@ -22,6 +22,8 @@
#include <linux/if_ether.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/uuid.h>
#include <linux/time.h>
#include "htt.h"
#include "htc.h"
@ -31,6 +33,7 @@
#include "../ath.h"
#include "../regd.h"
#include "../dfs_pattern_detector.h"
#include "spectral.h"
#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
@ -237,6 +240,7 @@ struct ath10k_vif {
bool is_started;
bool is_up;
bool spectral_enabled;
u32 aid;
u8 bssid[ETH_ALEN];
@ -276,11 +280,20 @@ struct ath10k_vif_iter {
struct ath10k_vif *arvif;
};
/* used for crash-dump storage, protected by data-lock */
struct ath10k_fw_crash_data {
bool crashed_since_read;
uuid_le uuid;
struct timespec timestamp;
__le32 registers[REG_DUMP_COUNT_QCA988X];
};
struct ath10k_debug {
struct dentry *debugfs_phy;
struct ath10k_target_stats target_stats;
u32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE];
DECLARE_BITMAP(wmi_service_bitmap, WMI_SERVICE_BM_SIZE);
struct completion event_stats_compl;
@ -293,6 +306,8 @@ struct ath10k_debug {
u8 htt_max_amsdu;
u8 htt_max_ampdu;
struct ath10k_fw_crash_data *fw_crash_data;
};
enum ath10k_state {
@ -330,6 +345,11 @@ enum ath10k_fw_features {
/* Firmware does not support P2P */
ATH10K_FW_FEATURE_NO_P2P = 3,
/* Firmware 10.2 feature bit. The ATH10K_FW_FEATURE_WMI_10X feature bit
* is required to be set as well.
*/
ATH10K_FW_FEATURE_WMI_10_2 = 4,
/* keep last */
ATH10K_FW_FEATURE_COUNT,
};
@ -337,10 +357,32 @@ enum ath10k_fw_features {
enum ath10k_dev_flags {
/* Indicates that ath10k device is during CAC phase of DFS */
ATH10K_CAC_RUNNING,
ATH10K_FLAG_FIRST_BOOT_DONE,
ATH10K_FLAG_CORE_REGISTERED,
};
enum ath10k_scan_state {
ATH10K_SCAN_IDLE,
ATH10K_SCAN_STARTING,
ATH10K_SCAN_RUNNING,
ATH10K_SCAN_ABORTING,
};
static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
{
switch (state) {
case ATH10K_SCAN_IDLE:
return "idle";
case ATH10K_SCAN_STARTING:
return "starting";
case ATH10K_SCAN_RUNNING:
return "running";
case ATH10K_SCAN_ABORTING:
return "aborting";
}
return "unknown";
}
struct ath10k {
struct ath_common ath_common;
struct ieee80211_hw *hw;
@ -368,7 +410,6 @@ struct ath10k {
bool p2p;
struct {
void *priv;
const struct ath10k_hif_ops *ops;
} hif;
@ -410,10 +451,9 @@ struct ath10k {
struct completion started;
struct completion completed;
struct completion on_channel;
struct timer_list timeout;
struct delayed_work timeout;
enum ath10k_scan_state state;
bool is_roc;
bool in_progress;
bool aborting;
int vdev_id;
int roc_freq;
} scan;
@ -494,9 +534,21 @@ struct ath10k {
#ifdef CONFIG_ATH10K_DEBUGFS
struct ath10k_debug debug;
#endif
struct {
/* relay(fs) channel for spectral scan */
struct rchan *rfs_chan_spec_scan;
/* spectral_mode and spec_config are protected by conf_mutex */
enum ath10k_spectral_mode mode;
struct ath10k_spec_scan config;
} spectral;
/* must be last */
u8 drv_priv[0] __aligned(sizeof(void *));
};
struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
const struct ath10k_hif_ops *hif_ops);
void ath10k_core_destroy(struct ath10k *ar);

View File

@ -17,6 +17,9 @@
#include <linux/module.h>
#include <linux/debugfs.h>
#include <linux/version.h>
#include <linux/vermagic.h>
#include <linux/vmalloc.h>
#include "core.h"
#include "debug.h"
@ -24,25 +27,86 @@
/* ms */
#define ATH10K_DEBUG_HTT_STATS_INTERVAL 1000
static int ath10k_printk(const char *level, const char *fmt, ...)
{
struct va_format vaf;
va_list args;
int rtn;
#define ATH10K_FW_CRASH_DUMP_VERSION 1
va_start(args, fmt);
/**
* enum ath10k_fw_crash_dump_type - types of data in the dump file
* @ATH10K_FW_CRASH_DUMP_REGDUMP: Register crash dump in binary format
*/
enum ath10k_fw_crash_dump_type {
ATH10K_FW_CRASH_DUMP_REGISTERS = 0,
vaf.fmt = fmt;
vaf.va = &args;
ATH10K_FW_CRASH_DUMP_MAX,
};
rtn = printk("%sath10k: %pV", level, &vaf);
struct ath10k_tlv_dump_data {
/* see ath10k_fw_crash_dump_type above */
__le32 type;
va_end(args);
/* in bytes */
__le32 tlv_len;
return rtn;
}
/* pad to 32-bit boundaries as needed */
u8 tlv_data[];
} __packed;
int ath10k_info(const char *fmt, ...)
struct ath10k_dump_file_data {
/* dump file information */
/* "ATH10K-FW-DUMP" */
char df_magic[16];
__le32 len;
/* file dump version */
__le32 version;
/* some info we can get from ath10k struct that might help */
u8 uuid[16];
__le32 chip_id;
/* 0 for now, in place for later hardware */
__le32 bus_type;
__le32 target_version;
__le32 fw_version_major;
__le32 fw_version_minor;
__le32 fw_version_release;
__le32 fw_version_build;
__le32 phy_capability;
__le32 hw_min_tx_power;
__le32 hw_max_tx_power;
__le32 ht_cap_info;
__le32 vht_cap_info;
__le32 num_rf_chains;
/* firmware version string */
char fw_ver[ETHTOOL_FWVERS_LEN];
/* Kernel related information */
/* time-of-day stamp */
__le64 tv_sec;
/* time-of-day stamp, nano-seconds */
__le64 tv_nsec;
/* LINUX_VERSION_CODE */
__le32 kernel_ver_code;
/* VERMAGIC_STRING */
char kernel_ver[64];
/* room for growth w/out changing binary format */
u8 unused[128];
/* struct ath10k_tlv_dump_data + more */
u8 data[0];
} __packed;
int ath10k_info(struct ath10k *ar, const char *fmt, ...)
{
struct va_format vaf = {
.fmt = fmt,
@ -52,7 +116,7 @@ int ath10k_info(const char *fmt, ...)
va_start(args, fmt);
vaf.va = &args;
ret = ath10k_printk(KERN_INFO, "%pV", &vaf);
ret = dev_info(ar->dev, "%pV", &vaf);
trace_ath10k_log_info(&vaf);
va_end(args);
@ -60,7 +124,25 @@ int ath10k_info(const char *fmt, ...)
}
EXPORT_SYMBOL(ath10k_info);
int ath10k_err(const char *fmt, ...)
void ath10k_print_driver_info(struct ath10k *ar)
{
ath10k_info(ar, "%s (0x%08x, 0x%08x) fw %s api %d htt %d.%d\n",
ar->hw_params.name,
ar->target_version,
ar->chip_id,
ar->hw->wiphy->fw_version,
ar->fw_api,
ar->htt.target_version_major,
ar->htt.target_version_minor);
ath10k_info(ar, "debug %d debugfs %d tracing %d dfs %d\n",
config_enabled(CONFIG_ATH10K_DEBUG),
config_enabled(CONFIG_ATH10K_DEBUGFS),
config_enabled(CONFIG_ATH10K_TRACING),
config_enabled(CONFIG_ATH10K_DFS_CERTIFIED));
}
EXPORT_SYMBOL(ath10k_print_driver_info);
int ath10k_err(struct ath10k *ar, const char *fmt, ...)
{
struct va_format vaf = {
.fmt = fmt,
@ -70,7 +152,7 @@ int ath10k_err(const char *fmt, ...)
va_start(args, fmt);
vaf.va = &args;
ret = ath10k_printk(KERN_ERR, "%pV", &vaf);
ret = dev_err(ar->dev, "%pV", &vaf);
trace_ath10k_log_err(&vaf);
va_end(args);
@ -78,25 +160,21 @@ int ath10k_err(const char *fmt, ...)
}
EXPORT_SYMBOL(ath10k_err);
int ath10k_warn(const char *fmt, ...)
int ath10k_warn(struct ath10k *ar, const char *fmt, ...)
{
struct va_format vaf = {
.fmt = fmt,
};
va_list args;
int ret = 0;
va_start(args, fmt);
vaf.va = &args;
if (net_ratelimit())
ret = ath10k_printk(KERN_WARNING, "%pV", &vaf);
dev_warn_ratelimited(ar->dev, "%pV", &vaf);
trace_ath10k_log_warn(&vaf);
va_end(args);
return ret;
return 0;
}
EXPORT_SYMBOL(ath10k_warn);
@ -115,9 +193,10 @@ static ssize_t ath10k_read_wmi_services(struct file *file,
{
struct ath10k *ar = file->private_data;
char *buf;
unsigned int len = 0, buf_len = 1500;
const char *status;
unsigned int len = 0, buf_len = 4096;
const char *name;
ssize_t ret_cnt;
bool enabled;
int i;
buf = kzalloc(buf_len, GFP_KERNEL);
@ -129,15 +208,22 @@ static ssize_t ath10k_read_wmi_services(struct file *file,
if (len > buf_len)
len = buf_len;
for (i = 0; i < WMI_SERVICE_LAST; i++) {
if (WMI_SERVICE_IS_ENABLED(ar->debug.wmi_service_bitmap, i))
status = "enabled";
else
status = "disabled";
for (i = 0; i < WMI_MAX_SERVICE; i++) {
enabled = test_bit(i, ar->debug.wmi_service_bitmap);
name = wmi_service_name(i);
if (!name) {
if (enabled)
len += scnprintf(buf + len, buf_len - len,
"%-40s %s (bit %d)\n",
"unknown", "enabled", i);
continue;
}
len += scnprintf(buf + len, buf_len - len,
"0x%02x - %20s - %s\n",
i, wmi_service_name(i), status);
"%-40s %s\n",
name, enabled ? "enabled" : "-");
}
ret_cnt = simple_read_from_buffer(user_buf, count, ppos, buf, len);
@ -309,7 +395,7 @@ static ssize_t ath10k_read_fw_stats(struct file *file, char __user *user_buf,
ret = ath10k_wmi_request_stats(ar, WMI_REQUEST_PEER_STAT);
if (ret) {
ath10k_warn("could not request stats (%d)\n", ret);
ath10k_warn(ar, "could not request stats (%d)\n", ret);
goto exit;
}
@ -527,11 +613,14 @@ static ssize_t ath10k_write_simulate_fw_crash(struct file *file,
}
if (!strcmp(buf, "soft")) {
ath10k_info("simulating soft firmware crash\n");
ath10k_info(ar, "simulating soft firmware crash\n");
ret = ath10k_wmi_force_fw_hang(ar, WMI_FORCE_FW_HANG_ASSERT, 0);
} else if (!strcmp(buf, "hard")) {
ath10k_info("simulating hard firmware crash\n");
ret = ath10k_wmi_vdev_set_param(ar, TARGET_NUM_VDEVS + 1,
ath10k_info(ar, "simulating hard firmware crash\n");
/* 0x7fff is vdev id, and it is always out of range for all
* firmware variants in order to force a firmware crash.
*/
ret = ath10k_wmi_vdev_set_param(ar, 0x7fff,
ar->wmi.vdev_param->rts_threshold, 0);
} else {
ret = -EINVAL;
@ -539,7 +628,7 @@ static ssize_t ath10k_write_simulate_fw_crash(struct file *file,
}
if (ret) {
ath10k_warn("failed to simulate firmware crash: %d\n", ret);
ath10k_warn(ar, "failed to simulate firmware crash: %d\n", ret);
goto exit;
}
@ -577,6 +666,138 @@ static const struct file_operations fops_chip_id = {
.llseek = default_llseek,
};
struct ath10k_fw_crash_data *
ath10k_debug_get_new_fw_crash_data(struct ath10k *ar)
{
struct ath10k_fw_crash_data *crash_data = ar->debug.fw_crash_data;
lockdep_assert_held(&ar->data_lock);
crash_data->crashed_since_read = true;
uuid_le_gen(&crash_data->uuid);
getnstimeofday(&crash_data->timestamp);
return crash_data;
}
EXPORT_SYMBOL(ath10k_debug_get_new_fw_crash_data);
static struct ath10k_dump_file_data *ath10k_build_dump_file(struct ath10k *ar)
{
struct ath10k_fw_crash_data *crash_data = ar->debug.fw_crash_data;
struct ath10k_dump_file_data *dump_data;
struct ath10k_tlv_dump_data *dump_tlv;
int hdr_len = sizeof(*dump_data);
unsigned int len, sofar = 0;
unsigned char *buf;
len = hdr_len;
len += sizeof(*dump_tlv) + sizeof(crash_data->registers);
sofar += hdr_len;
/* This is going to get big when we start dumping FW RAM and such,
* so go ahead and use vmalloc.
*/
buf = vzalloc(len);
if (!buf)
return NULL;
spin_lock_bh(&ar->data_lock);
if (!crash_data->crashed_since_read) {
spin_unlock_bh(&ar->data_lock);
vfree(buf);
return NULL;
}
dump_data = (struct ath10k_dump_file_data *)(buf);
strlcpy(dump_data->df_magic, "ATH10K-FW-DUMP",
sizeof(dump_data->df_magic));
dump_data->len = cpu_to_le32(len);
dump_data->version = cpu_to_le32(ATH10K_FW_CRASH_DUMP_VERSION);
memcpy(dump_data->uuid, &crash_data->uuid, sizeof(dump_data->uuid));
dump_data->chip_id = cpu_to_le32(ar->chip_id);
dump_data->bus_type = cpu_to_le32(0);
dump_data->target_version = cpu_to_le32(ar->target_version);
dump_data->fw_version_major = cpu_to_le32(ar->fw_version_major);
dump_data->fw_version_minor = cpu_to_le32(ar->fw_version_minor);
dump_data->fw_version_release = cpu_to_le32(ar->fw_version_release);
dump_data->fw_version_build = cpu_to_le32(ar->fw_version_build);
dump_data->phy_capability = cpu_to_le32(ar->phy_capability);
dump_data->hw_min_tx_power = cpu_to_le32(ar->hw_min_tx_power);
dump_data->hw_max_tx_power = cpu_to_le32(ar->hw_max_tx_power);
dump_data->ht_cap_info = cpu_to_le32(ar->ht_cap_info);
dump_data->vht_cap_info = cpu_to_le32(ar->vht_cap_info);
dump_data->num_rf_chains = cpu_to_le32(ar->num_rf_chains);
strlcpy(dump_data->fw_ver, ar->hw->wiphy->fw_version,
sizeof(dump_data->fw_ver));
dump_data->kernel_ver_code = cpu_to_le32(LINUX_VERSION_CODE);
strlcpy(dump_data->kernel_ver, VERMAGIC_STRING,
sizeof(dump_data->kernel_ver));
dump_data->tv_sec = cpu_to_le64(crash_data->timestamp.tv_sec);
dump_data->tv_nsec = cpu_to_le64(crash_data->timestamp.tv_nsec);
/* Gather crash-dump */
dump_tlv = (struct ath10k_tlv_dump_data *)(buf + sofar);
dump_tlv->type = cpu_to_le32(ATH10K_FW_CRASH_DUMP_REGISTERS);
dump_tlv->tlv_len = cpu_to_le32(sizeof(crash_data->registers));
memcpy(dump_tlv->tlv_data, &crash_data->registers,
sizeof(crash_data->registers));
sofar += sizeof(*dump_tlv) + sizeof(crash_data->registers);
ar->debug.fw_crash_data->crashed_since_read = false;
spin_unlock_bh(&ar->data_lock);
return dump_data;
}
static int ath10k_fw_crash_dump_open(struct inode *inode, struct file *file)
{
struct ath10k *ar = inode->i_private;
struct ath10k_dump_file_data *dump;
dump = ath10k_build_dump_file(ar);
if (!dump)
return -ENODATA;
file->private_data = dump;
return 0;
}
static ssize_t ath10k_fw_crash_dump_read(struct file *file,
char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath10k_dump_file_data *dump_file = file->private_data;
return simple_read_from_buffer(user_buf, count, ppos,
dump_file,
le32_to_cpu(dump_file->len));
}
static int ath10k_fw_crash_dump_release(struct inode *inode,
struct file *file)
{
vfree(file->private_data);
return 0;
}
static const struct file_operations fops_fw_crash_dump = {
.open = ath10k_fw_crash_dump_open,
.read = ath10k_fw_crash_dump_read,
.release = ath10k_fw_crash_dump_release,
.owner = THIS_MODULE,
.llseek = default_llseek,
};
static int ath10k_debug_htt_stats_req(struct ath10k *ar)
{
u64 cookie;
@ -596,7 +817,7 @@ static int ath10k_debug_htt_stats_req(struct ath10k *ar)
ret = ath10k_htt_h2t_stats_req(&ar->htt, ar->debug.htt_stats_mask,
cookie);
if (ret) {
ath10k_warn("failed to send htt stats request: %d\n", ret);
ath10k_warn(ar, "failed to send htt stats request: %d\n", ret);
return ret;
}
@ -770,7 +991,7 @@ static ssize_t ath10k_write_fw_dbglog(struct file *file,
if (ar->state == ATH10K_STATE_ON) {
ret = ath10k_wmi_dbglog_cfg(ar, ar->debug.fw_dbglog_mask);
if (ret) {
ath10k_warn("dbglog cfg failed from debugfs: %d\n",
ath10k_warn(ar, "dbglog cfg failed from debugfs: %d\n",
ret);
goto exit;
}
@ -801,13 +1022,14 @@ int ath10k_debug_start(struct ath10k *ar)
ret = ath10k_debug_htt_stats_req(ar);
if (ret)
/* continue normally anyway, this isn't serious */
ath10k_warn("failed to start htt stats workqueue: %d\n", ret);
ath10k_warn(ar, "failed to start htt stats workqueue: %d\n",
ret);
if (ar->debug.fw_dbglog_mask) {
ret = ath10k_wmi_dbglog_cfg(ar, ar->debug.fw_dbglog_mask);
if (ret)
/* not serious */
ath10k_warn("failed to enable dbglog during start: %d",
ath10k_warn(ar, "failed to enable dbglog during start: %d",
ret);
}
@ -910,11 +1132,20 @@ static const struct file_operations fops_dfs_stats = {
int ath10k_debug_create(struct ath10k *ar)
{
int ret;
ar->debug.fw_crash_data = vzalloc(sizeof(*ar->debug.fw_crash_data));
if (!ar->debug.fw_crash_data) {
ret = -ENOMEM;
goto err;
}
ar->debug.debugfs_phy = debugfs_create_dir("ath10k",
ar->hw->wiphy->debugfsdir);
if (!ar->debug.debugfs_phy)
return -ENOMEM;
if (!ar->debug.debugfs_phy) {
ret = -ENOMEM;
goto err_free_fw_crash_data;
}
INIT_DELAYED_WORK(&ar->debug.htt_stats_dwork,
ath10k_debug_htt_stats_dwork);
@ -930,6 +1161,9 @@ int ath10k_debug_create(struct ath10k *ar)
debugfs_create_file("simulate_fw_crash", S_IRUSR, ar->debug.debugfs_phy,
ar, &fops_simulate_fw_crash);
debugfs_create_file("fw_crash_dump", S_IRUSR, ar->debug.debugfs_phy,
ar, &fops_fw_crash_dump);
debugfs_create_file("chip_id", S_IRUSR, ar->debug.debugfs_phy,
ar, &fops_chip_id);
@ -958,17 +1192,25 @@ int ath10k_debug_create(struct ath10k *ar)
}
return 0;
err_free_fw_crash_data:
vfree(ar->debug.fw_crash_data);
err:
return ret;
}
void ath10k_debug_destroy(struct ath10k *ar)
{
vfree(ar->debug.fw_crash_data);
cancel_delayed_work_sync(&ar->debug.htt_stats_dwork);
}
#endif /* CONFIG_ATH10K_DEBUGFS */
#ifdef CONFIG_ATH10K_DEBUG
void ath10k_dbg(enum ath10k_debug_mask mask, const char *fmt, ...)
void ath10k_dbg(struct ath10k *ar, enum ath10k_debug_mask mask,
const char *fmt, ...)
{
struct va_format vaf;
va_list args;
@ -979,7 +1221,7 @@ void ath10k_dbg(enum ath10k_debug_mask mask, const char *fmt, ...)
vaf.va = &args;
if (ath10k_debug_mask & mask)
ath10k_printk(KERN_DEBUG, "%pV", &vaf);
dev_printk(KERN_DEBUG, ar->dev, "%pV", &vaf);
trace_ath10k_log_dbg(mask, &vaf);
@ -987,13 +1229,14 @@ void ath10k_dbg(enum ath10k_debug_mask mask, const char *fmt, ...)
}
EXPORT_SYMBOL(ath10k_dbg);
void ath10k_dbg_dump(enum ath10k_debug_mask mask,
void ath10k_dbg_dump(struct ath10k *ar,
enum ath10k_debug_mask mask,
const char *msg, const char *prefix,
const void *buf, size_t len)
{
if (ath10k_debug_mask & mask) {
if (msg)
ath10k_dbg(mask, "%s\n", msg);
ath10k_dbg(ar, mask, "%s\n", msg);
print_hex_dump_bytes(prefix, DUMP_PREFIX_OFFSET, buf, len);
}

View File

@ -39,9 +39,10 @@ enum ath10k_debug_mask {
extern unsigned int ath10k_debug_mask;
__printf(1, 2) int ath10k_info(const char *fmt, ...);
__printf(1, 2) int ath10k_err(const char *fmt, ...);
__printf(1, 2) int ath10k_warn(const char *fmt, ...);
__printf(2, 3) int ath10k_info(struct ath10k *ar, const char *fmt, ...);
__printf(2, 3) int ath10k_err(struct ath10k *ar, const char *fmt, ...);
__printf(2, 3) int ath10k_warn(struct ath10k *ar, const char *fmt, ...);
void ath10k_print_driver_info(struct ath10k *ar);
#ifdef CONFIG_ATH10K_DEBUGFS
int ath10k_debug_start(struct ath10k *ar);
@ -53,6 +54,10 @@ void ath10k_debug_read_service_map(struct ath10k *ar,
size_t map_size);
void ath10k_debug_read_target_stats(struct ath10k *ar,
struct wmi_stats_event *ev);
struct ath10k_fw_crash_data *
ath10k_debug_get_new_fw_crash_data(struct ath10k *ar);
void ath10k_debug_dbglog_add(struct ath10k *ar, u8 *buffer, int len);
#define ATH10K_DFS_STAT_INC(ar, c) (ar->debug.dfs_stats.c++)
@ -86,25 +91,40 @@ static inline void ath10k_debug_read_target_stats(struct ath10k *ar,
{
}
static inline void ath10k_debug_dbglog_add(struct ath10k *ar, u8 *buffer,
int len)
{
}
static inline struct ath10k_fw_crash_data *
ath10k_debug_get_new_fw_crash_data(struct ath10k *ar)
{
return NULL;
}
#define ATH10K_DFS_STAT_INC(ar, c) do { } while (0)
#endif /* CONFIG_ATH10K_DEBUGFS */
#ifdef CONFIG_ATH10K_DEBUG
__printf(2, 3) void ath10k_dbg(enum ath10k_debug_mask mask,
__printf(3, 4) void ath10k_dbg(struct ath10k *ar,
enum ath10k_debug_mask mask,
const char *fmt, ...);
void ath10k_dbg_dump(enum ath10k_debug_mask mask,
void ath10k_dbg_dump(struct ath10k *ar,
enum ath10k_debug_mask mask,
const char *msg, const char *prefix,
const void *buf, size_t len);
#else /* CONFIG_ATH10K_DEBUG */
static inline int ath10k_dbg(enum ath10k_debug_mask dbg_mask,
static inline int ath10k_dbg(struct ath10k *ar,
enum ath10k_debug_mask dbg_mask,
const char *fmt, ...)
{
return 0;
}
static inline void ath10k_dbg_dump(enum ath10k_debug_mask mask,
static inline void ath10k_dbg_dump(struct ath10k *ar,
enum ath10k_debug_mask mask,
const char *msg, const char *prefix,
const void *buf, size_t len)
{

View File

@ -46,7 +46,7 @@ static struct sk_buff *ath10k_htc_build_tx_ctrl_skb(void *ar)
skb = dev_alloc_skb(ATH10K_HTC_CONTROL_BUFFER_SIZE);
if (!skb) {
ath10k_warn("Unable to allocate ctrl skb\n");
ath10k_warn(ar, "Unable to allocate ctrl skb\n");
return NULL;
}
@ -56,7 +56,7 @@ static struct sk_buff *ath10k_htc_build_tx_ctrl_skb(void *ar)
skb_cb = ATH10K_SKB_CB(skb);
memset(skb_cb, 0, sizeof(*skb_cb));
ath10k_dbg(ATH10K_DBG_HTC, "%s: skb %p\n", __func__, skb);
ath10k_dbg(ar, ATH10K_DBG_HTC, "%s: skb %p\n", __func__, skb);
return skb;
}
@ -72,13 +72,15 @@ static inline void ath10k_htc_restore_tx_skb(struct ath10k_htc *htc,
static void ath10k_htc_notify_tx_completion(struct ath10k_htc_ep *ep,
struct sk_buff *skb)
{
ath10k_dbg(ATH10K_DBG_HTC, "%s: ep %d skb %p\n", __func__,
struct ath10k *ar = ep->htc->ar;
ath10k_dbg(ar, ATH10K_DBG_HTC, "%s: ep %d skb %p\n", __func__,
ep->eid, skb);
ath10k_htc_restore_tx_skb(ep->htc, skb);
if (!ep->ep_ops.ep_tx_complete) {
ath10k_warn("no tx handler for eid %d\n", ep->eid);
ath10k_warn(ar, "no tx handler for eid %d\n", ep->eid);
dev_kfree_skb_any(skb);
return;
}
@ -89,12 +91,14 @@ static void ath10k_htc_notify_tx_completion(struct ath10k_htc_ep *ep,
/* assumes tx_lock is held */
static bool ath10k_htc_ep_need_credit_update(struct ath10k_htc_ep *ep)
{
struct ath10k *ar = ep->htc->ar;
if (!ep->tx_credit_flow_enabled)
return false;
if (ep->tx_credits >= ep->tx_credits_per_max_message)
return false;
ath10k_dbg(ATH10K_DBG_HTC, "HTC: endpoint %d needs credit update\n",
ath10k_dbg(ar, ATH10K_DBG_HTC, "HTC: endpoint %d needs credit update\n",
ep->eid);
return true;
}
@ -123,6 +127,7 @@ int ath10k_htc_send(struct ath10k_htc *htc,
enum ath10k_htc_ep_id eid,
struct sk_buff *skb)
{
struct ath10k *ar = htc->ar;
struct ath10k_htc_ep *ep = &htc->endpoint[eid];
struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(skb);
struct ath10k_hif_sg_item sg_item;
@ -134,18 +139,10 @@ int ath10k_htc_send(struct ath10k_htc *htc,
return -ECOMM;
if (eid >= ATH10K_HTC_EP_COUNT) {
ath10k_warn("Invalid endpoint id: %d\n", eid);
ath10k_warn(ar, "Invalid endpoint id: %d\n", eid);
return -ENOENT;
}
/* FIXME: This looks ugly, can we fix it? */
spin_lock_bh(&htc->tx_lock);
if (htc->stopped) {
spin_unlock_bh(&htc->tx_lock);
return -ESHUTDOWN;
}
spin_unlock_bh(&htc->tx_lock);
skb_push(skb, sizeof(struct ath10k_htc_hdr));
if (ep->tx_credit_flow_enabled) {
@ -157,7 +154,7 @@ int ath10k_htc_send(struct ath10k_htc *htc,
goto err_pull;
}
ep->tx_credits -= credits;
ath10k_dbg(ATH10K_DBG_HTC,
ath10k_dbg(ar, ATH10K_DBG_HTC,
"htc ep %d consumed %d credits (total %d)\n",
eid, credits, ep->tx_credits);
spin_unlock_bh(&htc->tx_lock);
@ -188,7 +185,7 @@ err_credits:
if (ep->tx_credit_flow_enabled) {
spin_lock_bh(&htc->tx_lock);
ep->tx_credits += credits;
ath10k_dbg(ATH10K_DBG_HTC,
ath10k_dbg(ar, ATH10K_DBG_HTC,
"htc ep %d reverted %d credits back (total %d)\n",
eid, credits, ep->tx_credits);
spin_unlock_bh(&htc->tx_lock);
@ -227,11 +224,12 @@ ath10k_htc_process_credit_report(struct ath10k_htc *htc,
int len,
enum ath10k_htc_ep_id eid)
{
struct ath10k *ar = htc->ar;
struct ath10k_htc_ep *ep;
int i, n_reports;
if (len % sizeof(*report))
ath10k_warn("Uneven credit report len %d", len);
ath10k_warn(ar, "Uneven credit report len %d", len);
n_reports = len / sizeof(*report);
@ -243,7 +241,7 @@ ath10k_htc_process_credit_report(struct ath10k_htc *htc,
ep = &htc->endpoint[report->eid];
ep->tx_credits += report->credits;
ath10k_dbg(ATH10K_DBG_HTC, "htc ep %d got %d credits (total %d)\n",
ath10k_dbg(ar, ATH10K_DBG_HTC, "htc ep %d got %d credits (total %d)\n",
report->eid, report->credits, ep->tx_credits);
if (ep->ep_ops.ep_tx_credits) {
@ -260,6 +258,7 @@ static int ath10k_htc_process_trailer(struct ath10k_htc *htc,
int length,
enum ath10k_htc_ep_id src_eid)
{
struct ath10k *ar = htc->ar;
int status = 0;
struct ath10k_htc_record *record;
u8 *orig_buffer;
@ -279,7 +278,7 @@ static int ath10k_htc_process_trailer(struct ath10k_htc *htc,
if (record->hdr.len > length) {
/* no room left in buffer for record */
ath10k_warn("Invalid record length: %d\n",
ath10k_warn(ar, "Invalid record length: %d\n",
record->hdr.len);
status = -EINVAL;
break;
@ -289,7 +288,7 @@ static int ath10k_htc_process_trailer(struct ath10k_htc *htc,
case ATH10K_HTC_RECORD_CREDITS:
len = sizeof(struct ath10k_htc_credit_report);
if (record->hdr.len < len) {
ath10k_warn("Credit report too long\n");
ath10k_warn(ar, "Credit report too long\n");
status = -EINVAL;
break;
}
@ -299,7 +298,7 @@ static int ath10k_htc_process_trailer(struct ath10k_htc *htc,
src_eid);
break;
default:
ath10k_warn("Unhandled record: id:%d length:%d\n",
ath10k_warn(ar, "Unhandled record: id:%d length:%d\n",
record->hdr.id, record->hdr.len);
break;
}
@ -313,7 +312,7 @@ static int ath10k_htc_process_trailer(struct ath10k_htc *htc,
}
if (status)
ath10k_dbg_dump(ATH10K_DBG_HTC, "htc rx bad trailer", "",
ath10k_dbg_dump(ar, ATH10K_DBG_HTC, "htc rx bad trailer", "",
orig_buffer, orig_length);
return status;
@ -339,8 +338,8 @@ static int ath10k_htc_rx_completion_handler(struct ath10k *ar,
eid = hdr->eid;
if (eid >= ATH10K_HTC_EP_COUNT) {
ath10k_warn("HTC Rx: invalid eid %d\n", eid);
ath10k_dbg_dump(ATH10K_DBG_HTC, "htc bad header", "",
ath10k_warn(ar, "HTC Rx: invalid eid %d\n", eid);
ath10k_dbg_dump(ar, ATH10K_DBG_HTC, "htc bad header", "",
hdr, sizeof(*hdr));
status = -EINVAL;
goto out;
@ -360,19 +359,19 @@ static int ath10k_htc_rx_completion_handler(struct ath10k *ar,
payload_len = __le16_to_cpu(hdr->len);
if (payload_len + sizeof(*hdr) > ATH10K_HTC_MAX_LEN) {
ath10k_warn("HTC rx frame too long, len: %zu\n",
ath10k_warn(ar, "HTC rx frame too long, len: %zu\n",
payload_len + sizeof(*hdr));
ath10k_dbg_dump(ATH10K_DBG_HTC, "htc bad rx pkt len", "",
ath10k_dbg_dump(ar, ATH10K_DBG_HTC, "htc bad rx pkt len", "",
hdr, sizeof(*hdr));
status = -EINVAL;
goto out;
}
if (skb->len < payload_len) {
ath10k_dbg(ATH10K_DBG_HTC,
ath10k_dbg(ar, ATH10K_DBG_HTC,
"HTC Rx: insufficient length, got %d, expected %d\n",
skb->len, payload_len);
ath10k_dbg_dump(ATH10K_DBG_HTC, "htc bad rx pkt len",
ath10k_dbg_dump(ar, ATH10K_DBG_HTC, "htc bad rx pkt len",
"", hdr, sizeof(*hdr));
status = -EINVAL;
goto out;
@ -388,7 +387,7 @@ static int ath10k_htc_rx_completion_handler(struct ath10k *ar,
if ((trailer_len < min_len) ||
(trailer_len > payload_len)) {
ath10k_warn("Invalid trailer length: %d\n",
ath10k_warn(ar, "Invalid trailer length: %d\n",
trailer_len);
status = -EPROTO;
goto out;
@ -421,7 +420,7 @@ static int ath10k_htc_rx_completion_handler(struct ath10k *ar,
* this is a fatal error, target should not be
* sending unsolicited messages on the ep 0
*/
ath10k_warn("HTC rx ctrl still processing\n");
ath10k_warn(ar, "HTC rx ctrl still processing\n");
status = -EINVAL;
complete(&htc->ctl_resp);
goto out;
@ -442,7 +441,7 @@ static int ath10k_htc_rx_completion_handler(struct ath10k *ar,
goto out;
}
ath10k_dbg(ATH10K_DBG_HTC, "htc rx completion ep %d skb %p\n",
ath10k_dbg(ar, ATH10K_DBG_HTC, "htc rx completion ep %d skb %p\n",
eid, skb);
ep->ep_ops.ep_rx_complete(ar, skb);
@ -459,7 +458,7 @@ static void ath10k_htc_control_rx_complete(struct ath10k *ar,
{
/* This is unexpected. FW is not supposed to send regular rx on this
* endpoint. */
ath10k_warn("unexpected htc rx\n");
ath10k_warn(ar, "unexpected htc rx\n");
kfree_skb(skb);
}
@ -546,6 +545,7 @@ static u8 ath10k_htc_get_credit_allocation(struct ath10k_htc *htc,
int ath10k_htc_wait_target(struct ath10k_htc *htc)
{
struct ath10k *ar = htc->ar;
int i, status = 0;
struct ath10k_htc_svc_conn_req conn_req;
struct ath10k_htc_svc_conn_resp conn_resp;
@ -563,7 +563,7 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
* iomap writes unmasking PCI CE irqs aren't propagated
* properly in KVM PCI-passthrough sometimes.
*/
ath10k_warn("failed to receive control response completion, polling..\n");
ath10k_warn(ar, "failed to receive control response completion, polling..\n");
for (i = 0; i < CE_COUNT; i++)
ath10k_hif_send_complete_check(htc->ar, i, 1);
@ -576,12 +576,12 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
}
if (status < 0) {
ath10k_err("ctl_resp never came in (%d)\n", status);
ath10k_err(ar, "ctl_resp never came in (%d)\n", status);
return status;
}
if (htc->control_resp_len < sizeof(msg->hdr) + sizeof(msg->ready)) {
ath10k_err("Invalid HTC ready msg len:%d\n",
ath10k_err(ar, "Invalid HTC ready msg len:%d\n",
htc->control_resp_len);
return -ECOMM;
}
@ -592,21 +592,21 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
credit_size = __le16_to_cpu(msg->ready.credit_size);
if (message_id != ATH10K_HTC_MSG_READY_ID) {
ath10k_err("Invalid HTC ready msg: 0x%x\n", message_id);
ath10k_err(ar, "Invalid HTC ready msg: 0x%x\n", message_id);
return -ECOMM;
}
htc->total_transmit_credits = credit_count;
htc->target_credit_size = credit_size;
ath10k_dbg(ATH10K_DBG_HTC,
ath10k_dbg(ar, ATH10K_DBG_HTC,
"Target ready! transmit resources: %d size:%d\n",
htc->total_transmit_credits,
htc->target_credit_size);
if ((htc->total_transmit_credits == 0) ||
(htc->target_credit_size == 0)) {
ath10k_err("Invalid credit size received\n");
ath10k_err(ar, "Invalid credit size received\n");
return -ECOMM;
}
@ -623,7 +623,8 @@ int ath10k_htc_wait_target(struct ath10k_htc *htc)
/* connect fake service */
status = ath10k_htc_connect_service(htc, &conn_req, &conn_resp);
if (status) {
ath10k_err("could not connect to htc service (%d)\n", status);
ath10k_err(ar, "could not connect to htc service (%d)\n",
status);
return status;
}
@ -634,6 +635,7 @@ int ath10k_htc_connect_service(struct ath10k_htc *htc,
struct ath10k_htc_svc_conn_req *conn_req,
struct ath10k_htc_svc_conn_resp *conn_resp)
{
struct ath10k *ar = htc->ar;
struct ath10k_htc_msg *msg;
struct ath10k_htc_conn_svc *req_msg;
struct ath10k_htc_conn_svc_response resp_msg_dummy;
@ -659,13 +661,13 @@ int ath10k_htc_connect_service(struct ath10k_htc *htc,
tx_alloc = ath10k_htc_get_credit_allocation(htc,
conn_req->service_id);
if (!tx_alloc)
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"boot htc service %s does not allocate target credits\n",
htc_service_name(conn_req->service_id));
skb = ath10k_htc_build_tx_ctrl_skb(htc->ar);
if (!skb) {
ath10k_err("Failed to allocate HTC packet\n");
ath10k_err(ar, "Failed to allocate HTC packet\n");
return -ENOMEM;
}
@ -703,7 +705,7 @@ int ath10k_htc_connect_service(struct ath10k_htc *htc,
if (status <= 0) {
if (status == 0)
status = -ETIMEDOUT;
ath10k_err("Service connect timeout: %d\n", status);
ath10k_err(ar, "Service connect timeout: %d\n", status);
return status;
}
@ -716,11 +718,11 @@ int ath10k_htc_connect_service(struct ath10k_htc *htc,
if ((message_id != ATH10K_HTC_MSG_CONNECT_SERVICE_RESP_ID) ||
(htc->control_resp_len < sizeof(msg->hdr) +
sizeof(msg->connect_service_response))) {
ath10k_err("Invalid resp message ID 0x%x", message_id);
ath10k_err(ar, "Invalid resp message ID 0x%x", message_id);
return -EPROTO;
}
ath10k_dbg(ATH10K_DBG_HTC,
ath10k_dbg(ar, ATH10K_DBG_HTC,
"HTC Service %s connect response: status: 0x%x, assigned ep: 0x%x\n",
htc_service_name(service_id),
resp_msg->status, resp_msg->eid);
@ -729,7 +731,7 @@ int ath10k_htc_connect_service(struct ath10k_htc *htc,
/* check response status */
if (resp_msg->status != ATH10K_HTC_CONN_SVC_STATUS_SUCCESS) {
ath10k_err("HTC Service %s connect request failed: 0x%x)\n",
ath10k_err(ar, "HTC Service %s connect request failed: 0x%x)\n",
htc_service_name(service_id),
resp_msg->status);
return -EPROTO;
@ -780,18 +782,18 @@ setup:
if (status)
return status;
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"boot htc service '%s' ul pipe %d dl pipe %d eid %d ready\n",
htc_service_name(ep->service_id), ep->ul_pipe_id,
ep->dl_pipe_id, ep->eid);
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"boot htc ep %d ul polled %d dl polled %d\n",
ep->eid, ep->ul_is_polled, ep->dl_is_polled);
if (disable_credit_flow_ctrl && ep->tx_credit_flow_enabled) {
ep->tx_credit_flow_enabled = false;
ath10k_dbg(ATH10K_DBG_BOOT,
ath10k_dbg(ar, ATH10K_DBG_BOOT,
"boot htc service '%s' eid %d TX flow control disabled\n",
htc_service_name(ep->service_id), assigned_eid);
}
@ -799,13 +801,13 @@ setup:
return status;
}
struct sk_buff *ath10k_htc_alloc_skb(int size)
struct sk_buff *ath10k_htc_alloc_skb(struct ath10k *ar, int size)
{
struct sk_buff *skb;
skb = dev_alloc_skb(size + sizeof(struct ath10k_htc_hdr));
if (!skb) {
ath10k_warn("could not allocate HTC tx skb\n");
ath10k_warn(ar, "could not allocate HTC tx skb\n");
return NULL;
}
@ -813,13 +815,14 @@ struct sk_buff *ath10k_htc_alloc_skb(int size)
/* FW/HTC requires 4-byte aligned streams */
if (!IS_ALIGNED((unsigned long)skb->data, 4))
ath10k_warn("Unaligned HTC tx skb\n");
ath10k_warn(ar, "Unaligned HTC tx skb\n");
return skb;
}
int ath10k_htc_start(struct ath10k_htc *htc)
{
struct ath10k *ar = htc->ar;
struct sk_buff *skb;
int status = 0;
struct ath10k_htc_msg *msg;
@ -835,7 +838,7 @@ int ath10k_htc_start(struct ath10k_htc *htc)
msg->hdr.message_id =
__cpu_to_le16(ATH10K_HTC_MSG_SETUP_COMPLETE_EX_ID);
ath10k_dbg(ATH10K_DBG_HTC, "HTC is using TX credit flow control\n");
ath10k_dbg(ar, ATH10K_DBG_HTC, "HTC is using TX credit flow control\n");
status = ath10k_htc_send(htc, ATH10K_HTC_EP_0, skb);
if (status) {
@ -846,13 +849,6 @@ int ath10k_htc_start(struct ath10k_htc *htc)
return 0;
}
void ath10k_htc_stop(struct ath10k_htc *htc)
{
spin_lock_bh(&htc->tx_lock);
htc->stopped = true;
spin_unlock_bh(&htc->tx_lock);
}
/* registered target arrival callback from the HIF layer */
int ath10k_htc_init(struct ath10k *ar)
{
@ -862,7 +858,6 @@ int ath10k_htc_init(struct ath10k *ar)
spin_lock_init(&htc->tx_lock);
htc->stopped = false;
ath10k_htc_reset_endpoint_states(htc);
/* setup HIF layer callbacks */

View File

@ -332,7 +332,7 @@ struct ath10k_htc {
struct ath10k *ar;
struct ath10k_htc_ep endpoint[ATH10K_HTC_EP_COUNT];
/* protects endpoint and stopped fields */
/* protects endpoints */
spinlock_t tx_lock;
struct ath10k_htc_ops htc_ops;
@ -345,8 +345,6 @@ struct ath10k_htc {
int total_transmit_credits;
struct ath10k_htc_svc_tx_credits service_tx_alloc[ATH10K_HTC_EP_COUNT];
int target_credit_size;
bool stopped;
};
int ath10k_htc_init(struct ath10k *ar);
@ -357,7 +355,6 @@ int ath10k_htc_connect_service(struct ath10k_htc *htc,
struct ath10k_htc_svc_conn_resp *conn_resp);
int ath10k_htc_send(struct ath10k_htc *htc, enum ath10k_htc_ep_id eid,
struct sk_buff *packet);
void ath10k_htc_stop(struct ath10k_htc *htc);
struct sk_buff *ath10k_htc_alloc_skb(int size);
struct sk_buff *ath10k_htc_alloc_skb(struct ath10k *ar, int size);
#endif

View File

@ -74,12 +74,14 @@ int ath10k_htt_init(struct ath10k *ar)
static int ath10k_htt_verify_version(struct ath10k_htt *htt)
{
ath10k_dbg(ATH10K_DBG_BOOT, "htt target version %d.%d\n",
struct ath10k *ar = htt->ar;
ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt target version %d.%d\n",
htt->target_version_major, htt->target_version_minor);
if (htt->target_version_major != 2 &&
htt->target_version_major != 3) {
ath10k_err("unsupported htt major version %d. supported versions are 2 and 3\n",
ath10k_err(ar, "unsupported htt major version %d. supported versions are 2 and 3\n",
htt->target_version_major);
return -ENOTSUPP;
}
@ -89,6 +91,7 @@ static int ath10k_htt_verify_version(struct ath10k_htt *htt)
int ath10k_htt_setup(struct ath10k_htt *htt)
{
struct ath10k *ar = htt->ar;
int status;
init_completion(&htt->target_version_received);
@ -100,7 +103,7 @@ int ath10k_htt_setup(struct ath10k_htt *htt)
status = wait_for_completion_timeout(&htt->target_version_received,
HTT_TARGET_VERSION_TIMEOUT_HZ);
if (status <= 0) {
ath10k_warn("htt version request timed out\n");
ath10k_warn(ar, "htt version request timed out\n");
return -ETIMEDOUT;
}

View File

@ -271,13 +271,14 @@ void ath10k_htt_rx_free(struct ath10k_htt *htt)
static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
{
struct ath10k *ar = htt->ar;
int idx;
struct sk_buff *msdu;
lockdep_assert_held(&htt->rx_ring.lock);
if (htt->rx_ring.fill_cnt == 0) {
ath10k_warn("tried to pop sk_buff from an empty rx ring\n");
ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n");
return NULL;
}
@ -311,6 +312,7 @@ static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
struct sk_buff **tail_msdu,
u32 *attention)
{
struct ath10k *ar = htt->ar;
int msdu_len, msdu_chaining = 0;
struct sk_buff *msdu;
struct htt_rx_desc *rx_desc;
@ -318,7 +320,7 @@ static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
lockdep_assert_held(&htt->rx_ring.lock);
if (htt->rx_confused) {
ath10k_warn("htt is confused. refusing rx\n");
ath10k_warn(ar, "htt is confused. refusing rx\n");
return -1;
}
@ -331,7 +333,7 @@ static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
msdu->len + skb_tailroom(msdu),
DMA_FROM_DEVICE);
ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ",
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ",
msdu->data, msdu->len + skb_tailroom(msdu));
rx_desc = (struct htt_rx_desc *)msdu->data;
@ -354,7 +356,7 @@ static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
ath10k_htt_rx_free_msdu_chain(*head_msdu);
*head_msdu = NULL;
msdu = NULL;
ath10k_err("htt rx stopped. cannot recover\n");
ath10k_err(ar, "htt rx stopped. cannot recover\n");
htt->rx_confused = true;
break;
}
@ -429,7 +431,7 @@ static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
next->len + skb_tailroom(next),
DMA_FROM_DEVICE);
ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL,
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL,
"htt rx chained: ", next->data,
next->len + skb_tailroom(next));
@ -483,13 +485,14 @@ static void ath10k_htt_rx_replenish_task(unsigned long ptr)
int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
{
struct ath10k *ar = htt->ar;
dma_addr_t paddr;
void *vaddr;
struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
if (!is_power_of_2(htt->rx_ring.size)) {
ath10k_warn("htt rx ring size is not power of 2\n");
ath10k_warn(ar, "htt rx ring size is not power of 2\n");
return -EINVAL;
}
@ -550,7 +553,7 @@ int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
(unsigned long)htt);
ath10k_dbg(ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
htt->rx_ring.size, htt->rx_ring.fill_level);
return 0;
@ -572,7 +575,8 @@ err_netbuf:
return -ENOMEM;
}
static int ath10k_htt_rx_crypto_param_len(enum htt_rx_mpdu_encrypt_type type)
static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar,
enum htt_rx_mpdu_encrypt_type type)
{
switch (type) {
case HTT_RX_MPDU_ENCRYPT_WEP40:
@ -588,11 +592,12 @@ static int ath10k_htt_rx_crypto_param_len(enum htt_rx_mpdu_encrypt_type type)
return 0;
}
ath10k_warn("unknown encryption type %d\n", type);
ath10k_warn(ar, "unknown encryption type %d\n", type);
return 0;
}
static int ath10k_htt_rx_crypto_tail_len(enum htt_rx_mpdu_encrypt_type type)
static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar,
enum htt_rx_mpdu_encrypt_type type)
{
switch (type) {
case HTT_RX_MPDU_ENCRYPT_NONE:
@ -608,7 +613,7 @@ static int ath10k_htt_rx_crypto_tail_len(enum htt_rx_mpdu_encrypt_type type)
return 8;
}
ath10k_warn("unknown encryption type %d\n", type);
ath10k_warn(ar, "unknown encryption type %d\n", type);
return 0;
}
@ -819,19 +824,55 @@ static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
return true;
}
static const char * const tid_to_ac[] = {
"BE",
"BK",
"BK",
"BE",
"VI",
"VI",
"VO",
"VO",
};
static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size)
{
u8 *qc;
int tid;
if (!ieee80211_is_data_qos(hdr->frame_control))
return "";
qc = ieee80211_get_qos_ctl(hdr);
tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
if (tid < 8)
snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]);
else
snprintf(out, size, "tid %d", tid);
return out;
}
static void ath10k_process_rx(struct ath10k *ar,
struct ieee80211_rx_status *rx_status,
struct sk_buff *skb)
{
struct ieee80211_rx_status *status;
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
char tid[32];
status = IEEE80211_SKB_RXCB(skb);
*status = *rx_status;
ath10k_dbg(ATH10K_DBG_DATA,
"rx skb %p len %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %imic-err %i\n",
ath10k_dbg(ar, ATH10K_DBG_DATA,
"rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
skb,
skb->len,
ieee80211_get_SA(hdr),
ath10k_get_tid(hdr, tid, sizeof(tid)),
is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
"mcast" : "ucast",
(__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
status->flag == 0 ? "legacy" : "",
status->flag & RX_FLAG_HT ? "ht" : "",
status->flag & RX_FLAG_VHT ? "vht" : "",
@ -843,8 +884,9 @@ static void ath10k_process_rx(struct ath10k *ar,
status->freq,
status->band, status->flag,
!!(status->flag & RX_FLAG_FAILED_FCS_CRC),
!!(status->flag & RX_FLAG_MMIC_ERROR));
ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
!!(status->flag & RX_FLAG_MMIC_ERROR),
!!(status->flag & RX_FLAG_AMSDU_MORE));
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
skb->data, skb->len);
ieee80211_rx(ar->hw, skb);
@ -860,13 +902,14 @@ static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
struct ieee80211_rx_status *rx_status,
struct sk_buff *skb_in)
{
struct ath10k *ar = htt->ar;
struct htt_rx_desc *rxd;
struct sk_buff *skb = skb_in;
struct sk_buff *first;
enum rx_msdu_decap_format fmt;
enum htt_rx_mpdu_encrypt_type enctype;
struct ieee80211_hdr *hdr;
u8 hdr_buf[64], addr[ETH_ALEN], *qos;
u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos;
unsigned int hdr_len;
rxd = (void *)skb->data - sizeof(*rxd);
@ -893,8 +936,8 @@ static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
/* First frame in an A-MSDU chain has more decapped data. */
if (skb == first) {
len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
len += round_up(ath10k_htt_rx_crypto_param_len(enctype),
4);
len += round_up(ath10k_htt_rx_crypto_param_len(ar,
enctype), 4);
decap_hdr += len;
}
@ -904,10 +947,11 @@ static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
skb_trim(skb, skb->len - FCS_LEN);
break;
case RX_MSDU_DECAP_NATIVE_WIFI:
/* pull decapped header and copy DA */
/* pull decapped header and copy SA & DA */
hdr = (struct ieee80211_hdr *)skb->data;
hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
memcpy(addr, ieee80211_get_DA(hdr), ETH_ALEN);
memcpy(da, ieee80211_get_DA(hdr), ETH_ALEN);
memcpy(sa, ieee80211_get_SA(hdr), ETH_ALEN);
skb_pull(skb, hdr_len);
/* push original 802.11 header */
@ -921,8 +965,11 @@ static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
qos = ieee80211_get_qos_ctl(hdr);
qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
/* original 802.11 header has a different DA */
memcpy(ieee80211_get_DA(hdr), addr, ETH_ALEN);
/* original 802.11 header has a different DA and in
* case of 4addr it may also have different SA
*/
memcpy(ieee80211_get_DA(hdr), da, ETH_ALEN);
memcpy(ieee80211_get_SA(hdr), sa, ETH_ALEN);
break;
case RX_MSDU_DECAP_ETHERNET2_DIX:
/* strip ethernet header and insert decapped 802.11
@ -965,6 +1012,7 @@ static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
struct ieee80211_rx_status *rx_status,
struct sk_buff *skb)
{
struct ath10k *ar = htt->ar;
struct htt_rx_desc *rxd;
struct ieee80211_hdr *hdr;
enum rx_msdu_decap_format fmt;
@ -974,7 +1022,7 @@ static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
/* This shouldn't happen. If it does than it may be a FW bug. */
if (skb->next) {
ath10k_warn("htt rx received chained non A-MSDU frame\n");
ath10k_warn(ar, "htt rx received chained non A-MSDU frame\n");
ath10k_htt_rx_free_msdu_chain(skb->next);
skb->next = NULL;
}
@ -1011,7 +1059,8 @@ static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
rfc1042 = hdr;
rfc1042 += roundup(hdr_len, 4);
rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(enctype), 4);
rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar,
enctype), 4);
skb_pull(skb, sizeof(struct ethhdr));
memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
@ -1120,27 +1169,29 @@ static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
bool channel_set,
u32 attention)
{
struct ath10k *ar = htt->ar;
if (head->len == 0) {
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt rx dropping due to zero-len\n");
return false;
}
if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) {
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt rx dropping due to decrypt-err\n");
return false;
}
if (!channel_set) {
ath10k_warn("no channel configured; ignoring frame!\n");
ath10k_warn(ar, "no channel configured; ignoring frame!\n");
return false;
}
/* Skip mgmt frames while we handle this in WMI */
if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL ||
attention & RX_ATTENTION_FLAGS_MGMT_TYPE) {
ath10k_dbg(ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
return false;
}
@ -1148,14 +1199,14 @@ static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR &&
status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER &&
!htt->ar->monitor_started) {
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt rx ignoring frame w/ status %d\n",
status);
return false;
}
if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt rx CAC running\n");
return false;
}
@ -1166,6 +1217,7 @@ static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
struct htt_rx_indication *rx)
{
struct ath10k *ar = htt->ar;
struct ieee80211_rx_status *rx_status = &htt->rx_status;
struct htt_rx_indication_mpdu_range *mpdu_ranges;
struct htt_rx_desc *rxd;
@ -1211,7 +1263,7 @@ static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
rx_status);
}
ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
rx, sizeof(*rx) +
(sizeof(struct htt_rx_indication_mpdu_range) *
num_mpdu_ranges));
@ -1233,7 +1285,7 @@ static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
&attention);
if (ret < 0) {
ath10k_warn("failed to pop amsdu from htt rx ring %d\n",
ath10k_warn(ar, "failed to pop amsdu from htt rx ring %d\n",
ret);
ath10k_htt_rx_free_msdu_chain(msdu_head);
continue;
@ -1282,6 +1334,7 @@ static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
struct htt_rx_fragment_indication *frag)
{
struct ath10k *ar = htt->ar;
struct sk_buff *msdu_head, *msdu_tail;
enum htt_rx_mpdu_encrypt_type enctype;
struct htt_rx_desc *rxd;
@ -1308,10 +1361,10 @@ static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
&attention);
spin_unlock_bh(&htt->rx_ring.lock);
ath10k_dbg(ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
if (ret) {
ath10k_warn("failed to pop amsdu from httr rx ring for fragmented rx %d\n",
ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n",
ret);
ath10k_htt_rx_free_msdu_chain(msdu_head);
return;
@ -1328,7 +1381,7 @@ static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
RX_MSDU_START_INFO1_DECAP_FORMAT);
if (fmt != RX_MSDU_DECAP_RAW) {
ath10k_warn("we dont support non-raw fragmented rx yet\n");
ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n");
dev_kfree_skb_any(msdu_head);
goto end;
}
@ -1340,17 +1393,17 @@ static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head);
if (tkip_mic_err)
ath10k_warn("tkip mic error\n");
ath10k_warn(ar, "tkip mic error\n");
if (decrypt_err) {
ath10k_warn("decryption err in fragmented rx\n");
ath10k_warn(ar, "decryption err in fragmented rx\n");
dev_kfree_skb_any(msdu_head);
goto end;
}
if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) {
hdrlen = ieee80211_hdrlen(hdr->frame_control);
paramlen = ath10k_htt_rx_crypto_param_len(enctype);
paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype);
/* It is more efficient to move the header than the payload */
memmove((void *)msdu_head->data + paramlen,
@ -1364,7 +1417,7 @@ static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
trim = 4;
/* remove crypto trailer */
trim += ath10k_htt_rx_crypto_tail_len(enctype);
trim += ath10k_htt_rx_crypto_tail_len(ar, enctype);
/* last fragment of TKIP frags has MIC */
if (!ieee80211_has_morefrags(hdr->frame_control) &&
@ -1372,20 +1425,20 @@ static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
trim += 8;
if (trim > msdu_head->len) {
ath10k_warn("htt rx fragment: trailer longer than the frame itself? drop\n");
ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n");
dev_kfree_skb_any(msdu_head);
goto end;
}
skb_trim(msdu_head, msdu_head->len - trim);
ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
msdu_head->data, msdu_head->len);
ath10k_process_rx(htt->ar, rx_status, msdu_head);
end:
if (fw_desc_len > 0) {
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"expecting more fragmented rx in one indication %d\n",
fw_desc_len);
}
@ -1415,12 +1468,12 @@ static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
tx_done.discard = true;
break;
default:
ath10k_warn("unhandled tx completion status %d\n", status);
ath10k_warn(ar, "unhandled tx completion status %d\n", status);
tx_done.discard = true;
break;
}
ath10k_dbg(ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
resp->data_tx_completion.num_msdus);
for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
@ -1441,14 +1494,14 @@ static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp)
tid = MS(info0, HTT_RX_BA_INFO0_TID);
peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt rx addba tid %hu peer_id %hu size %hhu\n",
tid, peer_id, ev->window_size);
spin_lock_bh(&ar->data_lock);
peer = ath10k_peer_find_by_id(ar, peer_id);
if (!peer) {
ath10k_warn("received addba event for invalid peer_id: %hu\n",
ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
peer_id);
spin_unlock_bh(&ar->data_lock);
return;
@ -1456,13 +1509,13 @@ static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp)
arvif = ath10k_get_arvif(ar, peer->vdev_id);
if (!arvif) {
ath10k_warn("received addba event for invalid vdev_id: %u\n",
ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
peer->vdev_id);
spin_unlock_bh(&ar->data_lock);
return;
}
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt rx start rx ba session sta %pM tid %hu size %hhu\n",
peer->addr, tid, ev->window_size);
@ -1481,14 +1534,14 @@ static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp)
tid = MS(info0, HTT_RX_BA_INFO0_TID);
peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt rx delba tid %hu peer_id %hu\n",
tid, peer_id);
spin_lock_bh(&ar->data_lock);
peer = ath10k_peer_find_by_id(ar, peer_id);
if (!peer) {
ath10k_warn("received addba event for invalid peer_id: %hu\n",
ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
peer_id);
spin_unlock_bh(&ar->data_lock);
return;
@ -1496,13 +1549,13 @@ static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp)
arvif = ath10k_get_arvif(ar, peer->vdev_id);
if (!arvif) {
ath10k_warn("received addba event for invalid vdev_id: %u\n",
ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
peer->vdev_id);
spin_unlock_bh(&ar->data_lock);
return;
}
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt rx stop rx ba session sta %pM tid %hu\n",
peer->addr, tid);
@ -1517,9 +1570,9 @@ void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
/* confirm alignment */
if (!IS_ALIGNED((unsigned long)skb->data, 4))
ath10k_warn("unaligned htt message, expect trouble\n");
ath10k_warn(ar, "unaligned htt message, expect trouble\n");
ath10k_dbg(ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
resp->hdr.msg_type);
switch (resp->hdr.msg_type) {
case HTT_T2H_MSG_TYPE_VERSION_CONF: {
@ -1583,7 +1636,7 @@ void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
struct ath10k *ar = htt->ar;
struct htt_security_indication *ev = &resp->security_indication;
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"sec ind peer_id %d unicast %d type %d\n",
__le16_to_cpu(ev->peer_id),
!!(ev->flags & HTT_SECURITY_IS_UNICAST),
@ -1592,7 +1645,7 @@ void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
break;
}
case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
skb->data, skb->len);
ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
break;
@ -1609,7 +1662,7 @@ void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
* sends all tx frames as already inspected so this shouldn't
* happen unless fw has a bug.
*/
ath10k_warn("received an unexpected htt tx inspect event\n");
ath10k_warn(ar, "received an unexpected htt tx inspect event\n");
break;
case HTT_T2H_MSG_TYPE_RX_ADDBA:
ath10k_htt_rx_addba(ar, resp);
@ -1624,9 +1677,9 @@ void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
break;
}
default:
ath10k_dbg(ATH10K_DBG_HTT, "htt event (%d) not handled\n",
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt event (%d) not handled\n",
resp->hdr.msg_type);
ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
skb->data, skb->len);
break;
};

View File

@ -58,6 +58,7 @@ exit:
int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt)
{
struct ath10k *ar = htt->ar;
int msdu_id;
lockdep_assert_held(&htt->tx_lock);
@ -67,24 +68,29 @@ int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt)
if (msdu_id == htt->max_num_pending_tx)
return -ENOBUFS;
ath10k_dbg(ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", msdu_id);
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx alloc msdu_id %d\n", msdu_id);
__set_bit(msdu_id, htt->used_msdu_ids);
return msdu_id;
}
void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id)
{
struct ath10k *ar = htt->ar;
lockdep_assert_held(&htt->tx_lock);
if (!test_bit(msdu_id, htt->used_msdu_ids))
ath10k_warn("trying to free unallocated msdu_id %d\n", msdu_id);
ath10k_warn(ar, "trying to free unallocated msdu_id %d\n",
msdu_id);
ath10k_dbg(ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx free msdu_id %hu\n", msdu_id);
__clear_bit(msdu_id, htt->used_msdu_ids);
}
int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
{
struct ath10k *ar = htt->ar;
spin_lock_init(&htt->tx_lock);
init_waitqueue_head(&htt->empty_tx_wq);
@ -93,7 +99,7 @@ int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
else
htt->max_num_pending_tx = TARGET_NUM_MSDU_DESC;
ath10k_dbg(ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt tx max num pending tx %d\n",
htt->max_num_pending_tx);
htt->pending_tx = kzalloc(sizeof(*htt->pending_tx) *
@ -122,6 +128,7 @@ int ath10k_htt_tx_alloc(struct ath10k_htt *htt)
static void ath10k_htt_tx_free_pending(struct ath10k_htt *htt)
{
struct ath10k *ar = htt->ar;
struct htt_tx_done tx_done = {0};
int msdu_id;
@ -130,7 +137,7 @@ static void ath10k_htt_tx_free_pending(struct ath10k_htt *htt)
if (!test_bit(msdu_id, htt->used_msdu_ids))
continue;
ath10k_dbg(ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n",
ath10k_dbg(ar, ATH10K_DBG_HTT, "force cleanup msdu_id %hu\n",
msdu_id);
tx_done.discard = 1;
@ -157,6 +164,7 @@ void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb)
int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
{
struct ath10k *ar = htt->ar;
struct sk_buff *skb;
struct htt_cmd *cmd;
int len = 0;
@ -165,7 +173,7 @@ int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
len += sizeof(cmd->hdr);
len += sizeof(cmd->ver_req);
skb = ath10k_htc_alloc_skb(len);
skb = ath10k_htc_alloc_skb(ar, len);
if (!skb)
return -ENOMEM;
@ -184,6 +192,7 @@ int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt)
int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
{
struct ath10k *ar = htt->ar;
struct htt_stats_req *req;
struct sk_buff *skb;
struct htt_cmd *cmd;
@ -192,7 +201,7 @@ int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
len += sizeof(cmd->hdr);
len += sizeof(cmd->stats_req);
skb = ath10k_htc_alloc_skb(len);
skb = ath10k_htc_alloc_skb(ar, len);
if (!skb)
return -ENOMEM;
@ -214,7 +223,8 @@ int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
ret = ath10k_htc_send(&htt->ar->htc, htt->eid, skb);
if (ret) {
ath10k_warn("failed to send htt type stats request: %d", ret);
ath10k_warn(ar, "failed to send htt type stats request: %d",
ret);
dev_kfree_skb_any(skb);
return ret;
}
@ -224,6 +234,7 @@ int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u8 mask, u64 cookie)
int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
{
struct ath10k *ar = htt->ar;
struct sk_buff *skb;
struct htt_cmd *cmd;
struct htt_rx_ring_setup_ring *ring;
@ -242,7 +253,7 @@ int ath10k_htt_send_rx_ring_cfg_ll(struct ath10k_htt *htt)
len = sizeof(cmd->hdr) + sizeof(cmd->rx_setup.hdr)
+ (sizeof(*ring) * num_rx_ring);
skb = ath10k_htc_alloc_skb(len);
skb = ath10k_htc_alloc_skb(ar, len);
if (!skb)
return -ENOMEM;
@ -311,6 +322,7 @@ int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
u8 max_subfrms_ampdu,
u8 max_subfrms_amsdu)
{
struct ath10k *ar = htt->ar;
struct htt_aggr_conf *aggr_conf;
struct sk_buff *skb;
struct htt_cmd *cmd;
@ -328,7 +340,7 @@ int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
len = sizeof(cmd->hdr);
len += sizeof(cmd->aggr_conf);
skb = ath10k_htc_alloc_skb(len);
skb = ath10k_htc_alloc_skb(ar, len);
if (!skb)
return -ENOMEM;
@ -340,7 +352,7 @@ int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
aggr_conf->max_num_ampdu_subframes = max_subfrms_ampdu;
aggr_conf->max_num_amsdu_subframes = max_subfrms_amsdu;
ath10k_dbg(ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt h2t aggr cfg msg amsdu %d ampdu %d",
aggr_conf->max_num_amsdu_subframes,
aggr_conf->max_num_ampdu_subframes);
@ -355,7 +367,8 @@ int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
{
struct device *dev = htt->ar->dev;
struct ath10k *ar = htt->ar;
struct device *dev = ar->dev;
struct sk_buff *txdesc = NULL;
struct htt_cmd *cmd;
struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
@ -382,7 +395,7 @@ int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
htt->pending_tx[msdu_id] = msdu;
spin_unlock_bh(&htt->tx_lock);
txdesc = ath10k_htc_alloc_skb(len);
txdesc = ath10k_htc_alloc_skb(ar, len);
if (!txdesc) {
res = -ENOMEM;
goto err_free_msdu_id;
@ -429,7 +442,8 @@ err:
int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
{
struct device *dev = htt->ar->dev;
struct ath10k *ar = htt->ar;
struct device *dev = ar->dev;
struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)msdu->data;
struct ath10k_skb_cb *skb_cb = ATH10K_SKB_CB(msdu);
struct ath10k_hif_sg_item sg_items[2];
@ -545,11 +559,11 @@ int ath10k_htt_tx(struct ath10k_htt *htt, struct sk_buff *msdu)
skb_cb->htt.txbuf->cmd_tx.frags_paddr = __cpu_to_le32(frags_paddr);
skb_cb->htt.txbuf->cmd_tx.peerid = __cpu_to_le32(HTT_INVALID_PEERID);
ath10k_dbg(ATH10K_DBG_HTT,
ath10k_dbg(ar, ATH10K_DBG_HTT,
"htt tx flags0 %hhu flags1 %hu len %d id %hu frags_paddr %08x, msdu_paddr %08x vdev %hhu tid %hhu\n",
flags0, flags1, msdu->len, msdu_id, frags_paddr,
(u32)skb_cb->paddr, vdev_id, tid);
ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt tx msdu: ",
msdu->data, msdu->len);
sg_items[0].transfer_id = 0;

View File

@ -28,16 +28,19 @@
#define QCA988X_HW_2_0_CHIP_ID_REV 0x2
#define QCA988X_HW_2_0_FW_DIR "ath10k/QCA988X/hw2.0"
#define QCA988X_HW_2_0_FW_FILE "firmware.bin"
#define QCA988X_HW_2_0_FW_2_FILE "firmware-2.bin"
#define QCA988X_HW_2_0_FW_3_FILE "firmware-3.bin"
#define QCA988X_HW_2_0_OTP_FILE "otp.bin"
#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
#define ATH10K_FW_API2_FILE "firmware-2.bin"
#define ATH10K_FW_API3_FILE "firmware-3.bin"
/* includes also the null byte */
#define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
#define REG_DUMP_COUNT_QCA988X 60
struct ath10k_fw_ie {
__le32 id;
__le32 len;

File diff suppressed because it is too large Load Diff

View File

@ -26,12 +26,14 @@ struct ath10k_generic_iter {
int ret;
};
struct ath10k *ath10k_mac_create(void);
struct ath10k *ath10k_mac_create(size_t priv_size);
void ath10k_mac_destroy(struct ath10k *ar);
int ath10k_mac_register(struct ath10k *ar);
void ath10k_mac_unregister(struct ath10k *ar);
struct ath10k_vif *ath10k_get_arvif(struct ath10k *ar, u32 vdev_id);
void ath10k_reset_scan(unsigned long ptr);
void __ath10k_scan_finish(struct ath10k *ar);
void ath10k_scan_finish(struct ath10k *ar);
void ath10k_scan_timeout_work(struct work_struct *work);
void ath10k_offchan_tx_purge(struct ath10k *ar);
void ath10k_offchan_tx_work(struct work_struct *work);
void ath10k_mgmt_over_wmi_tx_purge(struct ath10k *ar);

File diff suppressed because it is too large Load Diff

View File

@ -23,9 +23,6 @@
#include "hw.h"
#include "ce.h"
/* FW dump area */
#define REG_DUMP_COUNT_QCA988X 60
/*
* maximum number of bytes that can be handled atomically by DiagRead/DiagWrite
*/
@ -103,12 +100,12 @@ struct pcie_state {
* NOTE: Structure is shared between Host software and Target firmware!
*/
struct ce_pipe_config {
u32 pipenum;
u32 pipedir;
u32 nentries;
u32 nbytes_max;
u32 flags;
u32 reserved;
__le32 pipenum;
__le32 pipedir;
__le32 nentries;
__le32 nbytes_max;
__le32 flags;
__le32 reserved;
};
/*
@ -130,17 +127,9 @@ struct ce_pipe_config {
/* Establish a mapping between a service/direction and a pipe. */
struct service_to_pipe {
u32 service_id;
u32 pipedir;
u32 pipenum;
};
enum ath10k_pci_features {
ATH10K_PCI_FEATURE_MSI_X = 0,
ATH10K_PCI_FEATURE_SOC_POWER_SAVE = 1,
/* keep last */
ATH10K_PCI_FEATURE_COUNT
__le32 service_id;
__le32 pipedir;
__le32 pipenum;
};
/* Per-pipe state. */
@ -169,8 +158,6 @@ struct ath10k_pci {
struct ath10k *ar;
void __iomem *mem;
DECLARE_BITMAP(features, ATH10K_PCI_FEATURE_COUNT);
/*
* Number of MSI interrupts granted, 0 --> using legacy PCI line
* interrupts.
@ -179,12 +166,6 @@ struct ath10k_pci {
struct tasklet_struct intr_tq;
struct tasklet_struct msi_fw_err;
struct tasklet_struct early_irq_tasklet;
int started;
atomic_t keep_awake_count;
bool verified_awake;
struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
@ -198,27 +179,15 @@ struct ath10k_pci {
/* Map CE id to ce_state */
struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
struct timer_list rx_post_retry;
};
static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
{
return ar->hif.priv;
}
static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
}
static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
return (struct ath10k_pci *)ar->drv_priv;
}
#define ATH10K_PCI_RX_POST_RETRY_MS 50
#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
#define PCIE_WAKE_TIMEOUT 5000 /* 5ms */
@ -242,35 +211,17 @@ static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
#define DIAG_ACCESS_CE_TIMEOUT_MS 10
/*
* This API allows the Host to access Target registers directly
* and relatively efficiently over PCIe.
* This allows the Host to avoid extra overhead associated with
* sending a message to firmware and waiting for a response message
* from firmware, as is done on other interconnects.
/* Target exposes its registers for direct access. However before host can
* access them it needs to make sure the target is awake (ath10k_pci_wake,
* ath10k_pci_wake_wait, ath10k_pci_is_awake). Once target is awake it won't go
* to sleep unless host tells it to (ath10k_pci_sleep).
*
* Yet there is some complexity with direct accesses because the
* Target's power state is not known a priori. The Host must issue
* special PCIe reads/writes in order to explicitly wake the Target
* and to verify that it is awake and will remain awake.
* If host tries to access target registers without waking it up it can
* scribble over host memory.
*
* Usage:
*
* Use ath10k_pci_read32 and ath10k_pci_write32 to access Target space.
* These calls must be bracketed by ath10k_pci_wake and
* ath10k_pci_sleep. A single BEGIN/END pair is adequate for
* multiple READ/WRITE operations.
*
* Use ath10k_pci_wake to put the Target in a state in
* which it is legal for the Host to directly access it. This
* may involve waking the Target from a low power state, which
* may take up to 2Ms!
*
* Use ath10k_pci_sleep to tell the Target that as far as
* this code path is concerned, it no longer needs to remain
* directly accessible. BEGIN/END is under a reference counter;
* multiple code paths may issue BEGIN/END on a single targid.
* If target is asleep waking it up may take up to even 2ms.
*/
static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset,
u32 value)
{
@ -296,25 +247,18 @@ static inline void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val)
ath10k_pci_write32(ar, RTC_SOC_BASE_ADDRESS + addr, val);
}
int ath10k_do_pci_wake(struct ath10k *ar);
void ath10k_do_pci_sleep(struct ath10k *ar);
static inline int ath10k_pci_wake(struct ath10k *ar)
static inline u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
return ath10k_do_pci_wake(ar);
return 0;
return ioread32(ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
}
static inline void ath10k_pci_sleep(struct ath10k *ar)
static inline void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
if (test_bit(ATH10K_PCI_FEATURE_SOC_POWER_SAVE, ar_pci->features))
ath10k_do_pci_sleep(ar);
iowrite32(val, ar_pci->mem + PCIE_LOCAL_BASE_ADDRESS + addr);
}
#endif /* _PCI_H_ */

View File

@ -0,0 +1,561 @@
/*
* Copyright (c) 2013 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/relay.h>
#include "core.h"
#include "debug.h"
static void send_fft_sample(struct ath10k *ar,
const struct fft_sample_tlv *fft_sample_tlv)
{
int length;
if (!ar->spectral.rfs_chan_spec_scan)
return;
length = __be16_to_cpu(fft_sample_tlv->length) +
sizeof(*fft_sample_tlv);
relay_write(ar->spectral.rfs_chan_spec_scan, fft_sample_tlv, length);
}
static uint8_t get_max_exp(s8 max_index, u16 max_magnitude, size_t bin_len,
u8 *data)
{
int dc_pos;
u8 max_exp;
dc_pos = bin_len / 2;
/* peak index outside of bins */
if (dc_pos < max_index || -dc_pos >= max_index)
return 0;
for (max_exp = 0; max_exp < 8; max_exp++) {
if (data[dc_pos + max_index] == (max_magnitude >> max_exp))
break;
}
/* max_exp not found */
if (data[dc_pos + max_index] != (max_magnitude >> max_exp))
return 0;
return max_exp;
}
int ath10k_spectral_process_fft(struct ath10k *ar,
struct wmi_single_phyerr_rx_event *event,
struct phyerr_fft_report *fftr,
size_t bin_len, u64 tsf)
{
struct fft_sample_ath10k *fft_sample;
u8 buf[sizeof(*fft_sample) + SPECTRAL_ATH10K_MAX_NUM_BINS];
u16 freq1, freq2, total_gain_db, base_pwr_db, length, peak_mag;
u32 reg0, reg1, nf_list1, nf_list2;
u8 chain_idx, *bins;
int dc_pos;
fft_sample = (struct fft_sample_ath10k *)&buf;
if (bin_len < 64 || bin_len > SPECTRAL_ATH10K_MAX_NUM_BINS)
return -EINVAL;
reg0 = __le32_to_cpu(fftr->reg0);
reg1 = __le32_to_cpu(fftr->reg1);
length = sizeof(*fft_sample) - sizeof(struct fft_sample_tlv) + bin_len;
fft_sample->tlv.type = ATH_FFT_SAMPLE_ATH10K;
fft_sample->tlv.length = __cpu_to_be16(length);
/* TODO: there might be a reason why the hardware reports 20/40/80 MHz,
* but the results/plots suggest that its actually 22/44/88 MHz.
*/
switch (event->hdr.chan_width_mhz) {
case 20:
fft_sample->chan_width_mhz = 22;
break;
case 40:
fft_sample->chan_width_mhz = 44;
break;
case 80:
/* TODO: As experiments with an analogue sender and various
* configuaritions (fft-sizes of 64/128/256 and 20/40/80 Mhz)
* show, the particular configuration of 80 MHz/64 bins does
* not match with the other smaples at all. Until the reason
* for that is found, don't report these samples.
*/
if (bin_len == 64)
return -EINVAL;
fft_sample->chan_width_mhz = 88;
break;
default:
fft_sample->chan_width_mhz = event->hdr.chan_width_mhz;
}
fft_sample->relpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB);
fft_sample->avgpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB);
peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG);
fft_sample->max_magnitude = __cpu_to_be16(peak_mag);
fft_sample->max_index = MS(reg0, SEARCH_FFT_REPORT_REG0_PEAK_SIDX);
fft_sample->rssi = event->hdr.rssi_combined;
total_gain_db = MS(reg0, SEARCH_FFT_REPORT_REG0_TOTAL_GAIN_DB);
base_pwr_db = MS(reg0, SEARCH_FFT_REPORT_REG0_BASE_PWR_DB);
fft_sample->total_gain_db = __cpu_to_be16(total_gain_db);
fft_sample->base_pwr_db = __cpu_to_be16(base_pwr_db);
freq1 = __le16_to_cpu(event->hdr.freq1);
freq2 = __le16_to_cpu(event->hdr.freq2);
fft_sample->freq1 = __cpu_to_be16(freq1);
fft_sample->freq2 = __cpu_to_be16(freq2);
nf_list1 = __le32_to_cpu(event->hdr.nf_list_1);
nf_list2 = __le32_to_cpu(event->hdr.nf_list_2);
chain_idx = MS(reg0, SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX);
switch (chain_idx) {
case 0:
fft_sample->noise = __cpu_to_be16(nf_list1 & 0xffffu);
break;
case 1:
fft_sample->noise = __cpu_to_be16((nf_list1 >> 16) & 0xffffu);
break;
case 2:
fft_sample->noise = __cpu_to_be16(nf_list2 & 0xffffu);
break;
case 3:
fft_sample->noise = __cpu_to_be16((nf_list2 >> 16) & 0xffffu);
break;
}
bins = (u8 *)fftr;
bins += sizeof(*fftr);
fft_sample->tsf = __cpu_to_be64(tsf);
/* max_exp has been directly reported by previous hardware (ath9k),
* maybe its possible to get it by other means?
*/
fft_sample->max_exp = get_max_exp(fft_sample->max_index, peak_mag,
bin_len, bins);
memcpy(fft_sample->data, bins, bin_len);
/* DC value (value in the middle) is the blind spot of the spectral
* sample and invalid, interpolate it.
*/
dc_pos = bin_len / 2;
fft_sample->data[dc_pos] = (fft_sample->data[dc_pos + 1] +
fft_sample->data[dc_pos - 1]) / 2;
send_fft_sample(ar, &fft_sample->tlv);
return 0;
}
static struct ath10k_vif *ath10k_get_spectral_vdev(struct ath10k *ar)
{
struct ath10k_vif *arvif;
lockdep_assert_held(&ar->conf_mutex);
if (list_empty(&ar->arvifs))
return NULL;
/* if there already is a vif doing spectral, return that. */
list_for_each_entry(arvif, &ar->arvifs, list)
if (arvif->spectral_enabled)
return arvif;
/* otherwise, return the first vif. */
return list_first_entry(&ar->arvifs, typeof(*arvif), list);
}
static int ath10k_spectral_scan_trigger(struct ath10k *ar)
{
struct ath10k_vif *arvif;
int res;
int vdev_id;
lockdep_assert_held(&ar->conf_mutex);
arvif = ath10k_get_spectral_vdev(ar);
if (!arvif)
return -ENODEV;
vdev_id = arvif->vdev_id;
if (ar->spectral.mode == SPECTRAL_DISABLED)
return 0;
res = ath10k_wmi_vdev_spectral_enable(ar, vdev_id,
WMI_SPECTRAL_TRIGGER_CMD_CLEAR,
WMI_SPECTRAL_ENABLE_CMD_ENABLE);
if (res < 0)
return res;
res = ath10k_wmi_vdev_spectral_enable(ar, vdev_id,
WMI_SPECTRAL_TRIGGER_CMD_TRIGGER,
WMI_SPECTRAL_ENABLE_CMD_ENABLE);
if (res < 0)
return res;
return 0;
}
static int ath10k_spectral_scan_config(struct ath10k *ar,
enum ath10k_spectral_mode mode)
{
struct wmi_vdev_spectral_conf_arg arg;
struct ath10k_vif *arvif;
int vdev_id, count, res = 0;
lockdep_assert_held(&ar->conf_mutex);
arvif = ath10k_get_spectral_vdev(ar);
if (!arvif)
return -ENODEV;
vdev_id = arvif->vdev_id;
arvif->spectral_enabled = (mode != SPECTRAL_DISABLED);
ar->spectral.mode = mode;
res = ath10k_wmi_vdev_spectral_enable(ar, vdev_id,
WMI_SPECTRAL_TRIGGER_CMD_CLEAR,
WMI_SPECTRAL_ENABLE_CMD_DISABLE);
if (res < 0) {
ath10k_warn(ar, "failed to enable spectral scan: %d\n", res);
return res;
}
if (mode == SPECTRAL_DISABLED)
return 0;
if (mode == SPECTRAL_BACKGROUND)
count = WMI_SPECTRAL_COUNT_DEFAULT;
else
count = max_t(u8, 1, ar->spectral.config.count);
arg.vdev_id = vdev_id;
arg.scan_count = count;
arg.scan_period = WMI_SPECTRAL_PERIOD_DEFAULT;
arg.scan_priority = WMI_SPECTRAL_PRIORITY_DEFAULT;
arg.scan_fft_size = ar->spectral.config.fft_size;
arg.scan_gc_ena = WMI_SPECTRAL_GC_ENA_DEFAULT;
arg.scan_restart_ena = WMI_SPECTRAL_RESTART_ENA_DEFAULT;
arg.scan_noise_floor_ref = WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT;
arg.scan_init_delay = WMI_SPECTRAL_INIT_DELAY_DEFAULT;
arg.scan_nb_tone_thr = WMI_SPECTRAL_NB_TONE_THR_DEFAULT;
arg.scan_str_bin_thr = WMI_SPECTRAL_STR_BIN_THR_DEFAULT;
arg.scan_wb_rpt_mode = WMI_SPECTRAL_WB_RPT_MODE_DEFAULT;
arg.scan_rssi_rpt_mode = WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT;
arg.scan_rssi_thr = WMI_SPECTRAL_RSSI_THR_DEFAULT;
arg.scan_pwr_format = WMI_SPECTRAL_PWR_FORMAT_DEFAULT;
arg.scan_rpt_mode = WMI_SPECTRAL_RPT_MODE_DEFAULT;
arg.scan_bin_scale = WMI_SPECTRAL_BIN_SCALE_DEFAULT;
arg.scan_dbm_adj = WMI_SPECTRAL_DBM_ADJ_DEFAULT;
arg.scan_chn_mask = WMI_SPECTRAL_CHN_MASK_DEFAULT;
res = ath10k_wmi_vdev_spectral_conf(ar, &arg);
if (res < 0) {
ath10k_warn(ar, "failed to configure spectral scan: %d\n", res);
return res;
}
return 0;
}
static ssize_t read_file_spec_scan_ctl(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath10k *ar = file->private_data;
char *mode = "";
unsigned int len;
enum ath10k_spectral_mode spectral_mode;
mutex_lock(&ar->conf_mutex);
spectral_mode = ar->spectral.mode;
mutex_unlock(&ar->conf_mutex);
switch (spectral_mode) {
case SPECTRAL_DISABLED:
mode = "disable";
break;
case SPECTRAL_BACKGROUND:
mode = "background";
break;
case SPECTRAL_MANUAL:
mode = "manual";
break;
}
len = strlen(mode);
return simple_read_from_buffer(user_buf, count, ppos, mode, len);
}
static ssize_t write_file_spec_scan_ctl(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath10k *ar = file->private_data;
char buf[32];
ssize_t len;
int res;
len = min(count, sizeof(buf) - 1);
if (copy_from_user(buf, user_buf, len))
return -EFAULT;
buf[len] = '\0';
mutex_lock(&ar->conf_mutex);
if (strncmp("trigger", buf, 7) == 0) {
if (ar->spectral.mode == SPECTRAL_MANUAL ||
ar->spectral.mode == SPECTRAL_BACKGROUND) {
/* reset the configuration to adopt possibly changed
* debugfs parameters
*/
res = ath10k_spectral_scan_config(ar,
ar->spectral.mode);
if (res < 0) {
ath10k_warn(ar, "failed to reconfigure spectral scan: %d\n",
res);
}
res = ath10k_spectral_scan_trigger(ar);
if (res < 0) {
ath10k_warn(ar, "failed to trigger spectral scan: %d\n",
res);
}
} else {
res = -EINVAL;
}
} else if (strncmp("background", buf, 9) == 0) {
res = ath10k_spectral_scan_config(ar, SPECTRAL_BACKGROUND);
} else if (strncmp("manual", buf, 6) == 0) {
res = ath10k_spectral_scan_config(ar, SPECTRAL_MANUAL);
} else if (strncmp("disable", buf, 7) == 0) {
res = ath10k_spectral_scan_config(ar, SPECTRAL_DISABLED);
} else {
res = -EINVAL;
}
mutex_unlock(&ar->conf_mutex);
if (res < 0)
return res;
return count;
}
static const struct file_operations fops_spec_scan_ctl = {
.read = read_file_spec_scan_ctl,
.write = write_file_spec_scan_ctl,
.open = simple_open,
.owner = THIS_MODULE,
.llseek = default_llseek,
};
static ssize_t read_file_spectral_count(struct file *file,
char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath10k *ar = file->private_data;
char buf[32];
unsigned int len;
u8 spectral_count;
mutex_lock(&ar->conf_mutex);
spectral_count = ar->spectral.config.count;
mutex_unlock(&ar->conf_mutex);
len = sprintf(buf, "%d\n", spectral_count);
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
}
static ssize_t write_file_spectral_count(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath10k *ar = file->private_data;
unsigned long val;
char buf[32];
ssize_t len;
len = min(count, sizeof(buf) - 1);
if (copy_from_user(buf, user_buf, len))
return -EFAULT;
buf[len] = '\0';
if (kstrtoul(buf, 0, &val))
return -EINVAL;
if (val < 0 || val > 255)
return -EINVAL;
mutex_lock(&ar->conf_mutex);
ar->spectral.config.count = val;
mutex_unlock(&ar->conf_mutex);
return count;
}
static const struct file_operations fops_spectral_count = {
.read = read_file_spectral_count,
.write = write_file_spectral_count,
.open = simple_open,
.owner = THIS_MODULE,
.llseek = default_llseek,
};
static ssize_t read_file_spectral_bins(struct file *file,
char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath10k *ar = file->private_data;
char buf[32];
unsigned int len, bins, fft_size, bin_scale;
mutex_lock(&ar->conf_mutex);
fft_size = ar->spectral.config.fft_size;
bin_scale = WMI_SPECTRAL_BIN_SCALE_DEFAULT;
bins = 1 << (fft_size - bin_scale);
mutex_unlock(&ar->conf_mutex);
len = sprintf(buf, "%d\n", bins);
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
}
static ssize_t write_file_spectral_bins(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath10k *ar = file->private_data;
unsigned long val;
char buf[32];
ssize_t len;
len = min(count, sizeof(buf) - 1);
if (copy_from_user(buf, user_buf, len))
return -EFAULT;
buf[len] = '\0';
if (kstrtoul(buf, 0, &val))
return -EINVAL;
if (val < 64 || val > SPECTRAL_ATH10K_MAX_NUM_BINS)
return -EINVAL;
if (!is_power_of_2(val))
return -EINVAL;
mutex_lock(&ar->conf_mutex);
ar->spectral.config.fft_size = ilog2(val);
ar->spectral.config.fft_size += WMI_SPECTRAL_BIN_SCALE_DEFAULT;
mutex_unlock(&ar->conf_mutex);
return count;
}
static const struct file_operations fops_spectral_bins = {
.read = read_file_spectral_bins,
.write = write_file_spectral_bins,
.open = simple_open,
.owner = THIS_MODULE,
.llseek = default_llseek,
};
static struct dentry *create_buf_file_handler(const char *filename,
struct dentry *parent,
umode_t mode,
struct rchan_buf *buf,
int *is_global)
{
struct dentry *buf_file;
buf_file = debugfs_create_file(filename, mode, parent, buf,
&relay_file_operations);
*is_global = 1;
return buf_file;
}
static int remove_buf_file_handler(struct dentry *dentry)
{
debugfs_remove(dentry);
return 0;
}
static struct rchan_callbacks rfs_spec_scan_cb = {
.create_buf_file = create_buf_file_handler,
.remove_buf_file = remove_buf_file_handler,
};
int ath10k_spectral_start(struct ath10k *ar)
{
struct ath10k_vif *arvif;
lockdep_assert_held(&ar->conf_mutex);
list_for_each_entry(arvif, &ar->arvifs, list)
arvif->spectral_enabled = 0;
ar->spectral.mode = SPECTRAL_DISABLED;
ar->spectral.config.count = WMI_SPECTRAL_COUNT_DEFAULT;
ar->spectral.config.fft_size = WMI_SPECTRAL_FFT_SIZE_DEFAULT;
return 0;
}
int ath10k_spectral_vif_stop(struct ath10k_vif *arvif)
{
if (!arvif->spectral_enabled)
return 0;
return ath10k_spectral_scan_config(arvif->ar, SPECTRAL_DISABLED);
}
int ath10k_spectral_create(struct ath10k *ar)
{
ar->spectral.rfs_chan_spec_scan = relay_open("spectral_scan",
ar->debug.debugfs_phy,
1024, 256,
&rfs_spec_scan_cb, NULL);
debugfs_create_file("spectral_scan_ctl",
S_IRUSR | S_IWUSR,
ar->debug.debugfs_phy, ar,
&fops_spec_scan_ctl);
debugfs_create_file("spectral_count",
S_IRUSR | S_IWUSR,
ar->debug.debugfs_phy, ar,
&fops_spectral_count);
debugfs_create_file("spectral_bins",
S_IRUSR | S_IWUSR,
ar->debug.debugfs_phy, ar,
&fops_spectral_bins);
return 0;
}
void ath10k_spectral_destroy(struct ath10k *ar)
{
if (ar->spectral.rfs_chan_spec_scan) {
relay_close(ar->spectral.rfs_chan_spec_scan);
ar->spectral.rfs_chan_spec_scan = NULL;
}
}

View File

@ -0,0 +1,90 @@
/*
* Copyright (c) 2013 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef SPECTRAL_H
#define SPECTRAL_H
#include "../spectral_common.h"
/**
* struct ath10k_spec_scan - parameters for Atheros spectral scan
*
* @count: number of scan results requested for manual mode
* @fft_size: number of bins to be requested = 2^(fft_size - bin_scale)
*/
struct ath10k_spec_scan {
u8 count;
u8 fft_size;
};
/* enum ath10k_spectral_mode:
*
* @SPECTRAL_DISABLED: spectral mode is disabled
* @SPECTRAL_BACKGROUND: hardware sends samples when it is not busy with
* something else.
* @SPECTRAL_MANUAL: spectral scan is enabled, triggering for samples
* is performed manually.
*/
enum ath10k_spectral_mode {
SPECTRAL_DISABLED = 0,
SPECTRAL_BACKGROUND,
SPECTRAL_MANUAL,
};
#ifdef CONFIG_ATH10K_DEBUGFS
int ath10k_spectral_process_fft(struct ath10k *ar,
struct wmi_single_phyerr_rx_event *event,
struct phyerr_fft_report *fftr,
size_t bin_len, u64 tsf);
int ath10k_spectral_start(struct ath10k *ar);
int ath10k_spectral_vif_stop(struct ath10k_vif *arvif);
int ath10k_spectral_create(struct ath10k *ar);
void ath10k_spectral_destroy(struct ath10k *ar);
#else
static inline int
ath10k_spectral_process_fft(struct ath10k *ar,
struct wmi_single_phyerr_rx_event *event,
struct phyerr_fft_report *fftr,
size_t bin_len, u64 tsf)
{
return 0;
}
static inline int ath10k_spectral_start(struct ath10k *ar)
{
return 0;
}
static inline int ath10k_spectral_vif_stop(struct ath10k_vif *arvif)
{
return 0;
}
static inline int ath10k_spectral_create(struct ath10k *ar)
{
return 0;
}
static inline void ath10k_spectral_destroy(struct ath10k *ar)
{
}
#endif /* CONFIG_ATH10K_DEBUGFS */
#endif /* SPECTRAL_H */

View File

@ -32,14 +32,14 @@ static void ath10k_report_offchan_tx(struct ath10k *ar, struct sk_buff *skb)
* offchan_tx_skb. */
spin_lock_bh(&ar->data_lock);
if (ar->offchan_tx_skb != skb) {
ath10k_warn("completed old offchannel frame\n");
ath10k_warn(ar, "completed old offchannel frame\n");
goto out;
}
complete(&ar->offchan_tx_completed);
ar->offchan_tx_skb = NULL; /* just for sanity */
ath10k_dbg(ATH10K_DBG_HTT, "completed offchannel skb %p\n", skb);
ath10k_dbg(ar, ATH10K_DBG_HTT, "completed offchannel skb %p\n", skb);
out:
spin_unlock_bh(&ar->data_lock);
}
@ -47,18 +47,19 @@ out:
void ath10k_txrx_tx_unref(struct ath10k_htt *htt,
const struct htt_tx_done *tx_done)
{
struct device *dev = htt->ar->dev;
struct ath10k *ar = htt->ar;
struct device *dev = ar->dev;
struct ieee80211_tx_info *info;
struct ath10k_skb_cb *skb_cb;
struct sk_buff *msdu;
lockdep_assert_held(&htt->tx_lock);
ath10k_dbg(ATH10K_DBG_HTT, "htt tx completion msdu_id %u discard %d no_ack %d\n",
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion msdu_id %u discard %d no_ack %d\n",
tx_done->msdu_id, !!tx_done->discard, !!tx_done->no_ack);
if (tx_done->msdu_id >= htt->max_num_pending_tx) {
ath10k_warn("warning: msdu_id %d too big, ignoring\n",
ath10k_warn(ar, "warning: msdu_id %d too big, ignoring\n",
tx_done->msdu_id);
return;
}
@ -182,7 +183,7 @@ void ath10k_peer_map_event(struct ath10k_htt *htt,
wake_up(&ar->peer_mapping_wq);
}
ath10k_dbg(ATH10K_DBG_HTT, "htt peer map vdev %d peer %pM id %d\n",
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt peer map vdev %d peer %pM id %d\n",
ev->vdev_id, ev->addr, ev->peer_id);
set_bit(ev->peer_id, peer->peer_ids);
@ -199,12 +200,12 @@ void ath10k_peer_unmap_event(struct ath10k_htt *htt,
spin_lock_bh(&ar->data_lock);
peer = ath10k_peer_find_by_id(ar, ev->peer_id);
if (!peer) {
ath10k_warn("peer-unmap-event: unknown peer id %d\n",
ath10k_warn(ar, "peer-unmap-event: unknown peer id %d\n",
ev->peer_id);
goto exit;
}
ath10k_dbg(ATH10K_DBG_HTT, "htt peer unmap vdev %d peer %pM id %d\n",
ath10k_dbg(ar, ATH10K_DBG_HTT, "htt peer unmap vdev %d peer %pM id %d\n",
peer->vdev_id, peer->addr, ev->peer_id);
clear_bit(ev->peer_id, peer->peer_ids);

File diff suppressed because it is too large Load Diff

View File

@ -73,116 +73,279 @@ struct wmi_cmd_hdr {
#define HTC_PROTOCOL_VERSION 0x0002
#define WMI_PROTOCOL_VERSION 0x0002
enum wmi_service_id {
WMI_SERVICE_BEACON_OFFLOAD = 0, /* beacon offload */
WMI_SERVICE_SCAN_OFFLOAD, /* scan offload */
WMI_SERVICE_ROAM_OFFLOAD, /* roam offload */
WMI_SERVICE_BCN_MISS_OFFLOAD, /* beacon miss offload */
WMI_SERVICE_STA_PWRSAVE, /* fake sleep + basic power save */
WMI_SERVICE_STA_ADVANCED_PWRSAVE, /* uapsd, pspoll, force sleep */
WMI_SERVICE_AP_UAPSD, /* uapsd on AP */
WMI_SERVICE_AP_DFS, /* DFS on AP */
WMI_SERVICE_11AC, /* supports 11ac */
WMI_SERVICE_BLOCKACK, /* Supports triggering ADDBA/DELBA from host*/
WMI_SERVICE_PHYERR, /* PHY error */
WMI_SERVICE_BCN_FILTER, /* Beacon filter support */
WMI_SERVICE_RTT, /* RTT (round trip time) support */
WMI_SERVICE_RATECTRL, /* Rate-control */
WMI_SERVICE_WOW, /* WOW Support */
WMI_SERVICE_RATECTRL_CACHE, /* Rate-control caching */
WMI_SERVICE_IRAM_TIDS, /* TIDs in IRAM */
WMI_SERVICE_ARPNS_OFFLOAD, /* ARP NS Offload support */
WMI_SERVICE_NLO, /* Network list offload service */
WMI_SERVICE_GTK_OFFLOAD, /* GTK offload */
WMI_SERVICE_SCAN_SCH, /* Scan Scheduler Service */
WMI_SERVICE_CSA_OFFLOAD, /* CSA offload service */
WMI_SERVICE_CHATTER, /* Chatter service */
WMI_SERVICE_COEX_FREQAVOID, /* FW report freq range to avoid */
WMI_SERVICE_PACKET_POWER_SAVE, /* packet power save service */
WMI_SERVICE_FORCE_FW_HANG, /* To test fw recovery mechanism */
WMI_SERVICE_GPIO, /* GPIO service */
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM, /* Modulated DTIM support */
WMI_STA_UAPSD_BASIC_AUTO_TRIG, /* UAPSD AC Trigger Generation */
WMI_STA_UAPSD_VAR_AUTO_TRIG, /* -do- */
WMI_SERVICE_STA_KEEP_ALIVE, /* STA keep alive mechanism support */
WMI_SERVICE_TX_ENCAP, /* Packet type for TX encapsulation */
enum wmi_service {
WMI_SERVICE_BEACON_OFFLOAD = 0,
WMI_SERVICE_SCAN_OFFLOAD,
WMI_SERVICE_ROAM_OFFLOAD,
WMI_SERVICE_BCN_MISS_OFFLOAD,
WMI_SERVICE_STA_PWRSAVE,
WMI_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_SERVICE_AP_UAPSD,
WMI_SERVICE_AP_DFS,
WMI_SERVICE_11AC,
WMI_SERVICE_BLOCKACK,
WMI_SERVICE_PHYERR,
WMI_SERVICE_BCN_FILTER,
WMI_SERVICE_RTT,
WMI_SERVICE_RATECTRL,
WMI_SERVICE_WOW,
WMI_SERVICE_RATECTRL_CACHE,
WMI_SERVICE_IRAM_TIDS,
WMI_SERVICE_ARPNS_OFFLOAD,
WMI_SERVICE_NLO,
WMI_SERVICE_GTK_OFFLOAD,
WMI_SERVICE_SCAN_SCH,
WMI_SERVICE_CSA_OFFLOAD,
WMI_SERVICE_CHATTER,
WMI_SERVICE_COEX_FREQAVOID,
WMI_SERVICE_PACKET_POWER_SAVE,
WMI_SERVICE_FORCE_FW_HANG,
WMI_SERVICE_GPIO,
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM,
WMI_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG,
WMI_SERVICE_STA_UAPSD_VAR_AUTO_TRIG,
WMI_SERVICE_STA_KEEP_ALIVE,
WMI_SERVICE_TX_ENCAP,
WMI_SERVICE_BURST,
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT,
};
WMI_SERVICE_LAST,
WMI_MAX_SERVICE = 64 /* max service */
enum wmi_10x_service {
WMI_10X_SERVICE_BEACON_OFFLOAD = 0,
WMI_10X_SERVICE_SCAN_OFFLOAD,
WMI_10X_SERVICE_ROAM_OFFLOAD,
WMI_10X_SERVICE_BCN_MISS_OFFLOAD,
WMI_10X_SERVICE_STA_PWRSAVE,
WMI_10X_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_10X_SERVICE_AP_UAPSD,
WMI_10X_SERVICE_AP_DFS,
WMI_10X_SERVICE_11AC,
WMI_10X_SERVICE_BLOCKACK,
WMI_10X_SERVICE_PHYERR,
WMI_10X_SERVICE_BCN_FILTER,
WMI_10X_SERVICE_RTT,
WMI_10X_SERVICE_RATECTRL,
WMI_10X_SERVICE_WOW,
WMI_10X_SERVICE_RATECTRL_CACHE,
WMI_10X_SERVICE_IRAM_TIDS,
WMI_10X_SERVICE_BURST,
/* introduced in 10.2 */
WMI_10X_SERVICE_SMART_ANTENNA_SW_SUPPORT,
WMI_10X_SERVICE_FORCE_FW_HANG,
WMI_10X_SERVICE_SMART_ANTENNA_HW_SUPPORT,
};
enum wmi_main_service {
WMI_MAIN_SERVICE_BEACON_OFFLOAD = 0,
WMI_MAIN_SERVICE_SCAN_OFFLOAD,
WMI_MAIN_SERVICE_ROAM_OFFLOAD,
WMI_MAIN_SERVICE_BCN_MISS_OFFLOAD,
WMI_MAIN_SERVICE_STA_PWRSAVE,
WMI_MAIN_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_MAIN_SERVICE_AP_UAPSD,
WMI_MAIN_SERVICE_AP_DFS,
WMI_MAIN_SERVICE_11AC,
WMI_MAIN_SERVICE_BLOCKACK,
WMI_MAIN_SERVICE_PHYERR,
WMI_MAIN_SERVICE_BCN_FILTER,
WMI_MAIN_SERVICE_RTT,
WMI_MAIN_SERVICE_RATECTRL,
WMI_MAIN_SERVICE_WOW,
WMI_MAIN_SERVICE_RATECTRL_CACHE,
WMI_MAIN_SERVICE_IRAM_TIDS,
WMI_MAIN_SERVICE_ARPNS_OFFLOAD,
WMI_MAIN_SERVICE_NLO,
WMI_MAIN_SERVICE_GTK_OFFLOAD,
WMI_MAIN_SERVICE_SCAN_SCH,
WMI_MAIN_SERVICE_CSA_OFFLOAD,
WMI_MAIN_SERVICE_CHATTER,
WMI_MAIN_SERVICE_COEX_FREQAVOID,
WMI_MAIN_SERVICE_PACKET_POWER_SAVE,
WMI_MAIN_SERVICE_FORCE_FW_HANG,
WMI_MAIN_SERVICE_GPIO,
WMI_MAIN_SERVICE_STA_DTIM_PS_MODULATED_DTIM,
WMI_MAIN_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG,
WMI_MAIN_SERVICE_STA_UAPSD_VAR_AUTO_TRIG,
WMI_MAIN_SERVICE_STA_KEEP_ALIVE,
WMI_MAIN_SERVICE_TX_ENCAP,
};
static inline char *wmi_service_name(int service_id)
{
#define SVCSTR(x) case x: return #x
switch (service_id) {
case WMI_SERVICE_BEACON_OFFLOAD:
return "BEACON_OFFLOAD";
case WMI_SERVICE_SCAN_OFFLOAD:
return "SCAN_OFFLOAD";
case WMI_SERVICE_ROAM_OFFLOAD:
return "ROAM_OFFLOAD";
case WMI_SERVICE_BCN_MISS_OFFLOAD:
return "BCN_MISS_OFFLOAD";
case WMI_SERVICE_STA_PWRSAVE:
return "STA_PWRSAVE";
case WMI_SERVICE_STA_ADVANCED_PWRSAVE:
return "STA_ADVANCED_PWRSAVE";
case WMI_SERVICE_AP_UAPSD:
return "AP_UAPSD";
case WMI_SERVICE_AP_DFS:
return "AP_DFS";
case WMI_SERVICE_11AC:
return "11AC";
case WMI_SERVICE_BLOCKACK:
return "BLOCKACK";
case WMI_SERVICE_PHYERR:
return "PHYERR";
case WMI_SERVICE_BCN_FILTER:
return "BCN_FILTER";
case WMI_SERVICE_RTT:
return "RTT";
case WMI_SERVICE_RATECTRL:
return "RATECTRL";
case WMI_SERVICE_WOW:
return "WOW";
case WMI_SERVICE_RATECTRL_CACHE:
return "RATECTRL CACHE";
case WMI_SERVICE_IRAM_TIDS:
return "IRAM TIDS";
case WMI_SERVICE_ARPNS_OFFLOAD:
return "ARPNS_OFFLOAD";
case WMI_SERVICE_NLO:
return "NLO";
case WMI_SERVICE_GTK_OFFLOAD:
return "GTK_OFFLOAD";
case WMI_SERVICE_SCAN_SCH:
return "SCAN_SCH";
case WMI_SERVICE_CSA_OFFLOAD:
return "CSA_OFFLOAD";
case WMI_SERVICE_CHATTER:
return "CHATTER";
case WMI_SERVICE_COEX_FREQAVOID:
return "COEX_FREQAVOID";
case WMI_SERVICE_PACKET_POWER_SAVE:
return "PACKET_POWER_SAVE";
case WMI_SERVICE_FORCE_FW_HANG:
return "FORCE FW HANG";
case WMI_SERVICE_GPIO:
return "GPIO";
case WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM:
return "MODULATED DTIM";
case WMI_STA_UAPSD_BASIC_AUTO_TRIG:
return "BASIC UAPSD";
case WMI_STA_UAPSD_VAR_AUTO_TRIG:
return "VAR UAPSD";
case WMI_SERVICE_STA_KEEP_ALIVE:
return "STA KEEP ALIVE";
case WMI_SERVICE_TX_ENCAP:
return "TX ENCAP";
SVCSTR(WMI_SERVICE_BEACON_OFFLOAD);
SVCSTR(WMI_SERVICE_SCAN_OFFLOAD);
SVCSTR(WMI_SERVICE_ROAM_OFFLOAD);
SVCSTR(WMI_SERVICE_BCN_MISS_OFFLOAD);
SVCSTR(WMI_SERVICE_STA_PWRSAVE);
SVCSTR(WMI_SERVICE_STA_ADVANCED_PWRSAVE);
SVCSTR(WMI_SERVICE_AP_UAPSD);
SVCSTR(WMI_SERVICE_AP_DFS);
SVCSTR(WMI_SERVICE_11AC);
SVCSTR(WMI_SERVICE_BLOCKACK);
SVCSTR(WMI_SERVICE_PHYERR);
SVCSTR(WMI_SERVICE_BCN_FILTER);
SVCSTR(WMI_SERVICE_RTT);
SVCSTR(WMI_SERVICE_RATECTRL);
SVCSTR(WMI_SERVICE_WOW);
SVCSTR(WMI_SERVICE_RATECTRL_CACHE);
SVCSTR(WMI_SERVICE_IRAM_TIDS);
SVCSTR(WMI_SERVICE_ARPNS_OFFLOAD);
SVCSTR(WMI_SERVICE_NLO);
SVCSTR(WMI_SERVICE_GTK_OFFLOAD);
SVCSTR(WMI_SERVICE_SCAN_SCH);
SVCSTR(WMI_SERVICE_CSA_OFFLOAD);
SVCSTR(WMI_SERVICE_CHATTER);
SVCSTR(WMI_SERVICE_COEX_FREQAVOID);
SVCSTR(WMI_SERVICE_PACKET_POWER_SAVE);
SVCSTR(WMI_SERVICE_FORCE_FW_HANG);
SVCSTR(WMI_SERVICE_GPIO);
SVCSTR(WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM);
SVCSTR(WMI_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG);
SVCSTR(WMI_SERVICE_STA_UAPSD_VAR_AUTO_TRIG);
SVCSTR(WMI_SERVICE_STA_KEEP_ALIVE);
SVCSTR(WMI_SERVICE_TX_ENCAP);
SVCSTR(WMI_SERVICE_BURST);
SVCSTR(WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT);
SVCSTR(WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT);
default:
return "UNKNOWN SERVICE\n";
return NULL;
}
#undef SVCSTR
}
#define WMI_MAX_SERVICE 64
#define WMI_SERVICE_IS_ENABLED(wmi_svc_bmap, svc_id) \
(__le32_to_cpu((wmi_svc_bmap)[(svc_id)/(sizeof(u32))]) & \
BIT((svc_id)%(sizeof(u32))))
#define SVCMAP(x, y) \
do { \
if (WMI_SERVICE_IS_ENABLED((in), (x))) \
__set_bit(y, out); \
} while (0)
static inline void wmi_10x_svc_map(const __le32 *in, unsigned long *out)
{
SVCMAP(WMI_10X_SERVICE_BEACON_OFFLOAD,
WMI_SERVICE_BEACON_OFFLOAD);
SVCMAP(WMI_10X_SERVICE_SCAN_OFFLOAD,
WMI_SERVICE_SCAN_OFFLOAD);
SVCMAP(WMI_10X_SERVICE_ROAM_OFFLOAD,
WMI_SERVICE_ROAM_OFFLOAD);
SVCMAP(WMI_10X_SERVICE_BCN_MISS_OFFLOAD,
WMI_SERVICE_BCN_MISS_OFFLOAD);
SVCMAP(WMI_10X_SERVICE_STA_PWRSAVE,
WMI_SERVICE_STA_PWRSAVE);
SVCMAP(WMI_10X_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_SERVICE_STA_ADVANCED_PWRSAVE);
SVCMAP(WMI_10X_SERVICE_AP_UAPSD,
WMI_SERVICE_AP_UAPSD);
SVCMAP(WMI_10X_SERVICE_AP_DFS,
WMI_SERVICE_AP_DFS);
SVCMAP(WMI_10X_SERVICE_11AC,
WMI_SERVICE_11AC);
SVCMAP(WMI_10X_SERVICE_BLOCKACK,
WMI_SERVICE_BLOCKACK);
SVCMAP(WMI_10X_SERVICE_PHYERR,
WMI_SERVICE_PHYERR);
SVCMAP(WMI_10X_SERVICE_BCN_FILTER,
WMI_SERVICE_BCN_FILTER);
SVCMAP(WMI_10X_SERVICE_RTT,
WMI_SERVICE_RTT);
SVCMAP(WMI_10X_SERVICE_RATECTRL,
WMI_SERVICE_RATECTRL);
SVCMAP(WMI_10X_SERVICE_WOW,
WMI_SERVICE_WOW);
SVCMAP(WMI_10X_SERVICE_RATECTRL_CACHE,
WMI_SERVICE_RATECTRL_CACHE);
SVCMAP(WMI_10X_SERVICE_IRAM_TIDS,
WMI_SERVICE_IRAM_TIDS);
SVCMAP(WMI_10X_SERVICE_BURST,
WMI_SERVICE_BURST);
SVCMAP(WMI_10X_SERVICE_SMART_ANTENNA_SW_SUPPORT,
WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT);
SVCMAP(WMI_10X_SERVICE_FORCE_FW_HANG,
WMI_SERVICE_FORCE_FW_HANG);
SVCMAP(WMI_10X_SERVICE_SMART_ANTENNA_HW_SUPPORT,
WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT);
}
static inline void wmi_main_svc_map(const __le32 *in, unsigned long *out)
{
SVCMAP(WMI_MAIN_SERVICE_BEACON_OFFLOAD,
WMI_SERVICE_BEACON_OFFLOAD);
SVCMAP(WMI_MAIN_SERVICE_SCAN_OFFLOAD,
WMI_SERVICE_SCAN_OFFLOAD);
SVCMAP(WMI_MAIN_SERVICE_ROAM_OFFLOAD,
WMI_SERVICE_ROAM_OFFLOAD);
SVCMAP(WMI_MAIN_SERVICE_BCN_MISS_OFFLOAD,
WMI_SERVICE_BCN_MISS_OFFLOAD);
SVCMAP(WMI_MAIN_SERVICE_STA_PWRSAVE,
WMI_SERVICE_STA_PWRSAVE);
SVCMAP(WMI_MAIN_SERVICE_STA_ADVANCED_PWRSAVE,
WMI_SERVICE_STA_ADVANCED_PWRSAVE);
SVCMAP(WMI_MAIN_SERVICE_AP_UAPSD,
WMI_SERVICE_AP_UAPSD);
SVCMAP(WMI_MAIN_SERVICE_AP_DFS,
WMI_SERVICE_AP_DFS);
SVCMAP(WMI_MAIN_SERVICE_11AC,
WMI_SERVICE_11AC);
SVCMAP(WMI_MAIN_SERVICE_BLOCKACK,
WMI_SERVICE_BLOCKACK);
SVCMAP(WMI_MAIN_SERVICE_PHYERR,
WMI_SERVICE_PHYERR);
SVCMAP(WMI_MAIN_SERVICE_BCN_FILTER,
WMI_SERVICE_BCN_FILTER);
SVCMAP(WMI_MAIN_SERVICE_RTT,
WMI_SERVICE_RTT);
SVCMAP(WMI_MAIN_SERVICE_RATECTRL,
WMI_SERVICE_RATECTRL);
SVCMAP(WMI_MAIN_SERVICE_WOW,
WMI_SERVICE_WOW);
SVCMAP(WMI_MAIN_SERVICE_RATECTRL_CACHE,
WMI_SERVICE_RATECTRL_CACHE);
SVCMAP(WMI_MAIN_SERVICE_IRAM_TIDS,
WMI_SERVICE_IRAM_TIDS);
SVCMAP(WMI_MAIN_SERVICE_ARPNS_OFFLOAD,
WMI_SERVICE_ARPNS_OFFLOAD);
SVCMAP(WMI_MAIN_SERVICE_NLO,
WMI_SERVICE_NLO);
SVCMAP(WMI_MAIN_SERVICE_GTK_OFFLOAD,
WMI_SERVICE_GTK_OFFLOAD);
SVCMAP(WMI_MAIN_SERVICE_SCAN_SCH,
WMI_SERVICE_SCAN_SCH);
SVCMAP(WMI_MAIN_SERVICE_CSA_OFFLOAD,
WMI_SERVICE_CSA_OFFLOAD);
SVCMAP(WMI_MAIN_SERVICE_CHATTER,
WMI_SERVICE_CHATTER);
SVCMAP(WMI_MAIN_SERVICE_COEX_FREQAVOID,
WMI_SERVICE_COEX_FREQAVOID);
SVCMAP(WMI_MAIN_SERVICE_PACKET_POWER_SAVE,
WMI_SERVICE_PACKET_POWER_SAVE);
SVCMAP(WMI_MAIN_SERVICE_FORCE_FW_HANG,
WMI_SERVICE_FORCE_FW_HANG);
SVCMAP(WMI_MAIN_SERVICE_GPIO,
WMI_SERVICE_GPIO);
SVCMAP(WMI_MAIN_SERVICE_STA_DTIM_PS_MODULATED_DTIM,
WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM);
SVCMAP(WMI_MAIN_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG,
WMI_SERVICE_STA_UAPSD_BASIC_AUTO_TRIG);
SVCMAP(WMI_MAIN_SERVICE_STA_UAPSD_VAR_AUTO_TRIG,
WMI_SERVICE_STA_UAPSD_VAR_AUTO_TRIG);
SVCMAP(WMI_MAIN_SERVICE_STA_KEEP_ALIVE,
WMI_SERVICE_STA_KEEP_ALIVE);
SVCMAP(WMI_MAIN_SERVICE_TX_ENCAP,
WMI_SERVICE_TX_ENCAP);
}
#undef SVCMAP
#define WMI_SERVICE_BM_SIZE \
((WMI_MAX_SERVICE + sizeof(u32) - 1)/sizeof(u32))
@ -803,6 +966,159 @@ enum wmi_10x_event_id {
WMI_10X_PDEV_UTF_EVENTID = WMI_10X_END_EVENTID-1,
};
enum wmi_10_2_cmd_id {
WMI_10_2_START_CMDID = 0x9000,
WMI_10_2_END_CMDID = 0x9FFF,
WMI_10_2_INIT_CMDID,
WMI_10_2_START_SCAN_CMDID = WMI_10_2_START_CMDID,
WMI_10_2_STOP_SCAN_CMDID,
WMI_10_2_SCAN_CHAN_LIST_CMDID,
WMI_10_2_ECHO_CMDID,
WMI_10_2_PDEV_SET_REGDOMAIN_CMDID,
WMI_10_2_PDEV_SET_CHANNEL_CMDID,
WMI_10_2_PDEV_SET_PARAM_CMDID,
WMI_10_2_PDEV_PKTLOG_ENABLE_CMDID,
WMI_10_2_PDEV_PKTLOG_DISABLE_CMDID,
WMI_10_2_PDEV_SET_WMM_PARAMS_CMDID,
WMI_10_2_PDEV_SET_HT_CAP_IE_CMDID,
WMI_10_2_PDEV_SET_VHT_CAP_IE_CMDID,
WMI_10_2_PDEV_SET_BASE_MACADDR_CMDID,
WMI_10_2_PDEV_SET_QUIET_MODE_CMDID,
WMI_10_2_PDEV_GREEN_AP_PS_ENABLE_CMDID,
WMI_10_2_PDEV_GET_TPC_CONFIG_CMDID,
WMI_10_2_VDEV_CREATE_CMDID,
WMI_10_2_VDEV_DELETE_CMDID,
WMI_10_2_VDEV_START_REQUEST_CMDID,
WMI_10_2_VDEV_RESTART_REQUEST_CMDID,
WMI_10_2_VDEV_UP_CMDID,
WMI_10_2_VDEV_STOP_CMDID,
WMI_10_2_VDEV_DOWN_CMDID,
WMI_10_2_VDEV_STANDBY_RESPONSE_CMDID,
WMI_10_2_VDEV_RESUME_RESPONSE_CMDID,
WMI_10_2_VDEV_SET_PARAM_CMDID,
WMI_10_2_VDEV_INSTALL_KEY_CMDID,
WMI_10_2_VDEV_SET_DSCP_TID_MAP_CMDID,
WMI_10_2_PEER_CREATE_CMDID,
WMI_10_2_PEER_DELETE_CMDID,
WMI_10_2_PEER_FLUSH_TIDS_CMDID,
WMI_10_2_PEER_SET_PARAM_CMDID,
WMI_10_2_PEER_ASSOC_CMDID,
WMI_10_2_PEER_ADD_WDS_ENTRY_CMDID,
WMI_10_2_PEER_UPDATE_WDS_ENTRY_CMDID,
WMI_10_2_PEER_REMOVE_WDS_ENTRY_CMDID,
WMI_10_2_PEER_MCAST_GROUP_CMDID,
WMI_10_2_BCN_TX_CMDID,
WMI_10_2_BCN_PRB_TMPL_CMDID,
WMI_10_2_BCN_FILTER_RX_CMDID,
WMI_10_2_PRB_REQ_FILTER_RX_CMDID,
WMI_10_2_MGMT_TX_CMDID,
WMI_10_2_ADDBA_CLEAR_RESP_CMDID,
WMI_10_2_ADDBA_SEND_CMDID,
WMI_10_2_ADDBA_STATUS_CMDID,
WMI_10_2_DELBA_SEND_CMDID,
WMI_10_2_ADDBA_SET_RESP_CMDID,
WMI_10_2_SEND_SINGLEAMSDU_CMDID,
WMI_10_2_STA_POWERSAVE_MODE_CMDID,
WMI_10_2_STA_POWERSAVE_PARAM_CMDID,
WMI_10_2_STA_MIMO_PS_MODE_CMDID,
WMI_10_2_DBGLOG_CFG_CMDID,
WMI_10_2_PDEV_DFS_ENABLE_CMDID,
WMI_10_2_PDEV_DFS_DISABLE_CMDID,
WMI_10_2_PDEV_QVIT_CMDID,
WMI_10_2_ROAM_SCAN_MODE,
WMI_10_2_ROAM_SCAN_RSSI_THRESHOLD,
WMI_10_2_ROAM_SCAN_PERIOD,
WMI_10_2_ROAM_SCAN_RSSI_CHANGE_THRESHOLD,
WMI_10_2_ROAM_AP_PROFILE,
WMI_10_2_OFL_SCAN_ADD_AP_PROFILE,
WMI_10_2_OFL_SCAN_REMOVE_AP_PROFILE,
WMI_10_2_OFL_SCAN_PERIOD,
WMI_10_2_P2P_DEV_SET_DEVICE_INFO,
WMI_10_2_P2P_DEV_SET_DISCOVERABILITY,
WMI_10_2_P2P_GO_SET_BEACON_IE,
WMI_10_2_P2P_GO_SET_PROBE_RESP_IE,
WMI_10_2_AP_PS_PEER_PARAM_CMDID,
WMI_10_2_AP_PS_PEER_UAPSD_COEX_CMDID,
WMI_10_2_PEER_RATE_RETRY_SCHED_CMDID,
WMI_10_2_WLAN_PROFILE_TRIGGER_CMDID,
WMI_10_2_WLAN_PROFILE_SET_HIST_INTVL_CMDID,
WMI_10_2_WLAN_PROFILE_GET_PROFILE_DATA_CMDID,
WMI_10_2_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID,
WMI_10_2_WLAN_PROFILE_LIST_PROFILE_ID_CMDID,
WMI_10_2_PDEV_SUSPEND_CMDID,
WMI_10_2_PDEV_RESUME_CMDID,
WMI_10_2_ADD_BCN_FILTER_CMDID,
WMI_10_2_RMV_BCN_FILTER_CMDID,
WMI_10_2_WOW_ADD_WAKE_PATTERN_CMDID,
WMI_10_2_WOW_DEL_WAKE_PATTERN_CMDID,
WMI_10_2_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID,
WMI_10_2_WOW_ENABLE_CMDID,
WMI_10_2_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID,
WMI_10_2_RTT_MEASREQ_CMDID,
WMI_10_2_RTT_TSF_CMDID,
WMI_10_2_RTT_KEEPALIVE_CMDID,
WMI_10_2_PDEV_SEND_BCN_CMDID,
WMI_10_2_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID,
WMI_10_2_VDEV_SPECTRAL_SCAN_ENABLE_CMDID,
WMI_10_2_REQUEST_STATS_CMDID,
WMI_10_2_GPIO_CONFIG_CMDID,
WMI_10_2_GPIO_OUTPUT_CMDID,
WMI_10_2_VDEV_RATEMASK_CMDID,
WMI_10_2_PDEV_SMART_ANT_ENABLE_CMDID,
WMI_10_2_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID,
WMI_10_2_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID,
WMI_10_2_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID,
WMI_10_2_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID,
WMI_10_2_FORCE_FW_HANG_CMDID,
WMI_10_2_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID,
WMI_10_2_PDEV_SET_CTL_TABLE_CMDID,
WMI_10_2_PDEV_SET_MIMOGAIN_TABLE_CMDID,
WMI_10_2_PDEV_RATEPWR_TABLE_CMDID,
WMI_10_2_PDEV_RATEPWR_CHAINMSK_TABLE_CMDID,
WMI_10_2_PDEV_UTF_CMDID = WMI_10_2_END_CMDID - 1,
};
enum wmi_10_2_event_id {
WMI_10_2_SERVICE_READY_EVENTID = 0x8000,
WMI_10_2_READY_EVENTID,
WMI_10_2_DEBUG_MESG_EVENTID,
WMI_10_2_START_EVENTID = 0x9000,
WMI_10_2_END_EVENTID = 0x9FFF,
WMI_10_2_SCAN_EVENTID = WMI_10_2_START_EVENTID,
WMI_10_2_ECHO_EVENTID,
WMI_10_2_UPDATE_STATS_EVENTID,
WMI_10_2_INST_RSSI_STATS_EVENTID,
WMI_10_2_VDEV_START_RESP_EVENTID,
WMI_10_2_VDEV_STANDBY_REQ_EVENTID,
WMI_10_2_VDEV_RESUME_REQ_EVENTID,
WMI_10_2_VDEV_STOPPED_EVENTID,
WMI_10_2_PEER_STA_KICKOUT_EVENTID,
WMI_10_2_HOST_SWBA_EVENTID,
WMI_10_2_TBTTOFFSET_UPDATE_EVENTID,
WMI_10_2_MGMT_RX_EVENTID,
WMI_10_2_CHAN_INFO_EVENTID,
WMI_10_2_PHYERR_EVENTID,
WMI_10_2_ROAM_EVENTID,
WMI_10_2_PROFILE_MATCH,
WMI_10_2_DEBUG_PRINT_EVENTID,
WMI_10_2_PDEV_QVIT_EVENTID,
WMI_10_2_WLAN_PROFILE_DATA_EVENTID,
WMI_10_2_RTT_MEASUREMENT_REPORT_EVENTID,
WMI_10_2_TSF_MEASUREMENT_REPORT_EVENTID,
WMI_10_2_RTT_ERROR_REPORT_EVENTID,
WMI_10_2_RTT_KEEPALIVE_EVENTID,
WMI_10_2_WOW_WAKEUP_HOST_EVENTID,
WMI_10_2_DCS_INTERFERENCE_EVENTID,
WMI_10_2_PDEV_TPC_CONFIG_EVENTID,
WMI_10_2_GPIO_INPUT_EVENTID,
WMI_10_2_PEER_RATECODE_LIST_EVENTID,
WMI_10_2_GENERIC_BUFFER_EVENTID,
WMI_10_2_MCAST_BUF_RELEASE_EVENTID,
WMI_10_2_MCAST_LIST_AGEOUT_EVENTID,
WMI_10_2_WDS_PEER_EVENTID,
WMI_10_2_PDEV_UTF_EVENTID = WMI_10_2_END_EVENTID - 1,
};
enum wmi_phy_mode {
MODE_11A = 0, /* 11a Mode */
MODE_11G = 1, /* 11b/g Mode */
@ -1076,10 +1392,6 @@ struct wlan_host_mem_req {
__le32 num_units;
} __packed;
#define WMI_SERVICE_IS_ENABLED(wmi_svc_bmap, svc_id) \
((((wmi_svc_bmap)[(svc_id)/(sizeof(u32))]) & \
(1 << ((svc_id)%(sizeof(u32))))) != 0)
/*
* The following struct holds optional payload for
* wmi_service_ready_event,e.g., 11ac pass some of the
@ -1551,6 +1863,16 @@ struct wmi_resource_config_10x {
__le32 max_frag_entries;
} __packed;
struct wmi_resource_config_10_2 {
struct wmi_resource_config_10x common;
__le32 max_peer_ext_stats;
__le32 smart_ant_cap; /* 0-disable, 1-enable */
__le32 bk_min_free;
__le32 be_min_free;
__le32 vi_min_free;
__le32 vo_min_free;
__le32 rx_batchmode; /* 0-disable, 1-enable */
} __packed;
#define NUM_UNITS_IS_NUM_VDEVS 0x1
#define NUM_UNITS_IS_NUM_PEERS 0x2
@ -1588,11 +1910,28 @@ struct wmi_init_cmd_10x {
struct host_memory_chunk host_mem_chunks[1];
} __packed;
struct wmi_init_cmd_10_2 {
struct wmi_resource_config_10_2 resource_config;
__le32 num_host_mem_chunks;
/*
* variable number of host memory chunks.
* This should be the last element in the structure
*/
struct host_memory_chunk host_mem_chunks[1];
} __packed;
struct wmi_chan_list_entry {
__le16 freq;
u8 phy_mode; /* valid for 10.2 only */
u8 reserved;
} __packed;
/* TLV for channel list */
struct wmi_chan_list {
__le32 tag; /* WMI_CHAN_LIST_TAG */
__le32 num_chan;
__le32 channel_list[0];
struct wmi_chan_list_entry channel_list[0];
} __packed;
struct wmi_bssid_list {
@ -1821,7 +2160,7 @@ struct wmi_start_scan_arg {
u32 n_bssids;
u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN];
u32 channels[64];
u16 channels[64];
struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID];
struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID];
};
@ -2067,6 +2406,7 @@ struct wmi_comb_phyerr_rx_event {
#define PHYERR_TLV_SIG 0xBB
#define PHYERR_TLV_TAG_SEARCH_FFT_REPORT 0xFB
#define PHYERR_TLV_TAG_RADAR_PULSE_SUMMARY 0xF8
#define PHYERR_TLV_TAG_SPECTRAL_SUMMARY_REPORT 0xF9
struct phyerr_radar_report {
__le32 reg0; /* RADAR_REPORT_REG0_* */
@ -2515,6 +2855,19 @@ enum wmi_10x_pdev_param {
WMI_10X_PDEV_PARAM_BURST_DUR,
/* Set Bursting Enable*/
WMI_10X_PDEV_PARAM_BURST_ENABLE,
/* following are available as of firmware 10.2 */
WMI_10X_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA,
WMI_10X_PDEV_PARAM_IGMPMLD_OVERRIDE,
WMI_10X_PDEV_PARAM_IGMPMLD_TID,
WMI_10X_PDEV_PARAM_ANTENNA_GAIN,
WMI_10X_PDEV_PARAM_RX_DECAP_MODE,
WMI_10X_PDEV_PARAM_RX_FILTER,
WMI_10X_PDEV_PARAM_SET_MCAST_TO_UCAST_TID,
WMI_10X_PDEV_PARAM_PROXY_STA_MODE,
WMI_10X_PDEV_PARAM_SET_MCAST2UCAST_MODE,
WMI_10X_PDEV_PARAM_SET_MCAST2UCAST_BUFFER,
WMI_10X_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER,
};
struct wmi_pdev_set_param_cmd {
@ -3387,6 +3740,14 @@ enum wmi_10x_vdev_param {
WMI_10X_VDEV_PARAM_ENABLE_RTSCTS,
WMI_10X_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS,
/* following are available as of firmware 10.2 */
WMI_10X_VDEV_PARAM_TX_ENCAP_TYPE,
WMI_10X_VDEV_PARAM_CABQ_MAXDUR,
WMI_10X_VDEV_PARAM_MFPTEST_SET,
WMI_10X_VDEV_PARAM_RTS_FIXED_RATE,
WMI_10X_VDEV_PARAM_VHT_SGIMASK,
WMI_10X_VDEV_PARAM_VHT80_RATEMASK,
};
/* slot time long */
@ -3444,6 +3805,98 @@ struct wmi_vdev_simple_event {
/* unsupported VDEV combination */
#define WMI_INIFIED_VDEV_START_RESPONSE_NOT_SUPPORTED 0x2
/* TODO: please add more comments if you have in-depth information */
struct wmi_vdev_spectral_conf_cmd {
__le32 vdev_id;
/* number of fft samples to send (0 for infinite) */
__le32 scan_count;
__le32 scan_period;
__le32 scan_priority;
/* number of bins in the FFT: 2^(fft_size - bin_scale) */
__le32 scan_fft_size;
__le32 scan_gc_ena;
__le32 scan_restart_ena;
__le32 scan_noise_floor_ref;
__le32 scan_init_delay;
__le32 scan_nb_tone_thr;
__le32 scan_str_bin_thr;
__le32 scan_wb_rpt_mode;
__le32 scan_rssi_rpt_mode;
__le32 scan_rssi_thr;
__le32 scan_pwr_format;
/* rpt_mode: Format of FFT report to software for spectral scan
* triggered FFTs:
* 0: No FFT report (only spectral scan summary report)
* 1: 2-dword summary of metrics for each completed FFT + spectral
* scan summary report
* 2: 2-dword summary of metrics for each completed FFT +
* 1x- oversampled bins(in-band) per FFT + spectral scan summary
* report
* 3: 2-dword summary of metrics for each completed FFT +
* 2x- oversampled bins (all) per FFT + spectral scan summary
*/
__le32 scan_rpt_mode;
__le32 scan_bin_scale;
__le32 scan_dbm_adj;
__le32 scan_chn_mask;
} __packed;
struct wmi_vdev_spectral_conf_arg {
u32 vdev_id;
u32 scan_count;
u32 scan_period;
u32 scan_priority;
u32 scan_fft_size;
u32 scan_gc_ena;
u32 scan_restart_ena;
u32 scan_noise_floor_ref;
u32 scan_init_delay;
u32 scan_nb_tone_thr;
u32 scan_str_bin_thr;
u32 scan_wb_rpt_mode;
u32 scan_rssi_rpt_mode;
u32 scan_rssi_thr;
u32 scan_pwr_format;
u32 scan_rpt_mode;
u32 scan_bin_scale;
u32 scan_dbm_adj;
u32 scan_chn_mask;
};
#define WMI_SPECTRAL_ENABLE_DEFAULT 0
#define WMI_SPECTRAL_COUNT_DEFAULT 0
#define WMI_SPECTRAL_PERIOD_DEFAULT 35
#define WMI_SPECTRAL_PRIORITY_DEFAULT 1
#define WMI_SPECTRAL_FFT_SIZE_DEFAULT 7
#define WMI_SPECTRAL_GC_ENA_DEFAULT 1
#define WMI_SPECTRAL_RESTART_ENA_DEFAULT 0
#define WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96
#define WMI_SPECTRAL_INIT_DELAY_DEFAULT 80
#define WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12
#define WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8
#define WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0
#define WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0
#define WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0
#define WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0
#define WMI_SPECTRAL_RPT_MODE_DEFAULT 2
#define WMI_SPECTRAL_BIN_SCALE_DEFAULT 1
#define WMI_SPECTRAL_DBM_ADJ_DEFAULT 1
#define WMI_SPECTRAL_CHN_MASK_DEFAULT 1
struct wmi_vdev_spectral_enable_cmd {
__le32 vdev_id;
__le32 trigger_cmd;
__le32 enable_cmd;
} __packed;
#define WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1
#define WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2
#define WMI_SPECTRAL_ENABLE_CMD_ENABLE 1
#define WMI_SPECTRAL_ENABLE_CMD_DISABLE 2
/* Beacon processing related command and event structures */
struct wmi_bcn_tx_hdr {
__le32 vdev_id;
@ -3470,6 +3923,11 @@ enum wmi_bcn_tx_ref_flags {
WMI_BCN_TX_REF_FLAG_DELIVER_CAB = 0x2,
};
/* TODO: It is unclear why "no antenna" works while any other seemingly valid
* chainmask yields no beacons on the air at all.
*/
#define WMI_BCN_TX_REF_DEF_ANTENNA 0
struct wmi_bcn_tx_ref_cmd {
__le32 vdev_id;
__le32 data_len;
@ -3481,6 +3939,8 @@ struct wmi_bcn_tx_ref_cmd {
__le32 frame_control;
/* to control CABQ traffic: WMI_BCN_TX_REF_FLAG_ */
__le32 flags;
/* introduced in 10.2 */
__le32 antenna_mask;
} __packed;
/* Beacon filter */
@ -4053,7 +4513,7 @@ struct wmi_peer_set_q_empty_callback_cmd {
/* Maximum listen interval supported by hw in units of beacon interval */
#define ATH10K_MAX_HW_LISTEN_INTERVAL 5
struct wmi_peer_assoc_complete_cmd {
struct wmi_common_peer_assoc_complete_cmd {
struct wmi_mac_addr peer_macaddr;
__le32 vdev_id;
__le32 peer_new_assoc; /* 1=assoc, 0=reassoc */
@ -4071,11 +4531,30 @@ struct wmi_peer_assoc_complete_cmd {
__le32 peer_vht_caps;
__le32 peer_phymode;
struct wmi_vht_rate_set peer_vht_rates;
};
struct wmi_main_peer_assoc_complete_cmd {
struct wmi_common_peer_assoc_complete_cmd cmd;
/* HT Operation Element of the peer. Five bytes packed in 2
* INT32 array and filled from lsb to msb. */
__le32 peer_ht_info[2];
} __packed;
struct wmi_10_1_peer_assoc_complete_cmd {
struct wmi_common_peer_assoc_complete_cmd cmd;
} __packed;
#define WMI_PEER_ASSOC_INFO0_MAX_MCS_IDX_LSB 0
#define WMI_PEER_ASSOC_INFO0_MAX_MCS_IDX_MASK 0x0f
#define WMI_PEER_ASSOC_INFO0_MAX_NSS_LSB 4
#define WMI_PEER_ASSOC_INFO0_MAX_NSS_MASK 0xf0
struct wmi_10_2_peer_assoc_complete_cmd {
struct wmi_common_peer_assoc_complete_cmd cmd;
__le32 info0; /* WMI_PEER_ASSOC_INFO0_ */
} __packed;
struct wmi_peer_assoc_complete_arg {
u8 addr[ETH_ALEN];
u32 vdev_id;
@ -4290,6 +4769,10 @@ int ath10k_wmi_vdev_set_param(struct ath10k *ar, u32 vdev_id,
u32 param_id, u32 param_value);
int ath10k_wmi_vdev_install_key(struct ath10k *ar,
const struct wmi_vdev_install_key_arg *arg);
int ath10k_wmi_vdev_spectral_conf(struct ath10k *ar,
const struct wmi_vdev_spectral_conf_arg *arg);
int ath10k_wmi_vdev_spectral_enable(struct ath10k *ar, u32 vdev_id, u32 trigger,
u32 enable);
int ath10k_wmi_peer_create(struct ath10k *ar, u32 vdev_id,
const u8 peer_addr[ETH_ALEN]);
int ath10k_wmi_peer_delete(struct ath10k *ar, u32 vdev_id,

View File

@ -351,8 +351,7 @@ void ath5k_hw_deinit(struct ath5k_hw *ah)
{
__set_bit(ATH_STAT_INVALID, ah->status);
if (ah->ah_rf_banks != NULL)
kfree(ah->ah_rf_banks);
kfree(ah->ah_rf_banks);
ath5k_eeprom_detach(ah);

View File

@ -1423,7 +1423,7 @@ ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
break;
}
if (rxs->rate_idx >= 0 && rs->rs_rate ==
if (rs->rs_rate ==
ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
rxs->flag |= RX_FLAG_SHORTPRE;

View File

@ -894,6 +894,100 @@ static const struct file_operations fops_queue = {
.llseek = default_llseek,
};
/* debugfs: eeprom */
struct eeprom_private {
u16 *buf;
int len;
};
static int open_file_eeprom(struct inode *inode, struct file *file)
{
struct eeprom_private *ep;
struct ath5k_hw *ah = inode->i_private;
bool res;
int i, ret;
u32 eesize;
u16 val, *buf;
/* Get eeprom size */
res = ath5k_hw_nvram_read(ah, AR5K_EEPROM_SIZE_UPPER, &val);
if (!res)
return -EACCES;
if (val == 0) {
eesize = AR5K_EEPROM_INFO_MAX + AR5K_EEPROM_INFO_BASE;
} else {
eesize = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
ath5k_hw_nvram_read(ah, AR5K_EEPROM_SIZE_LOWER, &val);
eesize = eesize | val;
}
if (eesize > 4096)
return -EINVAL;
/* Create buffer and read in eeprom */
buf = vmalloc(eesize);
if (!buf) {
ret = -ENOMEM;
goto err;
}
for (i = 0; i < eesize; ++i) {
AR5K_EEPROM_READ(i, val);
buf[i] = val;
}
/* Create private struct and assign to file */
ep = kmalloc(sizeof(*ep), GFP_KERNEL);
if (!ep) {
ret = -ENOMEM;
goto freebuf;
}
ep->buf = buf;
ep->len = i;
file->private_data = (void *)ep;
return 0;
freebuf:
vfree(buf);
err:
return ret;
}
static ssize_t read_file_eeprom(struct file *file, char __user *user_buf,
size_t count, loff_t *ppos)
{
struct eeprom_private *ep = file->private_data;
return simple_read_from_buffer(user_buf, count, ppos, ep->buf, ep->len);
}
static int release_file_eeprom(struct inode *inode, struct file *file)
{
struct eeprom_private *ep = file->private_data;
vfree(ep->buf);
kfree(ep);
return 0;
}
static const struct file_operations fops_eeprom = {
.open = open_file_eeprom,
.read = read_file_eeprom,
.release = release_file_eeprom,
.owner = THIS_MODULE,
};
void
ath5k_debug_init_device(struct ath5k_hw *ah)
@ -921,6 +1015,8 @@ ath5k_debug_init_device(struct ath5k_hw *ah)
debugfs_create_file("misc", S_IRUSR, phydir, ah, &fops_misc);
debugfs_create_file("eeprom", S_IRUSR, phydir, ah, &fops_eeprom);
debugfs_create_file("frameerrors", S_IWUSR | S_IRUSR, phydir, ah,
&fops_frameerrors);

View File

@ -130,6 +130,7 @@ ath5k_register_led(struct ath5k_hw *ah, struct ath5k_led *led,
led->ah = ah;
strncpy(led->name, name, sizeof(led->name));
led->name[sizeof(led->name)-1] = 0;
led->led_dev.name = led->name;
led->led_dev.default_trigger = trigger;
led->led_dev.brightness_set = ath5k_led_brightness_set;

View File

@ -717,6 +717,7 @@ ath6kl_add_bss_if_needed(struct ath6kl_vif *vif,
memcpy(ie + 2, vif->ssid, vif->ssid_len);
memcpy(ie + 2 + vif->ssid_len, beacon_ie, beacon_ie_len);
bss = cfg80211_inform_bss(ar->wiphy, chan,
CFG80211_BSS_FTYPE_UNKNOWN,
bssid, 0, cap_val, 100,
ie, 2 + vif->ssid_len + beacon_ie_len,
0, GFP_KERNEL);

View File

@ -1049,7 +1049,7 @@ static int ath6kl_fetch_fw_apin(struct ath6kl *ar, const char *name)
ar->hw.reserved_ram_size = le32_to_cpup(val);
ath6kl_dbg(ATH6KL_DBG_BOOT,
"found reserved ram size ie 0x%d\n",
"found reserved ram size ie %d\n",
ar->hw.reserved_ram_size);
break;
case ATH6KL_FW_IE_CAPABILITIES:

View File

@ -225,7 +225,7 @@ int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value)
ret = ath6kl_hif_diag_write32(ar, address, value);
if (ret) {
ath6kl_err("failed to write 0x%x during diagnose window to 0x%d\n",
ath6kl_err("failed to write 0x%x during diagnose window to 0x%x\n",
address, value);
return ret;
}

View File

@ -1400,6 +1400,7 @@ static const struct sdio_device_id ath6kl_sdio_devices[] = {
{SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1))},
{SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x0))},
{SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))},
{SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x2))},
{},
};

View File

@ -1229,26 +1229,7 @@ static struct usb_driver ath6kl_usb_driver = {
.disable_hub_initiated_lpm = 1,
};
static int ath6kl_usb_init(void)
{
int ret;
ret = usb_register(&ath6kl_usb_driver);
if (ret) {
ath6kl_err("usb registration failed: %d\n", ret);
return ret;
}
return 0;
}
static void ath6kl_usb_exit(void)
{
usb_deregister(&ath6kl_usb_driver);
}
module_init(ath6kl_usb_init);
module_exit(ath6kl_usb_exit);
module_usb_driver(ath6kl_usb_driver);
MODULE_AUTHOR("Atheros Communications, Inc.");
MODULE_DESCRIPTION("Driver support for Atheros AR600x USB devices");

View File

@ -619,8 +619,7 @@ static int ath6kl_wmi_rx_probe_req_event_rx(struct wmi *wmi, u8 *datap, int len,
dlen, freq, vif->probe_req_report);
if (vif->probe_req_report || vif->nw_type == AP_NETWORK)
cfg80211_rx_mgmt(&vif->wdev, freq, 0, ev->data, dlen, 0,
GFP_ATOMIC);
cfg80211_rx_mgmt(&vif->wdev, freq, 0, ev->data, dlen, 0);
return 0;
}
@ -659,7 +658,7 @@ static int ath6kl_wmi_rx_action_event_rx(struct wmi *wmi, u8 *datap, int len,
return -EINVAL;
}
ath6kl_dbg(ATH6KL_DBG_WMI, "rx_action: len=%u freq=%u\n", dlen, freq);
cfg80211_rx_mgmt(&vif->wdev, freq, 0, ev->data, dlen, 0, GFP_ATOMIC);
cfg80211_rx_mgmt(&vif->wdev, freq, 0, ev->data, dlen, 0);
return 0;
}
@ -1093,7 +1092,6 @@ static int ath6kl_wmi_bssinfo_event_rx(struct wmi *wmi, u8 *datap, int len,
u8 *buf;
struct ieee80211_channel *channel;
struct ath6kl *ar = wmi->parent_dev;
struct ieee80211_mgmt *mgmt;
struct cfg80211_bss *bss;
if (len <= sizeof(struct wmi_bss_info_hdr2))
@ -1139,39 +1137,15 @@ static int ath6kl_wmi_bssinfo_event_rx(struct wmi *wmi, u8 *datap, int len,
}
}
/*
* In theory, use of cfg80211_inform_bss() would be more natural here
* since we do not have the full frame. However, at least for now,
* cfg80211 can only distinguish Beacon and Probe Response frames from
* each other when using cfg80211_inform_bss_frame(), so let's build a
* fake IEEE 802.11 header to be able to take benefit of this.
*/
mgmt = kmalloc(24 + len, GFP_ATOMIC);
if (mgmt == NULL)
return -EINVAL;
if (bih->frame_type == BEACON_FTYPE) {
mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
IEEE80211_STYPE_BEACON);
memset(mgmt->da, 0xff, ETH_ALEN);
} else {
struct net_device *dev = vif->ndev;
mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
IEEE80211_STYPE_PROBE_RESP);
memcpy(mgmt->da, dev->dev_addr, ETH_ALEN);
}
mgmt->duration = cpu_to_le16(0);
memcpy(mgmt->sa, bih->bssid, ETH_ALEN);
memcpy(mgmt->bssid, bih->bssid, ETH_ALEN);
mgmt->seq_ctrl = cpu_to_le16(0);
memcpy(&mgmt->u.beacon, buf, len);
bss = cfg80211_inform_bss_frame(ar->wiphy, channel, mgmt,
24 + len, (bih->snr - 95) * 100,
GFP_ATOMIC);
kfree(mgmt);
bss = cfg80211_inform_bss(ar->wiphy, channel,
bih->frame_type == BEACON_FTYPE ?
CFG80211_BSS_FTYPE_BEACON :
CFG80211_BSS_FTYPE_PRESP,
bih->bssid, get_unaligned_le64((__le64 *)buf),
get_unaligned_le16(((__le16 *)buf) + 5),
get_unaligned_le16(((__le16 *)buf) + 4),
buf + 8 + 2 + 2, len - 8 - 2 - 2,
(bih->snr - 95) * 100, GFP_ATOMIC);
if (bss == NULL)
return -ENOMEM;
cfg80211_put_bss(ar->wiphy, bss);

View File

@ -130,6 +130,15 @@ config ATH9K_RFKILL
seconds. Turn off to save power, but enable it if you have
a platform that can toggle the RF-Kill GPIO.
config ATH9K_CHANNEL_CONTEXT
bool "Channel Context support"
depends on ATH9K
default n
---help---
This option enables channel context support in ath9k, which is needed
for multi-channel concurrency. Enable this if P2P PowerSave support
is required.
config ATH9K_HTC
tristate "Atheros HTC based wireless cards support"
depends on USB && MAC80211

View File

@ -31,6 +31,7 @@
#include "spectral.h"
struct ath_node;
struct ath_vif;
extern struct ieee80211_ops ath9k_ops;
extern int ath9k_modparam_nohwcrypt;
@ -324,6 +325,10 @@ struct ath_rx {
u32 ampdu_ref;
};
/*******************/
/* Channel Context */
/*******************/
struct ath_chanctx {
struct cfg80211_chan_def chandef;
struct list_head vifs;
@ -354,7 +359,9 @@ enum ath_chanctx_event {
ATH_CHANCTX_EVENT_BEACON_RECEIVED,
ATH_CHANCTX_EVENT_ASSOC,
ATH_CHANCTX_EVENT_SWITCH,
ATH_CHANCTX_EVENT_ASSIGN,
ATH_CHANCTX_EVENT_UNASSIGN,
ATH_CHANCTX_EVENT_CHANGE,
ATH_CHANCTX_EVENT_ENABLE_MULTICHANNEL,
};
@ -403,35 +410,121 @@ struct ath_offchannel {
int roc_duration;
int duration;
};
#define case_rtn_string(val) case val: return #val
#define ath_for_each_chanctx(_sc, _ctx) \
for (ctx = &sc->chanctx[0]; \
ctx <= &sc->chanctx[ARRAY_SIZE(sc->chanctx) - 1]; \
ctx++)
void ath9k_fill_chanctx_ops(void);
void ath9k_chanctx_force_active(struct ieee80211_hw *hw,
struct ieee80211_vif *vif);
void ath_chanctx_init(struct ath_softc *sc);
void ath_chanctx_set_channel(struct ath_softc *sc, struct ath_chanctx *ctx,
struct cfg80211_chan_def *chandef);
#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
static inline struct ath_chanctx *
ath_chanctx_get(struct ieee80211_chanctx_conf *ctx)
{
struct ath_chanctx **ptr = (void *) ctx->drv_priv;
return *ptr;
}
void ath_chanctx_init(struct ath_softc *sc);
void ath_chanctx_set_channel(struct ath_softc *sc, struct ath_chanctx *ctx,
struct cfg80211_chan_def *chandef);
void ath_chanctx_switch(struct ath_softc *sc, struct ath_chanctx *ctx,
struct cfg80211_chan_def *chandef);
bool ath9k_is_chanctx_enabled(void);
void ath9k_fill_chanctx_ops(void);
void ath9k_init_channel_context(struct ath_softc *sc);
void ath9k_offchannel_init(struct ath_softc *sc);
void ath9k_deinit_channel_context(struct ath_softc *sc);
int ath9k_init_p2p(struct ath_softc *sc);
void ath9k_deinit_p2p(struct ath_softc *sc);
void ath9k_p2p_remove_vif(struct ath_softc *sc,
struct ieee80211_vif *vif);
void ath9k_p2p_beacon_sync(struct ath_softc *sc);
void ath9k_p2p_bss_info_changed(struct ath_softc *sc,
struct ieee80211_vif *vif);
void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp,
struct sk_buff *skb);
void ath9k_p2p_ps_timer(void *priv);
void ath9k_chanctx_wake_queues(struct ath_softc *sc);
void ath_chanctx_check_active(struct ath_softc *sc, struct ath_chanctx *ctx);
void ath_offchannel_timer(unsigned long data);
void ath_offchannel_channel_change(struct ath_softc *sc);
void ath_chanctx_offchan_switch(struct ath_softc *sc,
struct ieee80211_channel *chan);
struct ath_chanctx *ath_chanctx_get_oper_chan(struct ath_softc *sc,
bool active);
void ath_chanctx_beacon_recv_ev(struct ath_softc *sc, u32 ts,
enum ath_chanctx_event ev);
void ath_chanctx_beacon_sent_ev(struct ath_softc *sc,
enum ath_chanctx_event ev);
void ath_chanctx_event(struct ath_softc *sc, struct ieee80211_vif *vif,
enum ath_chanctx_event ev);
void ath_chanctx_timer(unsigned long data);
void ath_chanctx_set_next(struct ath_softc *sc, bool force);
void ath_offchannel_next(struct ath_softc *sc);
void ath_scan_complete(struct ath_softc *sc, bool abort);
void ath_roc_complete(struct ath_softc *sc, bool abort);
#else
static inline bool ath9k_is_chanctx_enabled(void)
{
return false;
}
static inline void ath9k_fill_chanctx_ops(void)
{
}
static inline void ath9k_init_channel_context(struct ath_softc *sc)
{
}
static inline void ath9k_offchannel_init(struct ath_softc *sc)
{
}
static inline void ath9k_deinit_channel_context(struct ath_softc *sc)
{
}
static inline void ath_chanctx_beacon_recv_ev(struct ath_softc *sc, u32 ts,
enum ath_chanctx_event ev)
{
}
static inline void ath_chanctx_beacon_sent_ev(struct ath_softc *sc,
enum ath_chanctx_event ev)
{
}
static inline void ath_chanctx_event(struct ath_softc *sc,
struct ieee80211_vif *vif,
enum ath_chanctx_event ev)
{
}
static inline int ath9k_init_p2p(struct ath_softc *sc)
{
return 0;
}
static inline void ath9k_deinit_p2p(struct ath_softc *sc)
{
}
static inline void ath9k_p2p_remove_vif(struct ath_softc *sc,
struct ieee80211_vif *vif)
{
}
static inline void ath9k_p2p_beacon_sync(struct ath_softc *sc)
{
}
static inline void ath9k_p2p_bss_info_changed(struct ath_softc *sc,
struct ieee80211_vif *vif)
{
}
static inline void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp,
struct sk_buff *skb)
{
}
static inline void ath9k_p2p_ps_timer(struct ath_softc *sc)
{
}
static inline void ath9k_chanctx_wake_queues(struct ath_softc *sc)
{
}
static inline void ath_chanctx_check_active(struct ath_softc *sc,
struct ath_chanctx *ctx)
{
}
#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan);
int ath_startrecv(struct ath_softc *sc);
@ -583,7 +676,6 @@ void ath9k_csa_update(struct ath_softc *sc);
#define ATH_PAPRD_TIMEOUT 100 /* msecs */
#define ATH_PLL_WORK_INTERVAL 100
void ath_chanctx_work(struct work_struct *work);
void ath_tx_complete_poll_work(struct work_struct *work);
void ath_reset_work(struct work_struct *work);
bool ath_hw_check(struct ath_softc *sc);
@ -597,8 +689,6 @@ int ath_update_survey_stats(struct ath_softc *sc);
void ath_update_survey_nf(struct ath_softc *sc, int channel);
void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type);
void ath_ps_full_sleep(unsigned long data);
void ath9k_p2p_ps_timer(void *priv);
void ath9k_update_p2p_ps(struct ath_softc *sc, struct ieee80211_vif *vif);
void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop);
/**********/
@ -849,12 +939,17 @@ struct ath_softc {
struct mutex mutex;
struct work_struct paprd_work;
struct work_struct hw_reset_work;
struct work_struct chanctx_work;
struct completion paprd_complete;
wait_queue_head_t tx_wait;
#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
struct work_struct chanctx_work;
struct ath_gen_timer *p2p_ps_timer;
struct ath_vif *p2p_ps_vif;
struct ath_chanctx_sched sched;
struct ath_offchannel offchannel;
struct ath_chanctx *next_chan;
#endif
unsigned long driver_data;
@ -875,10 +970,7 @@ struct ath_softc {
struct cfg80211_chan_def cur_chandef;
struct ath_chanctx chanctx[ATH9K_NUM_CHANCTX];
struct ath_chanctx *cur_chan;
struct ath_chanctx *next_chan;
spinlock_t chan_lock;
struct ath_offchannel offchannel;
struct ath_chanctx_sched sched;
#ifdef CONFIG_MAC80211_LEDS
bool led_registered;

View File

@ -108,55 +108,6 @@ static void ath9k_beacon_setup(struct ath_softc *sc, struct ieee80211_vif *vif,
ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
}
static void ath9k_beacon_add_noa(struct ath_softc *sc, struct ath_vif *avp,
struct sk_buff *skb)
{
static const u8 noa_ie_hdr[] = {
WLAN_EID_VENDOR_SPECIFIC, /* type */
0, /* length */
0x50, 0x6f, 0x9a, /* WFA OUI */
0x09, /* P2P subtype */
0x0c, /* Notice of Absence */
0x00, /* LSB of little-endian len */
0x00, /* MSB of little-endian len */
};
struct ieee80211_p2p_noa_attr *noa;
int noa_len, noa_desc, i = 0;
u8 *hdr;
if (!avp->offchannel_duration && !avp->periodic_noa_duration)
return;
noa_desc = !!avp->offchannel_duration + !!avp->periodic_noa_duration;
noa_len = 2 + sizeof(struct ieee80211_p2p_noa_desc) * noa_desc;
hdr = skb_put(skb, sizeof(noa_ie_hdr));
memcpy(hdr, noa_ie_hdr, sizeof(noa_ie_hdr));
hdr[1] = sizeof(noa_ie_hdr) + noa_len - 2;
hdr[7] = noa_len;
noa = (void *) skb_put(skb, noa_len);
memset(noa, 0, noa_len);
noa->index = avp->noa_index;
if (avp->periodic_noa_duration) {
u32 interval = TU_TO_USEC(sc->cur_chan->beacon.beacon_interval);
noa->desc[i].count = 255;
noa->desc[i].start_time = cpu_to_le32(avp->periodic_noa_start);
noa->desc[i].duration = cpu_to_le32(avp->periodic_noa_duration);
noa->desc[i].interval = cpu_to_le32(interval);
i++;
}
if (avp->offchannel_duration) {
noa->desc[i].count = 1;
noa->desc[i].start_time = cpu_to_le32(avp->offchannel_start);
noa->desc[i].duration = cpu_to_le32(avp->offchannel_duration);
}
}
static struct ath_buf *ath9k_beacon_generate(struct ieee80211_hw *hw,
struct ieee80211_vif *vif)
{
@ -427,9 +378,10 @@ void ath9k_beacon_tasklet(unsigned long data)
/* EDMA devices check that in the tx completion function. */
if (!edma) {
if (sc->sched.beacon_pending)
ath_chanctx_event(sc, NULL,
if (ath9k_is_chanctx_enabled()) {
ath_chanctx_beacon_sent_ev(sc,
ATH_CHANCTX_EVENT_BEACON_SENT);
}
if (ath9k_csa_is_finished(sc, vif))
return;
@ -438,7 +390,10 @@ void ath9k_beacon_tasklet(unsigned long data)
if (!vif || !vif->bss_conf.enable_beacon)
return;
ath_chanctx_event(sc, vif, ATH_CHANCTX_EVENT_BEACON_PREPARE);
if (ath9k_is_chanctx_enabled()) {
ath_chanctx_event(sc, vif, ATH_CHANCTX_EVENT_BEACON_PREPARE);
}
bf = ath9k_beacon_generate(sc->hw, vif);
if (sc->beacon.bmisscnt != 0) {

File diff suppressed because it is too large Load Diff

View File

@ -592,6 +592,8 @@ static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN |
WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
hw->queues = 4;
hw->max_listen_interval = 1;

View File

@ -61,10 +61,14 @@ static int ath9k_ps_enable;
module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
int ath9k_use_chanctx;
module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
bool is_ath9k_unloaded;
#ifdef CONFIG_MAC80211_LEDS
@ -511,7 +515,7 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
sc->tx99_power = MAX_RATE_POWER + 1;
init_waitqueue_head(&sc->tx_wait);
sc->cur_chan = &sc->chanctx[0];
if (!ath9k_use_chanctx)
if (!ath9k_is_chanctx_enabled())
sc->cur_chan->hw_queue_base = 0;
if (!pdata || pdata->use_eeprom) {
@ -567,11 +571,9 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
setup_timer(&sc->sleep_timer, ath_ps_full_sleep, (unsigned long)sc);
INIT_WORK(&sc->hw_reset_work, ath_reset_work);
INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
INIT_WORK(&sc->chanctx_work, ath_chanctx_work);
INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
setup_timer(&sc->offchannel.timer, ath_offchannel_timer,
(unsigned long)sc);
setup_timer(&sc->sched.timer, ath_chanctx_timer, (unsigned long)sc);
ath9k_init_channel_context(sc);
/*
* Cache line size is used to size and align various
@ -600,13 +602,15 @@ static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
if (ret)
goto err_btcoex;
sc->p2p_ps_timer = ath_gen_timer_alloc(sc->sc_ah, ath9k_p2p_ps_timer,
NULL, sc, AR_FIRST_NDP_TIMER);
ret = ath9k_init_p2p(sc);
if (ret)
goto err_btcoex;
ath9k_cmn_init_crypto(sc->sc_ah);
ath9k_init_misc(sc);
ath_fill_led_pin(sc);
ath_chanctx_init(sc);
ath9k_offchannel_init(sc);
if (common->bus_ops->aspm_init)
common->bus_ops->aspm_init(common);
@ -672,18 +676,14 @@ static const struct ieee80211_iface_limit wds_limits[] = {
{ .max = 2048, .types = BIT(NL80211_IFTYPE_WDS) },
};
static const struct ieee80211_iface_limit if_limits_multi[] = {
{ .max = 1, .types = BIT(NL80211_IFTYPE_STATION) },
{ .max = 1, .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
BIT(NL80211_IFTYPE_P2P_GO) },
};
#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
static const struct ieee80211_iface_limit if_dfs_limits[] = {
{ .max = 1, .types = BIT(NL80211_IFTYPE_AP) |
#ifdef CONFIG_MAC80211_MESH
BIT(NL80211_IFTYPE_MESH_POINT) |
#endif
BIT(NL80211_IFTYPE_ADHOC) },
static const struct ieee80211_iface_limit if_limits_multi[] = {
{ .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
BIT(NL80211_IFTYPE_AP) |
BIT(NL80211_IFTYPE_P2P_CLIENT) |
BIT(NL80211_IFTYPE_P2P_GO) },
{ .max = 1, .types = BIT(NL80211_IFTYPE_ADHOC) },
};
static const struct ieee80211_iface_combination if_comb_multi[] = {
@ -696,6 +696,16 @@ static const struct ieee80211_iface_combination if_comb_multi[] = {
},
};
#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
static const struct ieee80211_iface_limit if_dfs_limits[] = {
{ .max = 1, .types = BIT(NL80211_IFTYPE_AP) |
#ifdef CONFIG_MAC80211_MESH
BIT(NL80211_IFTYPE_MESH_POINT) |
#endif
BIT(NL80211_IFTYPE_ADHOC) },
};
static const struct ieee80211_iface_combination if_comb[] = {
{
.limits = if_limits,
@ -763,24 +773,31 @@ static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
BIT(NL80211_IFTYPE_AP) |
BIT(NL80211_IFTYPE_STATION) |
BIT(NL80211_IFTYPE_ADHOC) |
BIT(NL80211_IFTYPE_MESH_POINT);
if (!ath9k_use_chanctx) {
BIT(NL80211_IFTYPE_MESH_POINT) |
BIT(NL80211_IFTYPE_WDS);
hw->wiphy->iface_combinations = if_comb;
hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_WDS);
} else {
hw->wiphy->iface_combinations = if_comb_multi;
hw->wiphy->n_iface_combinations =
ARRAY_SIZE(if_comb_multi);
hw->wiphy->max_scan_ssids = 255;
hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
hw->wiphy->max_remain_on_channel_duration = 10000;
hw->chanctx_data_size = sizeof(void *);
hw->extra_beacon_tailroom =
sizeof(struct ieee80211_p2p_noa_attr) + 9;
}
}
#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
if (ath9k_is_chanctx_enabled()) {
hw->wiphy->interface_modes &= ~ BIT(NL80211_IFTYPE_WDS);
hw->wiphy->iface_combinations = if_comb_multi;
hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
hw->wiphy->max_scan_ssids = 255;
hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
hw->wiphy->max_remain_on_channel_duration = 10000;
hw->chanctx_data_size = sizeof(void *);
hw->extra_beacon_tailroom =
sizeof(struct ieee80211_p2p_noa_attr) + 9;
ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
}
#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
@ -915,9 +932,7 @@ static void ath9k_deinit_softc(struct ath_softc *sc)
{
int i = 0;
if (sc->p2p_ps_timer)
ath_gen_timer_free(sc->sc_ah, sc->p2p_ps_timer);
ath9k_deinit_p2p(sc);
ath9k_deinit_btcoex(sc);
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)

View File

@ -223,7 +223,6 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start)
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
unsigned long flags;
int i;
if (ath_startrecv(sc) != 0) {
ath_err(common, "Unable to restart recv logic\n");
@ -268,20 +267,10 @@ static bool ath_complete_reset(struct ath_softc *sc, bool start)
ath9k_hw_set_interrupts(ah);
ath9k_hw_enable_interrupts(ah);
if (!ath9k_use_chanctx)
if (!ath9k_is_chanctx_enabled())
ieee80211_wake_queues(sc->hw);
else {
if (sc->cur_chan == &sc->offchannel.chan)
ieee80211_wake_queue(sc->hw,
sc->hw->offchannel_tx_hw_queue);
else {
for (i = 0; i < IEEE80211_NUM_ACS; i++)
ieee80211_wake_queue(sc->hw,
sc->cur_chan->hw_queue_base + i);
}
if (ah->opmode == NL80211_IFTYPE_AP)
ieee80211_wake_queue(sc->hw, sc->hw->queues - 2);
}
else
ath9k_chanctx_wake_queues(sc);
ath9k_p2p_ps_timer(sc);
@ -314,6 +303,9 @@ int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
if (!ath_prepare_reset(sc))
fastcc = false;
if (ath9k_is_chanctx_enabled())
fastcc = false;
spin_lock_bh(&sc->chan_lock);
sc->cur_chandef = sc->cur_chan->chandef;
spin_unlock_bh(&sc->chan_lock);
@ -822,7 +814,8 @@ static void ath9k_stop(struct ieee80211_hw *hw)
struct ath_common *common = ath9k_hw_common(ah);
bool prev_idle;
cancel_work_sync(&sc->chanctx_work);
ath9k_deinit_channel_context(sc);
mutex_lock(&sc->mutex);
ath_cancel_work(sc);
@ -903,9 +896,9 @@ static bool ath9k_uses_beacons(int type)
}
}
static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
u8 *mac, struct ieee80211_vif *vif)
{
struct ath9k_vif_iter_data *iter_data = data;
int i;
if (iter_data->has_hw_macaddr) {
@ -968,6 +961,7 @@ void ath9k_calculate_iter_data(struct ath_softc *sc,
list_for_each_entry(avp, &ctx->vifs, list)
ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
if (ctx == &sc->offchannel.chan) {
struct ieee80211_vif *vif;
@ -980,6 +974,7 @@ void ath9k_calculate_iter_data(struct ath_softc *sc,
ath9k_vif_iter(iter_data, vif->addr, vif);
iter_data->beacons = false;
}
#endif
}
static void ath9k_set_assoc_state(struct ath_softc *sc,
@ -1139,7 +1134,7 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
ath9k_beacon_assign_slot(sc, vif);
avp->vif = vif;
if (!ath9k_use_chanctx) {
if (!ath9k_is_chanctx_enabled()) {
avp->chanctx = sc->cur_chan;
list_add_tail(&avp->list, &avp->chanctx->vifs);
}
@ -1202,29 +1197,6 @@ static int ath9k_change_interface(struct ieee80211_hw *hw,
return 0;
}
static void
ath9k_update_p2p_ps_timer(struct ath_softc *sc, struct ath_vif *avp)
{
struct ath_hw *ah = sc->sc_ah;
s32 tsf, target_tsf;
if (!avp || !avp->noa.has_next_tsf)
return;
ath9k_hw_gen_timer_stop(ah, sc->p2p_ps_timer);
tsf = ath9k_hw_gettsf32(sc->sc_ah);
target_tsf = avp->noa.next_tsf;
if (!avp->noa.absent)
target_tsf -= ATH_P2P_PS_STOP_TIME;
if (target_tsf - tsf < ATH_P2P_PS_STOP_TIME)
target_tsf = tsf + ATH_P2P_PS_STOP_TIME;
ath9k_hw_gen_timer_start(ah, sc->p2p_ps_timer, (u32) target_tsf, 1000000);
}
static void ath9k_remove_interface(struct ieee80211_hw *hw,
struct ieee80211_vif *vif)
{
@ -1236,16 +1208,11 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
mutex_lock(&sc->mutex);
spin_lock_bh(&sc->sc_pcu_lock);
if (avp == sc->p2p_ps_vif) {
sc->p2p_ps_vif = NULL;
ath9k_update_p2p_ps_timer(sc, NULL);
}
spin_unlock_bh(&sc->sc_pcu_lock);
ath9k_p2p_remove_vif(sc, vif);
sc->nvifs--;
sc->tx99_vif = NULL;
if (!ath9k_use_chanctx)
if (!ath9k_is_chanctx_enabled())
list_del(&avp->list);
if (ath9k_uses_beacons(vif->type))
@ -1423,7 +1390,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
}
}
if (!ath9k_use_chanctx && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
}
@ -1687,70 +1654,6 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
return ret;
}
void ath9k_p2p_ps_timer(void *priv)
{
struct ath_softc *sc = priv;
struct ath_vif *avp = sc->p2p_ps_vif;
struct ieee80211_vif *vif;
struct ieee80211_sta *sta;
struct ath_node *an;
u32 tsf;
del_timer_sync(&sc->sched.timer);
ath9k_hw_gen_timer_stop(sc->sc_ah, sc->p2p_ps_timer);
ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_TSF_TIMER);
if (!avp || avp->chanctx != sc->cur_chan)
return;
tsf = ath9k_hw_gettsf32(sc->sc_ah);
if (!avp->noa.absent)
tsf += ATH_P2P_PS_STOP_TIME;
if (!avp->noa.has_next_tsf ||
avp->noa.next_tsf - tsf > BIT(31))
ieee80211_update_p2p_noa(&avp->noa, tsf);
ath9k_update_p2p_ps_timer(sc, avp);
rcu_read_lock();
vif = avp->vif;
sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
if (!sta)
goto out;
an = (void *) sta->drv_priv;
if (an->sleeping == !!avp->noa.absent)
goto out;
an->sleeping = avp->noa.absent;
if (an->sleeping)
ath_tx_aggr_sleep(sta, sc, an);
else
ath_tx_aggr_wakeup(sc, an);
out:
rcu_read_unlock();
}
void ath9k_update_p2p_ps(struct ath_softc *sc, struct ieee80211_vif *vif)
{
struct ath_vif *avp = (void *)vif->drv_priv;
u32 tsf;
if (!sc->p2p_ps_timer)
return;
if (vif->type != NL80211_IFTYPE_STATION || !vif->p2p)
return;
sc->p2p_ps_vif = avp;
tsf = ath9k_hw_gettsf32(sc->sc_ah);
ieee80211_parse_p2p_noa(&vif->bss_conf.p2p_noa_attr, &avp->noa, tsf);
ath9k_update_p2p_ps_timer(sc, avp);
}
static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
struct ieee80211_bss_conf *bss_conf,
@ -1765,7 +1668,6 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
struct ath_hw *ah = sc->sc_ah;
struct ath_common *common = ath9k_hw_common(ah);
struct ath_vif *avp = (void *)vif->drv_priv;
unsigned long flags;
int slottime;
ath9k_ps_wakeup(sc);
@ -1776,8 +1678,12 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
bss_conf->bssid, bss_conf->assoc);
ath9k_calculate_summary_state(sc, avp->chanctx);
if (bss_conf->assoc)
ath_chanctx_event(sc, vif, ATH_CHANCTX_EVENT_ASSOC);
if (ath9k_is_chanctx_enabled()) {
if (bss_conf->assoc)
ath_chanctx_event(sc, vif,
ATH_CHANCTX_EVENT_ASSOC);
}
}
if (changed & BSS_CHANGED_IBSS) {
@ -1814,14 +1720,8 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
}
}
if (changed & BSS_CHANGED_P2P_PS) {
spin_lock_bh(&sc->sc_pcu_lock);
spin_lock_irqsave(&sc->sc_pm_lock, flags);
if (!(sc->ps_flags & PS_BEACON_SYNC))
ath9k_update_p2p_ps(sc, vif);
spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
spin_unlock_bh(&sc->sc_pcu_lock);
}
if (changed & BSS_CHANGED_P2P_PS)
ath9k_p2p_bss_info_changed(sc, vif);
if (changed & CHECK_ANI)
ath_check_ani(sc);
@ -2207,207 +2107,7 @@ static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
clear_bit(ATH_OP_SCANNING, &common->op_flags);
}
static int ath_scan_channel_duration(struct ath_softc *sc,
struct ieee80211_channel *chan)
{
struct cfg80211_scan_request *req = sc->offchannel.scan_req;
if (!req->n_ssids || (chan->flags & IEEE80211_CHAN_NO_IR))
return (HZ / 9); /* ~110 ms */
return (HZ / 16); /* ~60 ms */
}
static void
ath_scan_next_channel(struct ath_softc *sc)
{
struct cfg80211_scan_request *req = sc->offchannel.scan_req;
struct ieee80211_channel *chan;
if (sc->offchannel.scan_idx >= req->n_channels) {
sc->offchannel.state = ATH_OFFCHANNEL_IDLE;
ath_chanctx_switch(sc, ath_chanctx_get_oper_chan(sc, false),
NULL);
return;
}
chan = req->channels[sc->offchannel.scan_idx++];
sc->offchannel.duration = ath_scan_channel_duration(sc, chan);
sc->offchannel.state = ATH_OFFCHANNEL_PROBE_SEND;
ath_chanctx_offchan_switch(sc, chan);
}
static void ath_offchannel_next(struct ath_softc *sc)
{
struct ieee80211_vif *vif;
if (sc->offchannel.scan_req) {
vif = sc->offchannel.scan_vif;
sc->offchannel.chan.txpower = vif->bss_conf.txpower;
ath_scan_next_channel(sc);
} else if (sc->offchannel.roc_vif) {
vif = sc->offchannel.roc_vif;
sc->offchannel.chan.txpower = vif->bss_conf.txpower;
sc->offchannel.duration = sc->offchannel.roc_duration;
sc->offchannel.state = ATH_OFFCHANNEL_ROC_START;
ath_chanctx_offchan_switch(sc, sc->offchannel.roc_chan);
} else {
ath_chanctx_switch(sc, ath_chanctx_get_oper_chan(sc, false),
NULL);
sc->offchannel.state = ATH_OFFCHANNEL_IDLE;
if (sc->ps_idle)
ath_cancel_work(sc);
}
}
static void ath_roc_complete(struct ath_softc *sc, bool abort)
{
sc->offchannel.roc_vif = NULL;
sc->offchannel.roc_chan = NULL;
if (!abort)
ieee80211_remain_on_channel_expired(sc->hw);
ath_offchannel_next(sc);
ath9k_ps_restore(sc);
}
static void ath_scan_complete(struct ath_softc *sc, bool abort)
{
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
sc->offchannel.scan_req = NULL;
sc->offchannel.scan_vif = NULL;
sc->offchannel.state = ATH_OFFCHANNEL_IDLE;
ieee80211_scan_completed(sc->hw, abort);
clear_bit(ATH_OP_SCANNING, &common->op_flags);
ath_offchannel_next(sc);
ath9k_ps_restore(sc);
}
static void ath_scan_send_probe(struct ath_softc *sc,
struct cfg80211_ssid *ssid)
{
struct cfg80211_scan_request *req = sc->offchannel.scan_req;
struct ieee80211_vif *vif = sc->offchannel.scan_vif;
struct ath_tx_control txctl = {};
struct sk_buff *skb;
struct ieee80211_tx_info *info;
int band = sc->offchannel.chan.chandef.chan->band;
skb = ieee80211_probereq_get(sc->hw, vif,
ssid->ssid, ssid->ssid_len, req->ie_len);
if (!skb)
return;
info = IEEE80211_SKB_CB(skb);
if (req->no_cck)
info->flags |= IEEE80211_TX_CTL_NO_CCK_RATE;
if (req->ie_len)
memcpy(skb_put(skb, req->ie_len), req->ie, req->ie_len);
skb_set_queue_mapping(skb, IEEE80211_AC_VO);
if (!ieee80211_tx_prepare_skb(sc->hw, vif, skb, band, NULL))
goto error;
txctl.txq = sc->tx.txq_map[IEEE80211_AC_VO];
txctl.force_channel = true;
if (ath_tx_start(sc->hw, skb, &txctl))
goto error;
return;
error:
ieee80211_free_txskb(sc->hw, skb);
}
static void ath_scan_channel_start(struct ath_softc *sc)
{
struct cfg80211_scan_request *req = sc->offchannel.scan_req;
int i;
if (!(sc->cur_chan->chandef.chan->flags & IEEE80211_CHAN_NO_IR) &&
req->n_ssids) {
for (i = 0; i < req->n_ssids; i++)
ath_scan_send_probe(sc, &req->ssids[i]);
}
sc->offchannel.state = ATH_OFFCHANNEL_PROBE_WAIT;
mod_timer(&sc->offchannel.timer, jiffies + sc->offchannel.duration);
}
void ath_offchannel_channel_change(struct ath_softc *sc)
{
switch (sc->offchannel.state) {
case ATH_OFFCHANNEL_PROBE_SEND:
if (!sc->offchannel.scan_req)
return;
if (sc->cur_chan->chandef.chan !=
sc->offchannel.chan.chandef.chan)
return;
ath_scan_channel_start(sc);
break;
case ATH_OFFCHANNEL_IDLE:
if (!sc->offchannel.scan_req)
return;
ath_scan_complete(sc, false);
break;
case ATH_OFFCHANNEL_ROC_START:
if (sc->cur_chan != &sc->offchannel.chan)
break;
sc->offchannel.state = ATH_OFFCHANNEL_ROC_WAIT;
mod_timer(&sc->offchannel.timer, jiffies +
msecs_to_jiffies(sc->offchannel.duration));
ieee80211_ready_on_channel(sc->hw);
break;
case ATH_OFFCHANNEL_ROC_DONE:
ath_roc_complete(sc, false);
break;
default:
break;
}
}
void ath_offchannel_timer(unsigned long data)
{
struct ath_softc *sc = (struct ath_softc *)data;
struct ath_chanctx *ctx;
switch (sc->offchannel.state) {
case ATH_OFFCHANNEL_PROBE_WAIT:
if (!sc->offchannel.scan_req)
return;
/* get first active channel context */
ctx = ath_chanctx_get_oper_chan(sc, true);
if (ctx->active) {
sc->offchannel.state = ATH_OFFCHANNEL_SUSPEND;
ath_chanctx_switch(sc, ctx, NULL);
mod_timer(&sc->offchannel.timer, jiffies + HZ / 10);
break;
}
/* fall through */
case ATH_OFFCHANNEL_SUSPEND:
if (!sc->offchannel.scan_req)
return;
ath_scan_next_channel(sc);
break;
case ATH_OFFCHANNEL_ROC_START:
case ATH_OFFCHANNEL_ROC_WAIT:
ctx = ath_chanctx_get_oper_chan(sc, false);
sc->offchannel.state = ATH_OFFCHANNEL_ROC_DONE;
ath_chanctx_switch(sc, ctx, NULL);
break;
default:
break;
}
}
#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_scan_request *hw_req)
@ -2430,8 +2130,13 @@ static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
sc->offchannel.scan_req = req;
sc->offchannel.scan_idx = 0;
if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE)
ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
vif->addr);
if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
ath_offchannel_next(sc);
}
out:
mutex_unlock(&sc->mutex);
@ -2443,6 +2148,9 @@ static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
struct ieee80211_vif *vif)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
mutex_lock(&sc->mutex);
del_timer_sync(&sc->offchannel.timer);
@ -2456,6 +2164,7 @@ static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
enum ieee80211_roc_type type)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
int ret = 0;
mutex_lock(&sc->mutex);
@ -2470,8 +2179,14 @@ static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
sc->offchannel.roc_chan = chan;
sc->offchannel.roc_duration = duration;
if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE)
ath_dbg(common, CHAN_CTX,
"RoC request on vif: %pM, type: %d duration: %d\n",
vif->addr, type, duration);
if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
ath_offchannel_next(sc);
}
out:
mutex_unlock(&sc->mutex);
@ -2482,9 +2197,11 @@ out:
static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
mutex_lock(&sc->mutex);
ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
del_timer_sync(&sc->offchannel.timer);
if (sc->offchannel.roc_vif) {
@ -2501,6 +2218,7 @@ static int ath9k_add_chanctx(struct ieee80211_hw *hw,
struct ieee80211_chanctx_conf *conf)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_chanctx *ctx, **ptr;
int pos;
@ -2515,10 +2233,18 @@ static int ath9k_add_chanctx(struct ieee80211_hw *hw,
ctx->assigned = true;
pos = ctx - &sc->chanctx[0];
ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
ath_dbg(common, CHAN_CTX,
"Add channel context: %d MHz\n",
conf->def.chan->center_freq);
ath_chanctx_set_channel(sc, ctx, &conf->def);
ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_ASSIGN);
mutex_unlock(&sc->mutex);
return 0;
}
mutex_unlock(&sc->mutex);
return -ENOSPC;
}
@ -2528,12 +2254,19 @@ static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
struct ieee80211_chanctx_conf *conf)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_chanctx *ctx = ath_chanctx_get(conf);
mutex_lock(&sc->mutex);
ath_dbg(common, CHAN_CTX,
"Remove channel context: %d MHz\n",
conf->def.chan->center_freq);
ctx->assigned = false;
ctx->hw_queue_base = -1;
ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
mutex_unlock(&sc->mutex);
}
@ -2542,9 +2275,13 @@ static void ath9k_change_chanctx(struct ieee80211_hw *hw,
u32 changed)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_chanctx *ctx = ath_chanctx_get(conf);
mutex_lock(&sc->mutex);
ath_dbg(common, CHAN_CTX,
"Change channel context: %d MHz\n",
conf->def.chan->center_freq);
ath_chanctx_set_channel(sc, ctx, &conf->def);
mutex_unlock(&sc->mutex);
}
@ -2554,16 +2291,24 @@ static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
struct ieee80211_chanctx_conf *conf)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_vif *avp = (void *)vif->drv_priv;
struct ath_chanctx *ctx = ath_chanctx_get(conf);
int i;
mutex_lock(&sc->mutex);
ath_dbg(common, CHAN_CTX,
"Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
vif->addr, vif->type, vif->p2p,
conf->def.chan->center_freq);
avp->chanctx = ctx;
list_add_tail(&avp->list, &ctx->vifs);
ath9k_calculate_summary_state(sc, ctx);
for (i = 0; i < IEEE80211_NUM_ACS; i++)
vif->hw_queue[i] = ctx->hw_queue_base + i;
mutex_unlock(&sc->mutex);
return 0;
@ -2574,36 +2319,79 @@ static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
struct ieee80211_chanctx_conf *conf)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_vif *avp = (void *)vif->drv_priv;
struct ath_chanctx *ctx = ath_chanctx_get(conf);
int ac;
mutex_lock(&sc->mutex);
ath_dbg(common, CHAN_CTX,
"Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
vif->addr, vif->type, vif->p2p,
conf->def.chan->center_freq);
avp->chanctx = NULL;
list_del(&avp->list);
ath9k_calculate_summary_state(sc, ctx);
for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
mutex_unlock(&sc->mutex);
}
static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
struct ieee80211_vif *vif)
{
struct ath_softc *sc = hw->priv;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
bool changed = false;
if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
return;
if (!avp->chanctx)
return;
mutex_lock(&sc->mutex);
spin_lock_bh(&sc->chan_lock);
if (sc->next_chan || (sc->cur_chan != avp->chanctx)) {
sc->next_chan = avp->chanctx;
changed = true;
}
ath_dbg(common, CHAN_CTX,
"%s: Set chanctx state to FORCE_ACTIVE, changed: %d\n",
__func__, changed);
sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
spin_unlock_bh(&sc->chan_lock);
if (changed)
ath_chanctx_set_next(sc, true);
mutex_unlock(&sc->mutex);
}
void ath9k_fill_chanctx_ops(void)
{
if (!ath9k_use_chanctx)
if (!ath9k_is_chanctx_enabled())
return;
ath9k_ops.hw_scan = ath9k_hw_scan;
ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
ath9k_ops.hw_scan = ath9k_hw_scan;
ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
ath9k_ops.add_chanctx = ath9k_add_chanctx;
ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
ath9k_ops.change_chanctx = ath9k_change_chanctx;
ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
ath9k_ops.mgd_prepare_tx = ath9k_chanctx_force_active;
ath9k_ops.add_chanctx = ath9k_add_chanctx;
ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
ath9k_ops.change_chanctx = ath9k_change_chanctx;
ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
}
#endif
struct ieee80211_ops ath9k_ops = {
.tx = ath9k_tx,
.start = ath9k_start,

View File

@ -425,7 +425,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc)
if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah))
rfilt |= ATH9K_RX_FILTER_4ADDRESS;
if (ath9k_use_chanctx &&
if (ath9k_is_chanctx_enabled() &&
test_bit(ATH_OP_SCANNING, &common->op_flags))
rfilt |= ATH9K_RX_FILTER_BEACON;
@ -547,8 +547,8 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
"Reconfigure beacon timers based on synchronized timestamp\n");
if (!(WARN_ON_ONCE(sc->cur_chan->beacon.beacon_interval == 0)))
ath9k_set_beacon(sc);
if (sc->p2p_ps_vif)
ath9k_update_p2p_ps(sc, sc->p2p_ps_vif->vif);
ath9k_p2p_beacon_sync(sc);
}
if (ath_beacon_dtim_pending_cab(skb)) {
@ -892,9 +892,10 @@ static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
return -EINVAL;
}
if (rx_stats->is_mybeacon) {
sc->sched.next_tbtt = rx_stats->rs_tstamp;
ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_BEACON_RECEIVED);
if (ath9k_is_chanctx_enabled()) {
if (rx_stats->is_mybeacon)
ath_chanctx_beacon_recv_ev(sc, rx_stats->rs_tstamp,
ATH_CHANCTX_EVENT_BEACON_RECEIVED);
}
ath9k_cmn_process_rssi(common, hw, rx_stats, rx_status);

View File

@ -17,6 +17,8 @@
#ifndef SPECTRAL_H
#define SPECTRAL_H
#include "../spectral_common.h"
/* enum spectral_mode:
*
* @SPECTRAL_DISABLED: spectral mode is disabled
@ -54,8 +56,6 @@ struct ath_ht20_mag_info {
u8 max_exp;
} __packed;
#define SPECTRAL_HT20_NUM_BINS 56
/* WARNING: don't actually use this struct! MAC may vary the amount of
* data by -1/+2. This struct is for reference only.
*/
@ -83,8 +83,6 @@ struct ath_ht20_40_mag_info {
u8 max_exp;
} __packed;
#define SPECTRAL_HT20_40_NUM_BINS 128
/* WARNING: don't actually use this struct! MAC may vary the amount of
* data. This struct is for reference only.
*/
@ -125,71 +123,6 @@ static inline u8 spectral_bitmap_weight(u8 *bins)
return bins[0] & 0x3f;
}
/* FFT sample format given to userspace via debugfs.
*
* Please keep the type/length at the front position and change
* other fields after adding another sample type
*
* TODO: this might need rework when switching to nl80211-based
* interface.
*/
enum ath_fft_sample_type {
ATH_FFT_SAMPLE_HT20 = 1,
ATH_FFT_SAMPLE_HT20_40,
};
struct fft_sample_tlv {
u8 type; /* see ath_fft_sample */
__be16 length;
/* type dependent data follows */
} __packed;
struct fft_sample_ht20 {
struct fft_sample_tlv tlv;
u8 max_exp;
__be16 freq;
s8 rssi;
s8 noise;
__be16 max_magnitude;
u8 max_index;
u8 bitmap_weight;
__be64 tsf;
u8 data[SPECTRAL_HT20_NUM_BINS];
} __packed;
struct fft_sample_ht20_40 {
struct fft_sample_tlv tlv;
u8 channel_type;
__be16 freq;
s8 lower_rssi;
s8 upper_rssi;
__be64 tsf;
s8 lower_noise;
s8 upper_noise;
__be16 lower_max_magnitude;
__be16 upper_max_magnitude;
u8 lower_max_index;
u8 upper_max_index;
u8 lower_bitmap_weight;
u8 upper_bitmap_weight;
u8 max_exp;
u8 data[SPECTRAL_HT20_40_NUM_BINS];
} __packed;
void ath9k_spectral_init_debug(struct ath_softc *sc);
void ath9k_spectral_deinit_debug(struct ath_softc *sc);

View File

@ -193,7 +193,8 @@ int ath9k_suspend(struct ieee80211_hw *hw,
u32 wow_triggers_enabled = 0;
int ret = 0;
cancel_work_sync(&sc->chanctx_work);
ath9k_deinit_channel_context(sc);
mutex_lock(&sc->mutex);
ath_cancel_work(sc);

View File

@ -2632,8 +2632,11 @@ void ath_tx_edma_tasklet(struct ath_softc *sc)
sc->beacon.tx_processed = true;
sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
ath_chanctx_event(sc, NULL,
ATH_CHANCTX_EVENT_BEACON_SENT);
if (ath9k_is_chanctx_enabled()) {
ath_chanctx_event(sc, NULL,
ATH_CHANCTX_EVENT_BEACON_SENT);
}
ath9k_csa_update(sc);
continue;
}

View File

@ -1430,18 +1430,10 @@ static int carl9170_op_ampdu_action(struct ieee80211_hw *hw,
if (!sta_info->ht_sta)
return -EOPNOTSUPP;
rcu_read_lock();
if (rcu_dereference(sta_info->agg[tid])) {
rcu_read_unlock();
return -EBUSY;
}
tid_info = kzalloc(sizeof(struct carl9170_sta_tid),
GFP_ATOMIC);
if (!tid_info) {
rcu_read_unlock();
if (!tid_info)
return -ENOMEM;
}
tid_info->hsn = tid_info->bsn = tid_info->snx = (*ssn);
tid_info->state = CARL9170_TID_STATE_PROGRESS;
@ -1460,7 +1452,6 @@ static int carl9170_op_ampdu_action(struct ieee80211_hw *hw,
list_add_tail_rcu(&tid_info->list, &ar->tx_ampdu_list);
rcu_assign_pointer(sta_info->agg[tid], tid_info);
spin_unlock_bh(&ar->tx_ampdu_list_lock);
rcu_read_unlock();
ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
break;

View File

@ -1557,7 +1557,7 @@ static struct carl9170_vif_info *carl9170_pick_beaconing_vif(struct ar9170 *ar)
}
out:
rcu_assign_pointer(ar->beacon_iter, cvif);
RCU_INIT_POINTER(ar->beacon_iter, cvif);
return cvif;
}

View File

@ -0,0 +1,113 @@
/*
* Copyright (c) 2013 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef SPECTRAL_COMMON_H
#define SPECTRAL_COMMON_H
#define SPECTRAL_HT20_NUM_BINS 56
#define SPECTRAL_HT20_40_NUM_BINS 128
/* TODO: could possibly be 512, but no samples this large
* could be acquired so far.
*/
#define SPECTRAL_ATH10K_MAX_NUM_BINS 256
/* FFT sample format given to userspace via debugfs.
*
* Please keep the type/length at the front position and change
* other fields after adding another sample type
*
* TODO: this might need rework when switching to nl80211-based
* interface.
*/
enum ath_fft_sample_type {
ATH_FFT_SAMPLE_HT20 = 1,
ATH_FFT_SAMPLE_HT20_40,
ATH_FFT_SAMPLE_ATH10K,
};
struct fft_sample_tlv {
u8 type; /* see ath_fft_sample */
__be16 length;
/* type dependent data follows */
} __packed;
struct fft_sample_ht20 {
struct fft_sample_tlv tlv;
u8 max_exp;
__be16 freq;
s8 rssi;
s8 noise;
__be16 max_magnitude;
u8 max_index;
u8 bitmap_weight;
__be64 tsf;
u8 data[SPECTRAL_HT20_NUM_BINS];
} __packed;
struct fft_sample_ht20_40 {
struct fft_sample_tlv tlv;
u8 channel_type;
__be16 freq;
s8 lower_rssi;
s8 upper_rssi;
__be64 tsf;
s8 lower_noise;
s8 upper_noise;
__be16 lower_max_magnitude;
__be16 upper_max_magnitude;
u8 lower_max_index;
u8 upper_max_index;
u8 lower_bitmap_weight;
u8 upper_bitmap_weight;
u8 max_exp;
u8 data[SPECTRAL_HT20_40_NUM_BINS];
} __packed;
struct fft_sample_ath10k {
struct fft_sample_tlv tlv;
u8 chan_width_mhz;
__be16 freq1;
__be16 freq2;
__be16 noise;
__be16 max_magnitude;
__be16 total_gain_db;
__be16 base_pwr_db;
__be64 tsf;
s8 max_index;
u8 rssi;
u8 relpwr_db;
u8 avgpwr_db;
u8 max_exp;
u8 data[0];
} __packed;
#endif /* SPECTRAL_COMMON_H */

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -311,8 +311,10 @@ static int wil_cfg80211_scan(struct wiphy *wiphy,
rc = wmi_send(wil, WMI_START_SCAN_CMDID, &cmd, sizeof(cmd.cmd) +
cmd.cmd.num_channels * sizeof(cmd.cmd.channel_list[0]));
if (rc)
if (rc) {
del_timer_sync(&wil->scan_timer);
wil->scan_request = NULL;
}
return rc;
}

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -22,6 +22,7 @@
#include <linux/power_supply.h>
#include "wil6210.h"
#include "wmi.h"
#include "txrx.h"
/* Nasty hack. Better have per device instances */
@ -29,6 +30,21 @@ static u32 mem_addr;
static u32 dbg_txdesc_index;
static u32 dbg_vring_index; /* 24+ for Rx, 0..23 for Tx */
enum dbg_off_type {
doff_u32 = 0,
doff_x32 = 1,
doff_ulong = 2,
doff_io32 = 3,
};
/* offset to "wil" */
struct dbg_off {
const char *name;
umode_t mode;
ulong off;
enum dbg_off_type type;
};
static void wil_print_vring(struct seq_file *s, struct wil6210_priv *wil,
const char *name, struct vring *vring,
char _s, char _h)
@ -244,9 +260,9 @@ DEFINE_SIMPLE_ATTRIBUTE(fops_iomem_x32, wil_debugfs_iomem_x32_get,
static struct dentry *wil_debugfs_create_iomem_x32(const char *name,
umode_t mode,
struct dentry *parent,
void __iomem *value)
void *value)
{
return debugfs_create_file(name, mode, parent, (void * __force)value,
return debugfs_create_file(name, mode, parent, value,
&fops_iomem_x32);
}
@ -270,6 +286,59 @@ static struct dentry *wil_debugfs_create_ulong(const char *name, umode_t mode,
return debugfs_create_file(name, mode, parent, value, &wil_fops_ulong);
}
/**
* wil6210_debugfs_init_offset - create set of debugfs files
* @wil - driver's context, used for printing
* @dbg - directory on the debugfs, where files will be created
* @base - base address used in address calculation
* @tbl - table with file descriptions. Should be terminated with empty element.
*
* Creates files accordingly to the @tbl.
*/
static void wil6210_debugfs_init_offset(struct wil6210_priv *wil,
struct dentry *dbg, void *base,
const struct dbg_off * const tbl)
{
int i;
for (i = 0; tbl[i].name; i++) {
struct dentry *f = NULL;
switch (tbl[i].type) {
case doff_u32:
f = debugfs_create_u32(tbl[i].name, tbl[i].mode, dbg,
base + tbl[i].off);
break;
case doff_x32:
f = debugfs_create_x32(tbl[i].name, tbl[i].mode, dbg,
base + tbl[i].off);
break;
case doff_ulong:
f = wil_debugfs_create_ulong(tbl[i].name, tbl[i].mode,
dbg, base + tbl[i].off);
break;
case doff_io32:
f = wil_debugfs_create_iomem_x32(tbl[i].name,
tbl[i].mode, dbg,
base + tbl[i].off);
break;
}
if (IS_ERR_OR_NULL(f))
wil_err(wil, "Create file \"%s\": err %ld\n",
tbl[i].name, PTR_ERR(f));
}
}
static const struct dbg_off isr_off[] = {
{"ICC", S_IRUGO | S_IWUSR, offsetof(struct RGF_ICR, ICC), doff_io32},
{"ICR", S_IRUGO | S_IWUSR, offsetof(struct RGF_ICR, ICR), doff_io32},
{"ICM", S_IRUGO | S_IWUSR, offsetof(struct RGF_ICR, ICM), doff_io32},
{"ICS", S_IWUSR, offsetof(struct RGF_ICR, ICS), doff_io32},
{"IMV", S_IRUGO | S_IWUSR, offsetof(struct RGF_ICR, IMV), doff_io32},
{"IMS", S_IWUSR, offsetof(struct RGF_ICR, IMS), doff_io32},
{"IMC", S_IWUSR, offsetof(struct RGF_ICR, IMC), doff_io32},
{},
};
static int wil6210_debugfs_create_ISR(struct wil6210_priv *wil,
const char *name,
struct dentry *parent, u32 off)
@ -279,24 +348,19 @@ static int wil6210_debugfs_create_ISR(struct wil6210_priv *wil,
if (IS_ERR_OR_NULL(d))
return -ENODEV;
wil_debugfs_create_iomem_x32("ICC", S_IRUGO | S_IWUSR, d,
wil->csr + off);
wil_debugfs_create_iomem_x32("ICR", S_IRUGO | S_IWUSR, d,
wil->csr + off + 4);
wil_debugfs_create_iomem_x32("ICM", S_IRUGO | S_IWUSR, d,
wil->csr + off + 8);
wil_debugfs_create_iomem_x32("ICS", S_IWUSR, d,
wil->csr + off + 12);
wil_debugfs_create_iomem_x32("IMV", S_IRUGO | S_IWUSR, d,
wil->csr + off + 16);
wil_debugfs_create_iomem_x32("IMS", S_IWUSR, d,
wil->csr + off + 20);
wil_debugfs_create_iomem_x32("IMC", S_IWUSR, d,
wil->csr + off + 24);
wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr + off,
isr_off);
return 0;
}
static const struct dbg_off pseudo_isr_off[] = {
{"CAUSE", S_IRUGO, HOSTADDR(RGF_DMA_PSEUDO_CAUSE), doff_io32},
{"MASK_SW", S_IRUGO, HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW), doff_io32},
{"MASK_FW", S_IRUGO, HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_FW), doff_io32},
{},
};
static int wil6210_debugfs_create_pseudo_ISR(struct wil6210_priv *wil,
struct dentry *parent)
{
@ -305,16 +369,19 @@ static int wil6210_debugfs_create_pseudo_ISR(struct wil6210_priv *wil,
if (IS_ERR_OR_NULL(d))
return -ENODEV;
wil_debugfs_create_iomem_x32("CAUSE", S_IRUGO, d, wil->csr +
HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
wil_debugfs_create_iomem_x32("MASK_SW", S_IRUGO, d, wil->csr +
HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
wil_debugfs_create_iomem_x32("MASK_FW", S_IRUGO, d, wil->csr +
HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_FW));
wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr,
pseudo_isr_off);
return 0;
}
static const struct dbg_off itr_cnt_off[] = {
{"TRSH", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_CNT_TRSH), doff_io32},
{"DATA", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_CNT_DATA), doff_io32},
{"CTL", S_IRUGO | S_IWUSR, HOSTADDR(RGF_DMA_ITR_CNT_CRL), doff_io32},
{},
};
static int wil6210_debugfs_create_ITR_CNT(struct wil6210_priv *wil,
struct dentry *parent)
{
@ -323,12 +390,8 @@ static int wil6210_debugfs_create_ITR_CNT(struct wil6210_priv *wil,
if (IS_ERR_OR_NULL(d))
return -ENODEV;
wil_debugfs_create_iomem_x32("TRSH", S_IRUGO | S_IWUSR, d, wil->csr +
HOSTADDR(RGF_DMA_ITR_CNT_TRSH));
wil_debugfs_create_iomem_x32("DATA", S_IRUGO | S_IWUSR, d, wil->csr +
HOSTADDR(RGF_DMA_ITR_CNT_DATA));
wil_debugfs_create_iomem_x32("CTL", S_IRUGO | S_IWUSR, d, wil->csr +
HOSTADDR(RGF_DMA_ITR_CNT_CRL));
wil6210_debugfs_init_offset(wil, d, (void * __force)wil->csr,
itr_cnt_off);
return 0;
}
@ -666,16 +729,79 @@ static const struct file_operations fops_txdesc = {
};
/*---------beamforming------------*/
static char *wil_bfstatus_str(u32 status)
{
switch (status) {
case 0:
return "Failed";
case 1:
return "OK";
case 2:
return "Retrying";
default:
return "??";
}
}
static bool is_all_zeros(void * const x_, size_t sz)
{
/* if reply is all-0, ignore this CID */
u32 *x = x_;
int n;
for (n = 0; n < sz / sizeof(*x); n++)
if (x[n])
return false;
return true;
}
static int wil_bf_debugfs_show(struct seq_file *s, void *data)
{
int rc;
int i;
struct wil6210_priv *wil = s->private;
seq_printf(s,
"TSF : 0x%016llx\n"
"TxMCS : %d\n"
"Sectors(rx:tx) my %2d:%2d peer %2d:%2d\n",
wil->stats.tsf, wil->stats.bf_mcs,
wil->stats.my_rx_sector, wil->stats.my_tx_sector,
wil->stats.peer_rx_sector, wil->stats.peer_tx_sector);
struct wmi_notify_req_cmd cmd = {
.interval_usec = 0,
};
struct {
struct wil6210_mbox_hdr_wmi wmi;
struct wmi_notify_req_done_event evt;
} __packed reply;
for (i = 0; i < ARRAY_SIZE(wil->sta); i++) {
u32 status;
cmd.cid = i;
rc = wmi_call(wil, WMI_NOTIFY_REQ_CMDID, &cmd, sizeof(cmd),
WMI_NOTIFY_REQ_DONE_EVENTID, &reply,
sizeof(reply), 20);
/* if reply is all-0, ignore this CID */
if (rc || is_all_zeros(&reply.evt, sizeof(reply.evt)))
continue;
status = le32_to_cpu(reply.evt.status);
seq_printf(s, "CID %d {\n"
" TSF = 0x%016llx\n"
" TxMCS = %2d TxTpt = %4d\n"
" SQI = %4d\n"
" Status = 0x%08x %s\n"
" Sectors(rx:tx) my %2d:%2d peer %2d:%2d\n"
" Goodput(rx:tx) %4d:%4d\n"
"}\n",
i,
le64_to_cpu(reply.evt.tsf),
le16_to_cpu(reply.evt.bf_mcs),
le32_to_cpu(reply.evt.tx_tpt),
reply.evt.sqi,
status, wil_bfstatus_str(status),
le16_to_cpu(reply.evt.my_rx_sector),
le16_to_cpu(reply.evt.my_tx_sector),
le16_to_cpu(reply.evt.other_rx_sector),
le16_to_cpu(reply.evt.other_tx_sector),
le32_to_cpu(reply.evt.rx_goodput),
le32_to_cpu(reply.evt.tx_goodput));
}
return 0;
}
@ -985,6 +1111,87 @@ static void wil6210_debugfs_init_blobs(struct wil6210_priv *wil,
}
}
/* misc files */
static const struct {
const char *name;
umode_t mode;
const struct file_operations *fops;
} dbg_files[] = {
{"mbox", S_IRUGO, &fops_mbox},
{"vrings", S_IRUGO, &fops_vring},
{"stations", S_IRUGO, &fops_sta},
{"desc", S_IRUGO, &fops_txdesc},
{"bf", S_IRUGO, &fops_bf},
{"ssid", S_IRUGO | S_IWUSR, &fops_ssid},
{"mem_val", S_IRUGO, &fops_memread},
{"reset", S_IWUSR, &fops_reset},
{"rxon", S_IWUSR, &fops_rxon},
{"tx_mgmt", S_IWUSR, &fops_txmgmt},
{"wmi_send", S_IWUSR, &fops_wmi},
{"temp", S_IRUGO, &fops_temp},
{"freq", S_IRUGO, &fops_freq},
{"link", S_IRUGO, &fops_link},
{"info", S_IRUGO, &fops_info},
};
static void wil6210_debugfs_init_files(struct wil6210_priv *wil,
struct dentry *dbg)
{
int i;
for (i = 0; i < ARRAY_SIZE(dbg_files); i++)
debugfs_create_file(dbg_files[i].name, dbg_files[i].mode, dbg,
wil, dbg_files[i].fops);
}
/* interrupt control blocks */
static const struct {
const char *name;
u32 icr_off;
} dbg_icr[] = {
{"USER_ICR", HOSTADDR(RGF_USER_USER_ICR)},
{"DMA_EP_TX_ICR", HOSTADDR(RGF_DMA_EP_TX_ICR)},
{"DMA_EP_RX_ICR", HOSTADDR(RGF_DMA_EP_RX_ICR)},
{"DMA_EP_MISC_ICR", HOSTADDR(RGF_DMA_EP_MISC_ICR)},
};
static void wil6210_debugfs_init_isr(struct wil6210_priv *wil,
struct dentry *dbg)
{
int i;
for (i = 0; i < ARRAY_SIZE(dbg_icr); i++)
wil6210_debugfs_create_ISR(wil, dbg_icr[i].name, dbg,
dbg_icr[i].icr_off);
}
#define WIL_FIELD(name, mode, type) { __stringify(name), mode, \
offsetof(struct wil6210_priv, name), type}
/* fields in struct wil6210_priv */
static const struct dbg_off dbg_wil_off[] = {
WIL_FIELD(secure_pcp, S_IRUGO | S_IWUSR, doff_u32),
WIL_FIELD(status, S_IRUGO | S_IWUSR, doff_ulong),
WIL_FIELD(fw_version, S_IRUGO, doff_u32),
WIL_FIELD(hw_version, S_IRUGO, doff_x32),
{},
};
static const struct dbg_off dbg_wil_regs[] = {
{"RGF_MAC_MTRL_COUNTER_0", S_IRUGO, HOSTADDR(RGF_MAC_MTRL_COUNTER_0),
doff_io32},
{"RGF_USER_USAGE_1", S_IRUGO, HOSTADDR(RGF_USER_USAGE_1), doff_io32},
{},
};
/* static parameters */
static const struct dbg_off dbg_statics[] = {
{"desc_index", S_IRUGO | S_IWUSR, (ulong)&dbg_txdesc_index, doff_u32},
{"vring_index", S_IRUGO | S_IWUSR, (ulong)&dbg_vring_index, doff_u32},
{"mem_addr", S_IRUGO | S_IWUSR, (ulong)&mem_addr, doff_u32},
{},
};
int wil6210_debugfs_init(struct wil6210_priv *wil)
{
struct dentry *dbg = wil->debug = debugfs_create_dir(WIL_NAME,
@ -993,51 +1200,17 @@ int wil6210_debugfs_init(struct wil6210_priv *wil)
if (IS_ERR_OR_NULL(dbg))
return -ENODEV;
debugfs_create_file("mbox", S_IRUGO, dbg, wil, &fops_mbox);
debugfs_create_file("vrings", S_IRUGO, dbg, wil, &fops_vring);
debugfs_create_file("stations", S_IRUGO, dbg, wil, &fops_sta);
debugfs_create_file("desc", S_IRUGO, dbg, wil, &fops_txdesc);
debugfs_create_u32("desc_index", S_IRUGO | S_IWUSR, dbg,
&dbg_txdesc_index);
debugfs_create_u32("vring_index", S_IRUGO | S_IWUSR, dbg,
&dbg_vring_index);
debugfs_create_file("bf", S_IRUGO, dbg, wil, &fops_bf);
debugfs_create_file("ssid", S_IRUGO | S_IWUSR, dbg, wil, &fops_ssid);
debugfs_create_u32("secure_pcp", S_IRUGO | S_IWUSR, dbg,
&wil->secure_pcp);
wil_debugfs_create_ulong("status", S_IRUGO | S_IWUSR, dbg,
&wil->status);
debugfs_create_u32("fw_version", S_IRUGO, dbg, &wil->fw_version);
debugfs_create_x32("hw_version", S_IRUGO, dbg, &wil->hw_version);
wil6210_debugfs_create_ISR(wil, "USER_ICR", dbg,
HOSTADDR(RGF_USER_USER_ICR));
wil6210_debugfs_create_ISR(wil, "DMA_EP_TX_ICR", dbg,
HOSTADDR(RGF_DMA_EP_TX_ICR));
wil6210_debugfs_create_ISR(wil, "DMA_EP_RX_ICR", dbg,
HOSTADDR(RGF_DMA_EP_RX_ICR));
wil6210_debugfs_create_ISR(wil, "DMA_EP_MISC_ICR", dbg,
HOSTADDR(RGF_DMA_EP_MISC_ICR));
wil6210_debugfs_create_pseudo_ISR(wil, dbg);
wil6210_debugfs_create_ITR_CNT(wil, dbg);
wil_debugfs_create_iomem_x32("RGF_USER_USAGE_1", S_IRUGO, dbg,
wil->csr +
HOSTADDR(RGF_USER_USAGE_1));
debugfs_create_u32("mem_addr", S_IRUGO | S_IWUSR, dbg, &mem_addr);
debugfs_create_file("mem_val", S_IRUGO, dbg, wil, &fops_memread);
debugfs_create_file("reset", S_IWUSR, dbg, wil, &fops_reset);
debugfs_create_file("rxon", S_IWUSR, dbg, wil, &fops_rxon);
debugfs_create_file("tx_mgmt", S_IWUSR, dbg, wil, &fops_txmgmt);
debugfs_create_file("wmi_send", S_IWUSR, dbg, wil, &fops_wmi);
debugfs_create_file("temp", S_IRUGO, dbg, wil, &fops_temp);
debugfs_create_file("freq", S_IRUGO, dbg, wil, &fops_freq);
debugfs_create_file("link", S_IRUGO, dbg, wil, &fops_link);
debugfs_create_file("info", S_IRUGO, dbg, wil, &fops_info);
wil6210_debugfs_init_files(wil, dbg);
wil6210_debugfs_init_isr(wil, dbg);
wil6210_debugfs_init_blobs(wil, dbg);
wil6210_debugfs_init_offset(wil, dbg, wil, dbg_wil_off);
wil6210_debugfs_init_offset(wil, dbg, (void * __force)wil->csr,
dbg_wil_regs);
wil6210_debugfs_init_offset(wil, dbg, NULL, dbg_statics);
wil6210_debugfs_create_pseudo_ISR(wil, dbg);
wil6210_debugfs_create_ITR_CNT(wil, dbg);
return 0;
}

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -25,6 +25,9 @@ static bool no_fw_recovery;
module_param(no_fw_recovery, bool, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(no_fw_recovery, " disable FW error recovery");
#define RST_DELAY (20) /* msec, for loop in @wil_target_reset */
#define RST_COUNT (1 + 1000/RST_DELAY) /* round up to be above 1 sec total */
/*
* Due to a hardware issue,
* one has to read/write to/from NIC in 32-bit chunks;
@ -309,7 +312,7 @@ void wil_priv_deinit(struct wil6210_priv *wil)
destroy_workqueue(wil->wmi_wq);
}
static void wil_target_reset(struct wil6210_priv *wil)
static int wil_target_reset(struct wil6210_priv *wil)
{
int delay = 0;
u32 hw_state;
@ -327,6 +330,8 @@ static void wil_target_reset(struct wil6210_priv *wil)
/* register clear = read, AND with inverted, write */
#define C(a, v) W(a, R(a) & ~v)
wmb(); /* If host reorder writes here -> race in NIC */
W(RGF_USER_MAC_CPU_0, BIT(1)); /* mac_cpu_man_rst */
wil->hw_version = R(RGF_USER_FW_REV_ID);
rev_id = wil->hw_version & 0xff;
@ -343,8 +348,9 @@ static void wil_target_reset(struct wil6210_priv *wil)
wmb(); /* order is important here */
}
W(RGF_USER_MAC_CPU_0, BIT(1)); /* mac_cpu_man_rst */
W(RGF_USER_USER_CPU_0, BIT(1)); /* user_cpu_man_rst */
wmb(); /* If host reorder writes here -> race in NIC */
W(RGF_USER_MAC_CPU_0, BIT(1)); /* mac_cpu_man_rst */
wmb(); /* order is important here */
W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);
@ -385,14 +391,14 @@ static void wil_target_reset(struct wil6210_priv *wil)
W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
wmb(); /* order is important here */
/* wait until device ready */
/* wait until device ready. typical time is 200..250 msec */
do {
msleep(1);
msleep(RST_DELAY);
hw_state = R(RGF_USER_HW_MACHINE_STATE);
if (delay++ > 100) {
if (delay++ > RST_COUNT) {
wil_err(wil, "Reset not completed, hw_state 0x%08x\n",
hw_state);
return;
return -ETIME;
}
} while (hw_state != HW_MACHINE_BOOT_DONE);
@ -403,7 +409,8 @@ static void wil_target_reset(struct wil6210_priv *wil)
C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
wmb(); /* order is important here */
wil_dbg_misc(wil, "Reset completed in %d ms\n", delay);
wil_dbg_misc(wil, "Reset completed in %d ms\n", delay * RST_DELAY);
return 0;
#undef R
#undef W
@ -468,10 +475,11 @@ int wil_reset(struct wil6210_priv *wil)
flush_workqueue(wil->wmi_wq_conn);
flush_workqueue(wil->wmi_wq);
/* TODO: put MAC in reset */
wil_target_reset(wil);
rc = wil_target_reset(wil);
wil_rx_fini(wil);
if (rc)
return rc;
/* init after reset */
wil->pending_connect_cid = -1;

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -168,11 +168,15 @@ void *wil_if_alloc(struct device *dev, void __iomem *csr)
void wil_if_free(struct wil6210_priv *wil)
{
struct net_device *ndev = wil_to_ndev(wil);
if (!ndev)
return;
free_netdev(ndev);
wil_priv_deinit(wil);
wil_to_ndev(wil) = NULL;
free_netdev(ndev);
wil_wdev_free(wil);
}

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -218,12 +218,13 @@ static int wil_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
static void wil_pcie_remove(struct pci_dev *pdev)
{
struct wil6210_priv *wil = pci_get_drvdata(pdev);
void __iomem *csr = wil->csr;
wil6210_debugfs_remove(wil);
wil_if_pcie_disable(wil);
wil_if_remove(wil);
wil_if_free(wil);
pci_iounmap(pdev, wil->csr);
pci_iounmap(pdev, csr);
pci_release_region(pdev, 0);
pci_disable_device(pdev);
}
@ -243,6 +244,8 @@ static const struct pci_device_id wil6210_pcie_ids[] = {
.driver_data = (kernel_ulong_t)&wil_board_marlon },
{ PCI_DEVICE(0x1ae9, 0x0310),
.driver_data = (kernel_ulong_t)&wil_board_sparrow },
{ PCI_DEVICE(0x1ae9, 0x0302), /* same as above, firmware broken */
.driver_data = (kernel_ulong_t)&wil_board_sparrow },
{ /* end: all zeroes */ },
};
MODULE_DEVICE_TABLE(pci, wil6210_pcie_ids);

View File

@ -1,3 +1,19 @@
/*
* Copyright (c) 2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "wil6210.h"
#include "txrx.h"

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -414,7 +414,6 @@ static struct sk_buff *wil_vring_reap_rx(struct wil6210_priv *wil,
cid = wil_rxdesc_cid(d);
stats = &wil->sta[cid].stats;
stats->last_mcs_rx = wil_rxdesc_mcs(d);
wil->stats.last_mcs_rx = stats->last_mcs_rx;
/* use radiotap header only if required */
if (ndev->type == ARPHRD_IEEE80211_RADIOTAP)

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -133,6 +133,9 @@ struct RGF_ICR {
#define RGF_HP_CTRL (0x88265c)
#define RGF_PCIE_LOS_COUNTER_CTL (0x882dc4)
/* MAC timer, usec, for packet lifetime */
#define RGF_MAC_MTRL_COUNTER_0 (0x886aa8)
/* popular locations */
#define HOST_MBOX HOSTADDR(RGF_USER_USER_SCRATCH_PAD)
#define HOST_SW_INT (HOSTADDR(RGF_USER_USER_ICR) + \
@ -327,17 +330,6 @@ struct wil_tid_ampdu_rx {
bool first_time; /* is it 1-st time this buffer used? */
};
struct wil6210_stats {
u64 tsf;
u32 snr;
u16 last_mcs_rx;
u16 bf_mcs; /* last BF, used for Tx */
u16 my_rx_sector;
u16 my_tx_sector;
u16 peer_rx_sector;
u16 peer_tx_sector;
};
enum wil_sta_status {
wil_sta_unused = 0,
wil_sta_conn_pending = 1,
@ -430,7 +422,6 @@ struct wil6210_priv {
struct mutex mutex; /* for wil6210_priv access in wil_{up|down} */
/* statistics */
struct wil6210_stats stats;
atomic_t isr_count_rx, isr_count_tx;
/* debugfs */
struct dentry *debug;

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -14,6 +14,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <linux/moduleparam.h>
#include <linux/etherdevice.h>
#include <linux/if_arp.h>
@ -22,6 +23,10 @@
#include "wmi.h"
#include "trace.h"
static uint max_assoc_sta = 1;
module_param(max_assoc_sta, uint, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(max_assoc_sta, " Max number of stations associated to the AP");
/**
* WMI event receiving - theory of operations
*
@ -346,11 +351,11 @@ static void wmi_evt_rx_mgmt(struct wil6210_priv *wil, int id, void *d, int len)
rx_mgmt_frame->bssid);
cfg80211_put_bss(wiphy, bss);
} else {
wil_err(wil, "cfg80211_inform_bss() failed\n");
wil_err(wil, "cfg80211_inform_bss_frame() failed\n");
}
} else {
cfg80211_rx_mgmt(wil->wdev, freq, signal,
(void *)rx_mgmt_frame, d_len, 0, GFP_KERNEL);
(void *)rx_mgmt_frame, d_len, 0);
}
}
@ -482,33 +487,6 @@ static void wmi_evt_disconnect(struct wil6210_priv *wil, int id,
mutex_unlock(&wil->mutex);
}
static void wmi_evt_notify(struct wil6210_priv *wil, int id, void *d, int len)
{
struct wmi_notify_req_done_event *evt = d;
if (len < sizeof(*evt)) {
wil_err(wil, "Short NOTIFY event\n");
return;
}
wil->stats.tsf = le64_to_cpu(evt->tsf);
wil->stats.snr = le32_to_cpu(evt->snr_val);
wil->stats.bf_mcs = le16_to_cpu(evt->bf_mcs);
wil->stats.my_rx_sector = le16_to_cpu(evt->my_rx_sector);
wil->stats.my_tx_sector = le16_to_cpu(evt->my_tx_sector);
wil->stats.peer_rx_sector = le16_to_cpu(evt->other_rx_sector);
wil->stats.peer_tx_sector = le16_to_cpu(evt->other_tx_sector);
wil_dbg_wmi(wil, "Link status, MCS %d TSF 0x%016llx\n"
"BF status 0x%08x SNR 0x%08x SQI %d%%\n"
"Tx Tpt %d goodput %d Rx goodput %d\n"
"Sectors(rx:tx) my %d:%d peer %d:%d\n",
wil->stats.bf_mcs, wil->stats.tsf, evt->status,
wil->stats.snr, evt->sqi, le32_to_cpu(evt->tx_tpt),
le32_to_cpu(evt->tx_goodput), le32_to_cpu(evt->rx_goodput),
wil->stats.my_rx_sector, wil->stats.my_tx_sector,
wil->stats.peer_rx_sector, wil->stats.peer_tx_sector);
}
/*
* Firmware reports EAPOL frame using WME event.
* Reconstruct Ethernet frame and deliver it via normal Rx
@ -651,7 +629,6 @@ static const struct {
{WMI_SCAN_COMPLETE_EVENTID, wmi_evt_scan_complete},
{WMI_CONNECT_EVENTID, wmi_evt_connect},
{WMI_DISCONNECT_EVENTID, wmi_evt_disconnect},
{WMI_NOTIFY_REQ_DONE_EVENTID, wmi_evt_notify},
{WMI_EAPOL_RX_EVENTID, wmi_evt_eapol_rx},
{WMI_DATA_PORT_OPEN_EVENTID, wmi_evt_linkup},
{WMI_WBE_LINKDOWN_EVENTID, wmi_evt_linkdown},
@ -822,7 +799,7 @@ int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan)
.network_type = wmi_nettype,
.disable_sec_offload = 1,
.channel = chan - 1,
.pcp_max_assoc_sta = WIL6210_MAX_CID,
.pcp_max_assoc_sta = max_assoc_sta,
};
struct {
struct wil6210_mbox_hdr_wmi wmi;
@ -832,6 +809,14 @@ int wmi_pcp_start(struct wil6210_priv *wil, int bi, u8 wmi_nettype, u8 chan)
if (!wil->secure_pcp)
cmd.disable_sec = 1;
if ((cmd.pcp_max_assoc_sta > WIL6210_MAX_CID) ||
(cmd.pcp_max_assoc_sta <= 0)) {
wil_info(wil,
"Requested connection limit %u, valid values are 1 - %d. Setting to %d\n",
max_assoc_sta, WIL6210_MAX_CID, WIL6210_MAX_CID);
cmd.pcp_max_assoc_sta = WIL6210_MAX_CID;
}
/*
* Processing time may be huge, in case of secure AP it takes about
* 3500ms for FW to start AP

View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2012 Qualcomm Atheros, Inc.
* Copyright (c) 2012-2014 Qualcomm Atheros, Inc.
* Copyright (c) 2006-2012 Wilocity .
*
* Permission to use, copy, modify, and/or distribute this software for any
@ -980,7 +980,7 @@ struct wmi_ready_event {
* WMI_NOTIFY_REQ_DONE_EVENTID
*/
struct wmi_notify_req_done_event {
__le32 status;
__le32 status; /* beamforming status, 0: fail; 1: OK; 2: retrying */
__le64 tsf;
__le32 snr_val;
__le32 tx_tpt;

View File

@ -66,18 +66,18 @@ static void atmel_release(struct pcmcia_device *link);
static void atmel_detach(struct pcmcia_device *p_dev);
typedef struct local_info_t {
struct local_info {
struct net_device *eth_dev;
} local_info_t;
};
static int atmel_probe(struct pcmcia_device *p_dev)
{
local_info_t *local;
struct local_info *local;
dev_dbg(&p_dev->dev, "atmel_attach()\n");
/* Allocate space for private device-specific data */
local = kzalloc(sizeof(local_info_t), GFP_KERNEL);
local = kzalloc(sizeof(*local), GFP_KERNEL);
if (!local)
return -ENOMEM;
@ -117,7 +117,7 @@ static int atmel_config_check(struct pcmcia_device *p_dev, void *priv_data)
static int atmel_config(struct pcmcia_device *link)
{
local_info_t *dev;
struct local_info *dev;
int ret;
const struct pcmcia_device_id *did;
@ -141,14 +141,14 @@ static int atmel_config(struct pcmcia_device *link)
if (ret)
goto failed;
((local_info_t*)link->priv)->eth_dev =
((struct local_info *)link->priv)->eth_dev =
init_atmel_card(link->irq,
link->resource[0]->start,
did ? did->driver_info : ATMEL_FW_TYPE_NONE,
&link->dev,
card_present,
link);
if (!((local_info_t*)link->priv)->eth_dev)
if (!((struct local_info *)link->priv)->eth_dev)
goto failed;
@ -161,20 +161,20 @@ static int atmel_config(struct pcmcia_device *link)
static void atmel_release(struct pcmcia_device *link)
{
struct net_device *dev = ((local_info_t*)link->priv)->eth_dev;
struct net_device *dev = ((struct local_info *)link->priv)->eth_dev;
dev_dbg(&link->dev, "atmel_release\n");
if (dev)
stop_atmel_card(dev);
((local_info_t*)link->priv)->eth_dev = NULL;
((struct local_info *)link->priv)->eth_dev = NULL;
pcmcia_disable_device(link);
}
static int atmel_suspend(struct pcmcia_device *link)
{
local_info_t *local = link->priv;
struct local_info *local = link->priv;
netif_device_detach(local->eth_dev);
@ -183,7 +183,7 @@ static int atmel_suspend(struct pcmcia_device *link)
static int atmel_resume(struct pcmcia_device *link)
{
local_info_t *local = link->priv;
struct local_info *local = link->priv;
atmel_open(local->eth_dev);
netif_device_attach(local->eth_dev);

View File

@ -18,6 +18,7 @@ b43-y += xmit.o
b43-y += dma.o
b43-y += pio.o
b43-y += rfkill.o
b43-y += ppr.o
b43-$(CONFIG_B43_LEDS) += leds.o
b43-$(CONFIG_B43_PCMCIA) += pcmcia.o
b43-$(CONFIG_B43_SDIO) += sdio.o

View File

@ -457,6 +457,7 @@ enum {
#define B43_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
#define B43_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
#define B43_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep frames with bad PLCP */
#define B43_MACCTL_PHY_LOCK 0x00200000
#define B43_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
#define B43_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
#define B43_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
@ -791,6 +792,13 @@ struct b43_firmware {
bool pcm_request_failed;
};
enum b43_band {
B43_BAND_2G = 0,
B43_BAND_5G_LO = 1,
B43_BAND_5G_MI = 2,
B43_BAND_5G_HI = 3,
};
/* Device (802.11 core) initialization status. */
enum {
B43_STAT_UNINIT = 0, /* Uninitialized. */
@ -1012,6 +1020,16 @@ static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
dev->dev->write16(dev->dev, offset, value);
}
/* To optimize this check for flush_writes on BCM47XX_BCMA only. */
static inline void b43_write16f(struct b43_wldev *dev, u16 offset, u16 value)
{
b43_write16(dev, offset, value);
#if defined(CONFIG_BCM47XX_BCMA)
if (dev->dev->flush_writes)
b43_read16(dev, offset);
#endif
}
static inline void b43_maskset16(struct b43_wldev *dev, u16 offset, u16 mask,
u16 set)
{

View File

@ -22,6 +22,10 @@
*/
#ifdef CONFIG_BCM47XX_BCMA
#include <asm/mach-bcm47xx/bcm47xx.h>
#endif
#include "b43.h"
#include "bus.h"
@ -102,6 +106,12 @@ struct b43_bus_dev *b43_bus_dev_bcma_init(struct bcma_device *core)
dev->write32 = b43_bus_bcma_write32;
dev->block_read = b43_bus_bcma_block_read;
dev->block_write = b43_bus_bcma_block_write;
#ifdef CONFIG_BCM47XX_BCMA
if (b43_bus_host_is_pci(dev) &&
bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA &&
bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4716)
dev->flush_writes = true;
#endif
dev->dev = &core->dev;
dev->dma_dev = core->dma_dev;

View File

@ -33,6 +33,7 @@ struct b43_bus_dev {
size_t count, u16 offset, u8 reg_width);
void (*block_write)(struct b43_bus_dev *dev, const void *buffer,
size_t count, u16 offset, u8 reg_width);
bool flush_writes;
struct device *dev;
struct device *dma_dev;
@ -60,7 +61,21 @@ static inline bool b43_bus_host_is_pcmcia(struct b43_bus_dev *dev)
#else
return false;
#endif
};
static inline bool b43_bus_host_is_pci(struct b43_bus_dev *dev)
{
#ifdef CONFIG_B43_BCMA
if (dev->bus_type == B43_BUS_BCMA)
return (dev->bdev->bus->hosttype == BCMA_HOSTTYPE_PCI);
#endif
#ifdef CONFIG_B43_SSB
if (dev->bus_type == B43_BUS_SSB)
return (dev->sdev->bus->bustype == SSB_BUSTYPE_PCI);
#endif
return false;
}
static inline bool b43_bus_host_is_sdio(struct b43_bus_dev *dev)
{
#ifdef CONFIG_B43_SSB

View File

@ -4466,10 +4466,10 @@ static int b43_phy_versioning(struct b43_wldev *dev)
if (core_rev == 40 || core_rev == 42) {
radio_manuf = 0x17F;
b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 0);
b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 0);
radio_rev = b43_read16(dev, B43_MMIO_RADIO24_DATA);
b43_write16(dev, B43_MMIO_RADIO24_CONTROL, 1);
b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, 1);
radio_id = b43_read16(dev, B43_MMIO_RADIO24_DATA);
radio_ver = 0; /* Is there version somewhere? */
@ -4477,7 +4477,7 @@ static int b43_phy_versioning(struct b43_wldev *dev)
u16 radio24[3];
for (tmp = 0; tmp < 3; tmp++) {
b43_write16(dev, B43_MMIO_RADIO24_CONTROL, tmp);
b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, tmp);
radio24[tmp] = b43_read16(dev, B43_MMIO_RADIO24_DATA);
}
@ -4494,13 +4494,12 @@ static int b43_phy_versioning(struct b43_wldev *dev)
else
tmp = 0x5205017F;
} else {
b43_write16(dev, B43_MMIO_RADIO_CONTROL,
B43_RADIOCTL_ID);
b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
B43_RADIOCTL_ID);
tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
b43_write16(dev, B43_MMIO_RADIO_CONTROL,
B43_RADIOCTL_ID);
tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH)
<< 16;
b43_write16f(dev, B43_MMIO_RADIO_CONTROL,
B43_RADIOCTL_ID);
tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
}
radio_manuf = (tmp & 0x00000FFF);
radio_id = (tmp & 0x0FFFF000) >> 12;

View File

@ -444,14 +444,14 @@ static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)
static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)
{
reg = adjust_phyreg(dev, reg);
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
return b43_read16(dev, B43_MMIO_PHY_DATA);
}
static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
reg = adjust_phyreg(dev, reg);
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA, value);
}

View File

@ -222,12 +222,18 @@ static inline void assert_mac_suspended(struct b43_wldev *dev)
u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
{
assert_mac_suspended(dev);
dev->phy.writes_counter = 0;
return dev->phy.ops->radio_read(dev, reg);
}
void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
{
assert_mac_suspended(dev);
if (b43_bus_host_is_pci(dev->dev) &&
++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
b43_read32(dev, B43_MMIO_MACCTL);
dev->phy.writes_counter = 1;
}
dev->phy.ops->radio_write(dev, reg, value);
}
@ -268,17 +274,28 @@ u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
{
assert_mac_suspended(dev);
dev->phy.writes_counter = 0;
return dev->phy.ops->phy_read(dev, reg);
if (dev->phy.ops->phy_read)
return dev->phy.ops->phy_read(dev, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
return b43_read16(dev, B43_MMIO_PHY_DATA);
}
void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
{
assert_mac_suspended(dev);
dev->phy.ops->phy_write(dev, reg, value);
if (++dev->phy.writes_counter == B43_MAX_WRITES_IN_ROW) {
if (b43_bus_host_is_pci(dev->dev) &&
++dev->phy.writes_counter > B43_MAX_WRITES_IN_ROW) {
b43_read16(dev, B43_MMIO_PHY_VER);
dev->phy.writes_counter = 0;
dev->phy.writes_counter = 1;
}
if (dev->phy.ops->phy_write)
return dev->phy.ops->phy_write(dev, reg, value);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA, value);
}
void b43_phy_copy(struct b43_wldev *dev, u16 destreg, u16 srcreg)

View File

@ -2555,13 +2555,13 @@ static void b43_gphy_op_exit(struct b43_wldev *dev)
static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
return b43_read16(dev, B43_MMIO_PHY_DATA);
}
static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA, value);
}
@ -2572,7 +2572,7 @@ static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
/* G-PHY needs 0x80 for read access. */
reg |= 0x80;
b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
}
@ -2581,7 +2581,7 @@ static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
/* Register 1 is a 32-bit register. */
B43_WARN_ON(reg == 1);
b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
}

View File

@ -1071,22 +1071,10 @@ static unsigned int b43_phy_ht_op_get_default_chan(struct b43_wldev *dev)
* R/W ops.
**************************************************/
static u16 b43_phy_ht_op_read(struct b43_wldev *dev, u16 reg)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
return b43_read16(dev, B43_MMIO_PHY_DATA);
}
static void b43_phy_ht_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA, value);
}
static void b43_phy_ht_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
u16 set)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA,
(b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
}
@ -1096,14 +1084,14 @@ static u16 b43_phy_ht_op_radio_read(struct b43_wldev *dev, u16 reg)
/* HT-PHY needs 0x200 for read access */
reg |= 0x200;
b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);
return b43_read16(dev, B43_MMIO_RADIO24_DATA);
}
static void b43_phy_ht_op_radio_write(struct b43_wldev *dev, u16 reg,
u16 value)
{
b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);
b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
}
@ -1126,8 +1114,6 @@ const struct b43_phy_operations b43_phyops_ht = {
.free = b43_phy_ht_op_free,
.prepare_structs = b43_phy_ht_op_prepare_structs,
.init = b43_phy_ht_op_init,
.phy_read = b43_phy_ht_op_read,
.phy_write = b43_phy_ht_op_write,
.phy_maskset = b43_phy_ht_op_maskset,
.radio_read = b43_phy_ht_op_radio_read,
.radio_write = b43_phy_ht_op_radio_write,

View File

@ -810,22 +810,10 @@ static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
* R/W ops.
**************************************************/
static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
return b43_read16(dev, B43_MMIO_PHY_DATA);
}
static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA, value);
}
static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
u16 set)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA,
(b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
}
@ -835,14 +823,14 @@ static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
/* LCN-PHY needs 0x200 for read access */
reg |= 0x200;
b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);
return b43_read16(dev, B43_MMIO_RADIO24_DATA);
}
static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
u16 value)
{
b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO24_CONTROL, reg);
b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
}
@ -855,8 +843,6 @@ const struct b43_phy_operations b43_phyops_lcn = {
.free = b43_phy_lcn_op_free,
.prepare_structs = b43_phy_lcn_op_prepare_structs,
.init = b43_phy_lcn_op_init,
.phy_read = b43_phy_lcn_op_read,
.phy_write = b43_phy_lcn_op_write,
.phy_maskset = b43_phy_lcn_op_maskset,
.radio_read = b43_phy_lcn_op_radio_read,
.radio_write = b43_phy_lcn_op_radio_write,

View File

@ -1985,22 +1985,10 @@ static void lpphy_calibration(struct b43_wldev *dev)
b43_mac_enable(dev);
}
static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
return b43_read16(dev, B43_MMIO_PHY_DATA);
}
static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA, value);
}
static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
u16 set)
{
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA,
(b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
}
@ -2016,7 +2004,7 @@ static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
} else
reg |= 0x200;
b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
}
@ -2025,7 +2013,7 @@ static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
/* Register 1 is a 32-bit register. */
B43_WARN_ON(reg == 1);
b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
}
@ -2713,8 +2701,6 @@ const struct b43_phy_operations b43_phyops_lp = {
.free = b43_lpphy_op_free,
.prepare_structs = b43_lpphy_op_prepare_structs,
.init = b43_lpphy_op_init,
.phy_read = b43_lpphy_op_read,
.phy_write = b43_lpphy_op_write,
.phy_maskset = b43_lpphy_op_maskset,
.radio_read = b43_lpphy_op_radio_read,
.radio_write = b43_lpphy_op_radio_write,

View File

@ -34,6 +34,7 @@
#include "radio_2056.h"
#include "radio_2057.h"
#include "main.h"
#include "ppr.h"
struct nphy_txgains {
u16 tx_lpf[2];
@ -3606,16 +3607,6 @@ static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
* Tx and Rx
**************************************************/
static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
{//TODO
}
static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
bool ignore_tssi)
{//TODO
return B43_TXPWR_RES_DONE;
}
/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */
static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
{
@ -4069,6 +4060,7 @@ static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
s16 a1[2], b0[2], b1[2];
u8 idle[2];
u8 ppr_max;
s8 target[2];
s32 num, den, pwr;
u32 regval[64];
@ -4147,7 +4139,12 @@ static void b43_nphy_tx_power_ctl_setup(struct b43_wldev *dev)
b1[0] = b1[1] = -1393;
}
}
/* target[0] = target[1] = nphy->tx_power_max; */
ppr_max = b43_ppr_get_max(dev, &nphy->tx_pwr_max_ppr);
if (ppr_max) {
target[0] = ppr_max;
target[1] = ppr_max;
}
if (dev->phy.rev >= 3) {
if (sprom->fem.ghz2.tssipos)
@ -4235,8 +4232,9 @@ static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
const u32 *table = NULL;
u32 rfpwr_offset;
u8 pga_gain;
u8 pga_gain, pad_gain;
int i;
const s16 *uninitialized_var(rf_pwr_offset_table);
table = b43_nphy_get_tx_gain_table(dev);
if (!table)
@ -4252,13 +4250,27 @@ static void b43_nphy_tx_gain_table_upload(struct b43_wldev *dev)
nphy->gmval = (table[0] >> 16) & 0x7000;
#endif
if (phy->rev >= 19) {
return;
} else if (phy->rev >= 7) {
rf_pwr_offset_table = b43_ntab_get_rf_pwr_offset_table(dev);
if (!rf_pwr_offset_table)
return;
/* TODO: Enable this once we have gains configured */
return;
}
for (i = 0; i < 128; i++) {
if (phy->rev >= 19) {
/* TODO */
return;
} else if (phy->rev >= 7) {
/* TODO */
return;
pga_gain = (table[i] >> 24) & 0xf;
pad_gain = (table[i] >> 19) & 0x1f;
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
rfpwr_offset = rf_pwr_offset_table[pad_gain];
else
rfpwr_offset = rf_pwr_offset_table[pga_gain];
} else {
pga_gain = (table[i] >> 24) & 0xF;
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
@ -5874,6 +5886,69 @@ static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
b43_mac_enable(dev);
}
static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
bool ignore_tssi)
{
struct b43_phy *phy = &dev->phy;
struct b43_phy_n *nphy = dev->phy.n;
struct ieee80211_channel *channel = dev->wl->hw->conf.chandef.chan;
struct b43_ppr *ppr = &nphy->tx_pwr_max_ppr;
u8 max; /* qdBm */
bool tx_pwr_state;
if (nphy->tx_pwr_last_recalc_freq == channel->center_freq &&
nphy->tx_pwr_last_recalc_limit == phy->desired_txpower)
return B43_TXPWR_RES_DONE;
/* Make sure we have a clean PPR */
b43_ppr_clear(dev, ppr);
/* HW limitations */
b43_ppr_load_max_from_sprom(dev, ppr, B43_BAND_2G);
/* Regulatory & user settings */
max = INT_TO_Q52(phy->chandef->chan->max_power);
if (phy->desired_txpower)
max = min_t(u8, max, INT_TO_Q52(phy->desired_txpower));
b43_ppr_apply_max(dev, ppr, max);
if (b43_debug(dev, B43_DBG_XMITPOWER))
b43dbg(dev->wl, "Calculated TX power: " Q52_FMT "\n",
Q52_ARG(b43_ppr_get_max(dev, ppr)));
/* TODO: Enable this once we get gains working */
#if 0
/* Some extra gains */
hw_gain = 6; /* N-PHY specific */
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
hw_gain += sprom->antenna_gain.a0;
else
hw_gain += sprom->antenna_gain.a1;
b43_ppr_add(dev, ppr, -hw_gain);
#endif
/* Make sure we didn't go too low */
b43_ppr_apply_min(dev, ppr, INT_TO_Q52(8));
/* Apply */
tx_pwr_state = nphy->txpwrctrl;
b43_mac_suspend(dev);
b43_nphy_tx_power_ctl_setup(dev);
if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12) {
b43_maskset32(dev, B43_MMIO_MACCTL, ~0, B43_MACCTL_PHY_LOCK);
b43_read32(dev, B43_MMIO_MACCTL);
udelay(1);
}
b43_nphy_tx_power_ctrl(dev, nphy->txpwrctrl);
if (dev->dev->core_rev == 11 || dev->dev->core_rev == 12)
b43_maskset32(dev, B43_MMIO_MACCTL, ~B43_MACCTL_PHY_LOCK, 0);
b43_mac_enable(dev);
nphy->tx_pwr_last_recalc_freq = channel->center_freq;
nphy->tx_pwr_last_recalc_limit = phy->desired_txpower;
return B43_TXPWR_RES_DONE;
}
/**************************************************
* N-PHY init
**************************************************/
@ -6407,6 +6482,7 @@ static int b43_nphy_op_allocate(struct b43_wldev *dev)
nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
if (!nphy)
return -ENOMEM;
dev->phy.n = nphy;
return 0;
@ -6497,26 +6573,13 @@ static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
#endif /* B43_DEBUG */
}
static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
{
check_phyreg(dev, reg);
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
return b43_read16(dev, B43_MMIO_PHY_DATA);
}
static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
{
check_phyreg(dev, reg);
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16(dev, B43_MMIO_PHY_DATA, value);
}
static void b43_nphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
u16 set)
{
check_phyreg(dev, reg);
b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
b43_write16f(dev, B43_MMIO_PHY_CONTROL, reg);
b43_maskset16(dev, B43_MMIO_PHY_DATA, mask, set);
dev->phy.writes_counter = 1;
}
static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
@ -6529,7 +6592,7 @@ static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
else
reg |= 0x100;
b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
}
@ -6538,7 +6601,7 @@ static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
/* Register 1 is a 32-bit register. */
B43_WARN_ON(dev->phy.rev < 7 && reg == 1);
b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16f(dev, B43_MMIO_RADIO_CONTROL, reg);
b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
}
@ -6652,8 +6715,6 @@ const struct b43_phy_operations b43_phyops_n = {
.free = b43_nphy_op_free,
.prepare_structs = b43_nphy_op_prepare_structs,
.init = b43_nphy_op_init,
.phy_read = b43_nphy_op_read,
.phy_write = b43_nphy_op_write,
.phy_maskset = b43_nphy_op_maskset,
.radio_read = b43_nphy_op_radio_read,
.radio_write = b43_nphy_op_radio_write,
@ -6662,5 +6723,4 @@ const struct b43_phy_operations b43_phyops_n = {
.switch_channel = b43_nphy_op_switch_channel,
.get_default_chan = b43_nphy_op_get_default_chan,
.recalc_txpower = b43_nphy_op_recalc_txpower,
.adjust_txpower = b43_nphy_op_adjust_txpower,
};

View File

@ -2,6 +2,7 @@
#define B43_NPHY_H_
#include "phy_common.h"
#include "ppr.h"
/* N-PHY registers. */
@ -967,6 +968,9 @@ struct b43_phy_n {
struct b43_phy_n_txpwrindex txpwrindex[2];
struct b43_phy_n_pwr_ctl_info pwr_ctl_info[2];
struct b43_chanspec txiqlocal_chanspec;
struct b43_ppr tx_pwr_max_ppr;
u16 tx_pwr_last_recalc_freq;
int tx_pwr_last_recalc_limit;
u8 txrx_chain;
u16 tx_rx_cal_phy_saveregs[11];

View File

@ -0,0 +1,199 @@
/*
* Broadcom B43 wireless driver
* PPR (Power Per Rate) management
*
* Copyright (c) 2014 Rafał Miłecki <zajec5@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "ppr.h"
#include "b43.h"
#define ppr_for_each_entry(ppr, i, entry) \
for (i = 0, entry = &(ppr)->__all_rates[i]; \
i < B43_PPR_RATES_NUM; \
i++, entry++)
void b43_ppr_clear(struct b43_wldev *dev, struct b43_ppr *ppr)
{
memset(ppr, 0, sizeof(*ppr));
/* Compile-time PPR check */
BUILD_BUG_ON(sizeof(struct b43_ppr) != B43_PPR_RATES_NUM * sizeof(u8));
}
void b43_ppr_add(struct b43_wldev *dev, struct b43_ppr *ppr, int diff)
{
int i;
u8 *rate;
ppr_for_each_entry(ppr, i, rate) {
*rate = clamp_val(*rate + diff, 0, 127);
}
}
void b43_ppr_apply_max(struct b43_wldev *dev, struct b43_ppr *ppr, u8 max)
{
int i;
u8 *rate;
ppr_for_each_entry(ppr, i, rate) {
*rate = min(*rate, max);
}
}
void b43_ppr_apply_min(struct b43_wldev *dev, struct b43_ppr *ppr, u8 min)
{
int i;
u8 *rate;
ppr_for_each_entry(ppr, i, rate) {
*rate = max(*rate, min);
}
}
u8 b43_ppr_get_max(struct b43_wldev *dev, struct b43_ppr *ppr)
{
u8 res = 0;
int i;
u8 *rate;
ppr_for_each_entry(ppr, i, rate) {
res = max(*rate, res);
}
return res;
}
bool b43_ppr_load_max_from_sprom(struct b43_wldev *dev, struct b43_ppr *ppr,
enum b43_band band)
{
struct b43_ppr_rates *rates = &ppr->rates;
struct ssb_sprom *sprom = dev->dev->bus_sprom;
struct b43_phy *phy = &dev->phy;
u8 maxpwr, off;
u32 sprom_ofdm_po;
u16 *sprom_mcs_po;
u8 extra_cdd_po, extra_stbc_po;
int i;
switch (band) {
case B43_BAND_2G:
maxpwr = min(sprom->core_pwr_info[0].maxpwr_2g,
sprom->core_pwr_info[1].maxpwr_2g);
sprom_ofdm_po = sprom->ofdm2gpo;
sprom_mcs_po = sprom->mcs2gpo;
extra_cdd_po = (sprom->cddpo >> 0) & 0xf;
extra_stbc_po = (sprom->stbcpo >> 0) & 0xf;
break;
case B43_BAND_5G_LO:
maxpwr = min(sprom->core_pwr_info[0].maxpwr_5gl,
sprom->core_pwr_info[1].maxpwr_5gl);
sprom_ofdm_po = sprom->ofdm5glpo;
sprom_mcs_po = sprom->mcs5glpo;
extra_cdd_po = (sprom->cddpo >> 8) & 0xf;
extra_stbc_po = (sprom->stbcpo >> 8) & 0xf;
break;
case B43_BAND_5G_MI:
maxpwr = min(sprom->core_pwr_info[0].maxpwr_5g,
sprom->core_pwr_info[1].maxpwr_5g);
sprom_ofdm_po = sprom->ofdm5gpo;
sprom_mcs_po = sprom->mcs5gpo;
extra_cdd_po = (sprom->cddpo >> 4) & 0xf;
extra_stbc_po = (sprom->stbcpo >> 4) & 0xf;
break;
case B43_BAND_5G_HI:
maxpwr = min(sprom->core_pwr_info[0].maxpwr_5gh,
sprom->core_pwr_info[1].maxpwr_5gh);
sprom_ofdm_po = sprom->ofdm5ghpo;
sprom_mcs_po = sprom->mcs5ghpo;
extra_cdd_po = (sprom->cddpo >> 12) & 0xf;
extra_stbc_po = (sprom->stbcpo >> 12) & 0xf;
break;
default:
WARN_ON_ONCE(1);
return false;
}
if (band == B43_BAND_2G) {
for (i = 0; i < 4; i++) {
off = ((sprom->cck2gpo >> (i * 4)) & 0xf) * 2;
rates->cck[i] = maxpwr - off;
}
}
/* OFDM */
for (i = 0; i < 8; i++) {
off = ((sprom_ofdm_po >> (i * 4)) & 0xf) * 2;
rates->ofdm[i] = maxpwr - off;
}
/* MCS 20 SISO */
rates->mcs_20[0] = rates->ofdm[0];
rates->mcs_20[1] = rates->ofdm[2];
rates->mcs_20[2] = rates->ofdm[3];
rates->mcs_20[3] = rates->ofdm[4];
rates->mcs_20[4] = rates->ofdm[5];
rates->mcs_20[5] = rates->ofdm[6];
rates->mcs_20[6] = rates->ofdm[7];
rates->mcs_20[7] = rates->ofdm[7];
/* MCS 20 CDD */
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_cdd[i] = maxpwr - off;
if (phy->type == B43_PHYTYPE_N && phy->rev >= 3)
rates->mcs_20_cdd[i] -= extra_cdd_po;
}
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_cdd[4 + i] = maxpwr - off;
if (phy->type == B43_PHYTYPE_N && phy->rev >= 3)
rates->mcs_20_cdd[4 + i] -= extra_cdd_po;
}
/* OFDM 20 CDD */
rates->ofdm_20_cdd[0] = rates->mcs_20_cdd[0];
rates->ofdm_20_cdd[1] = rates->mcs_20_cdd[0];
rates->ofdm_20_cdd[2] = rates->mcs_20_cdd[1];
rates->ofdm_20_cdd[3] = rates->mcs_20_cdd[2];
rates->ofdm_20_cdd[4] = rates->mcs_20_cdd[3];
rates->ofdm_20_cdd[5] = rates->mcs_20_cdd[4];
rates->ofdm_20_cdd[6] = rates->mcs_20_cdd[5];
rates->ofdm_20_cdd[7] = rates->mcs_20_cdd[6];
/* MCS 20 STBC */
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_stbc[i] = maxpwr - off;
if (phy->type == B43_PHYTYPE_N && phy->rev >= 3)
rates->mcs_20_stbc[i] -= extra_stbc_po;
}
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_stbc[4 + i] = maxpwr - off;
if (phy->type == B43_PHYTYPE_N && phy->rev >= 3)
rates->mcs_20_stbc[4 + i] -= extra_stbc_po;
}
/* MCS 20 SDM */
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[2] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_sdm[i] = maxpwr - off;
}
for (i = 0; i < 4; i++) {
off = ((sprom_mcs_po[3] >> (i * 4)) & 0xf) * 2;
rates->mcs_20_sdm[4 + i] = maxpwr - off;
}
return true;
}

View File

@ -0,0 +1,45 @@
#ifndef LINUX_B43_PPR_H_
#define LINUX_B43_PPR_H_
#include <linux/types.h>
#define B43_PPR_CCK_RATES_NUM 4
#define B43_PPR_OFDM_RATES_NUM 8
#define B43_PPR_MCS_RATES_NUM 8
#define B43_PPR_RATES_NUM (B43_PPR_CCK_RATES_NUM + \
B43_PPR_OFDM_RATES_NUM * 2 + \
B43_PPR_MCS_RATES_NUM * 4)
struct b43_ppr_rates {
u8 cck[B43_PPR_CCK_RATES_NUM];
u8 ofdm[B43_PPR_OFDM_RATES_NUM];
u8 ofdm_20_cdd[B43_PPR_OFDM_RATES_NUM];
u8 mcs_20[B43_PPR_MCS_RATES_NUM]; /* SISO */
u8 mcs_20_cdd[B43_PPR_MCS_RATES_NUM];
u8 mcs_20_stbc[B43_PPR_MCS_RATES_NUM];
u8 mcs_20_sdm[B43_PPR_MCS_RATES_NUM];
};
struct b43_ppr {
/* All powers are in qdbm (Q5.2) */
union {
u8 __all_rates[B43_PPR_RATES_NUM];
struct b43_ppr_rates rates;
};
};
struct b43_wldev;
enum b43_band;
void b43_ppr_clear(struct b43_wldev *dev, struct b43_ppr *ppr);
void b43_ppr_add(struct b43_wldev *dev, struct b43_ppr *ppr, int diff);
void b43_ppr_apply_max(struct b43_wldev *dev, struct b43_ppr *ppr, u8 max);
void b43_ppr_apply_min(struct b43_wldev *dev, struct b43_ppr *ppr, u8 min);
u8 b43_ppr_get_max(struct b43_wldev *dev, struct b43_ppr *ppr);
bool b43_ppr_load_max_from_sprom(struct b43_wldev *dev, struct b43_ppr *ppr,
enum b43_band band);
#endif /* LINUX_B43_PPR_H_ */

View File

@ -2878,6 +2878,40 @@ const s8 b43_ntab_papd_pga_gain_delta_ipa_2g[] = {
-54, -46, -39, -31, -23, -15, -8, 0
};
/* Extracted from MMIO dump of 6.30.223.248
* Entries: 0, 15, 17, 21, 24, 26, 27, 29, 30 were guessed
*/
static const s16 b43_ntab_rf_pwr_offset_2057_rev9_2g[] = {
-133, -133, -107, -92, -81,
-73, -66, -61, -56, -52,
-48, -44, -41, -37, -34,
-31, -28, -25, -22, -19,
-17, -14, -12, -10, -9,
-7, -5, -4, -3, -2,
-1, 0,
};
/* Extracted from MMIO dump of 6.30.223.248 */
static const s16 b43_ntab_rf_pwr_offset_2057_rev9_5g[] = {
-101, -94, -86, -79, -72,
-65, -57, -50, -42, -35,
-28, -21, -16, -9, -4,
0,
};
/* Extracted from MMIO dump of 6.30.223.248
* Entries: 0, 26, 28, 29, 30, 31 were guessed
*/
static const s16 b43_ntab_rf_pwr_offset_2057_rev14_2g[] = {
-111, -111, -111, -84, -70,
-59, -52, -45, -40, -36,
-32, -29, -26, -23, -21,
-18, -16, -15, -13, -11,
-10, -8, -7, -6, -5,
-4, -4, -3, -3, -2,
-2, -1,
};
const u16 tbl_iqcal_gainparams[2][9][8] = {
{
{ 0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69 },
@ -3197,7 +3231,7 @@ static struct nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = {
{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
0x527E, /* invalid for external LNA! */
{ 0x513F, 0x513F, 0x513F, 0x513F }, /* invalid for external LNA! */
0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */
0x007E, 0x0066, 0x0000, /* low is invalid (the last one) */
0x18, 0x18, 0x18,
0x01D0, 0x5,
},
@ -3708,9 +3742,43 @@ const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev)
}
}
const s16 *b43_ntab_get_rf_pwr_offset_table(struct b43_wldev *dev)
{
struct b43_phy *phy = &dev->phy;
if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
switch (phy->rev) {
case 17:
if (phy->radio_rev == 14)
return b43_ntab_rf_pwr_offset_2057_rev14_2g;
break;
case 16:
if (phy->radio_rev == 9)
return b43_ntab_rf_pwr_offset_2057_rev9_2g;
break;
}
b43err(dev->wl,
"No 2GHz RF power table available for this device\n");
return NULL;
} else {
switch (phy->rev) {
case 16:
if (phy->radio_rev == 9)
return b43_ntab_rf_pwr_offset_2057_rev9_5g;
break;
}
b43err(dev->wl,
"No 5GHz RF power table available for this device\n");
return NULL;
}
}
struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
struct b43_wldev *dev, bool ghz5, bool ext_lna)
{
struct b43_phy *phy = &dev->phy;
struct nphy_gain_ctl_workaround_entry *e;
u8 phy_idx;
@ -3729,37 +3797,49 @@ struct nphy_gain_ctl_workaround_entry *b43_nphy_get_gain_ctl_workaround_ent(
e = &nphy_gain_ctl_workaround[ghz5][phy_idx];
/* Some workarounds to the workarounds... */
if (ghz5 && dev->phy.rev >= 6) {
if (dev->phy.radio_rev == 11 &&
!b43_is_40mhz(dev))
e->cliplo_gain = 0x2d;
} else if (!ghz5 && dev->phy.rev >= 5) {
static const int gain_data[] = {0x0062, 0x0064, 0x006a, 0x106a,
0x106c, 0x1074, 0x107c, 0x207c};
if (!ghz5) {
u8 tr_iso = dev->dev->bus_sprom->fem.ghz2.tr_iso;
if (ext_lna) {
if (tr_iso > 7)
tr_iso = 3;
if (phy->rev >= 6) {
static const int gain_data[] = { 0x106a, 0x106c, 0x1074,
0x107c, 0x007e, 0x107e,
0x207e, 0x307e, };
e->cliplo_gain = gain_data[tr_iso];
} else if (phy->rev == 5) {
static const int gain_data[] = { 0x0062, 0x0064, 0x006a,
0x106a, 0x106c, 0x1074,
0x107c, 0x207c, };
e->cliplo_gain = gain_data[tr_iso];
}
if (phy->rev >= 5 && ext_lna) {
e->rfseq_init[0] &= ~0x4000;
e->rfseq_init[1] &= ~0x4000;
e->rfseq_init[2] &= ~0x4000;
e->rfseq_init[3] &= ~0x4000;
e->init_gain &= ~0x4000;
}
if (tr_iso > 7)
tr_iso = 3;
e->cliplo_gain = gain_data[tr_iso];
} else if (ghz5 && dev->phy.rev == 4 && ext_lna) {
e->rfseq_init[0] &= ~0x4000;
e->rfseq_init[1] &= ~0x4000;
e->rfseq_init[2] &= ~0x4000;
e->rfseq_init[3] &= ~0x4000;
e->init_gain &= ~0x4000;
e->rfseq_init[0] |= 0x1000;
e->rfseq_init[1] |= 0x1000;
e->rfseq_init[2] |= 0x1000;
e->rfseq_init[3] |= 0x1000;
e->init_gain |= 0x1000;
} else {
if (phy->rev >= 6) {
if (phy->radio_rev == 11 && !b43_is_40mhz(dev))
e->crsminu = 0x2d;
} else if (phy->rev == 4 && ext_lna) {
e->rfseq_init[0] &= ~0x4000;
e->rfseq_init[1] &= ~0x4000;
e->rfseq_init[2] &= ~0x4000;
e->rfseq_init[3] &= ~0x4000;
e->init_gain &= ~0x4000;
e->rfseq_init[0] |= 0x1000;
e->rfseq_init[1] |= 0x1000;
e->rfseq_init[2] |= 0x1000;
e->rfseq_init[3] |= 0x1000;
e->init_gain |= 0x1000;
}
}
return e;

View File

@ -191,6 +191,8 @@ void b43_nphy_tables_init(struct b43_wldev *dev);
const u32 *b43_nphy_get_tx_gain_table(struct b43_wldev *dev);
const s16 *b43_ntab_get_rf_pwr_offset_table(struct b43_wldev *dev);
extern const s8 b43_ntab_papd_pga_gain_delta_ipa_2g[];
extern const u16 tbl_iqcal_gainparams[2][9][8];

View File

@ -1431,8 +1431,7 @@ int brcmf_p2p_notify_action_frame_rx(struct brcmf_if *ifp,
IEEE80211_BAND_5GHZ);
wdev = &ifp->vif->wdev;
cfg80211_rx_mgmt(wdev, freq, 0, (u8 *)mgmt_frame, mgmt_frame_len, 0,
GFP_ATOMIC);
cfg80211_rx_mgmt(wdev, freq, 0, (u8 *)mgmt_frame, mgmt_frame_len, 0);
kfree(mgmt_frame);
return 0;
@ -1896,8 +1895,7 @@ s32 brcmf_p2p_notify_rx_mgmt_p2p_probereq(struct brcmf_if *ifp,
IEEE80211_BAND_2GHZ :
IEEE80211_BAND_5GHZ);
cfg80211_rx_mgmt(&vif->wdev, freq, 0, mgmt_frame, mgmt_frame_len, 0,
GFP_ATOMIC);
cfg80211_rx_mgmt(&vif->wdev, freq, 0, mgmt_frame, mgmt_frame_len, 0);
brcmf_dbg(INFO, "mgmt_frame_len (%d) , e->datalen (%d), chanspec (%04x), freq (%d)\n",
mgmt_frame_len, e->datalen, chanspec, freq);

View File

@ -2394,9 +2394,13 @@ static s32 brcmf_inform_single_bss(struct brcmf_cfg80211_info *cfg,
brcmf_dbg(CONN, "Beacon interval: %d\n", notify_interval);
brcmf_dbg(CONN, "Signal: %d\n", notify_signal);
bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)bi->BSSID,
0, notify_capability, notify_interval, notify_ie,
notify_ielen, notify_signal, GFP_KERNEL);
bss = cfg80211_inform_bss(wiphy, notify_channel,
CFG80211_BSS_FTYPE_UNKNOWN,
(const u8 *)bi->BSSID,
0, notify_capability,
notify_interval, notify_ie,
notify_ielen, notify_signal,
GFP_KERNEL);
if (!bss)
return -ENOMEM;
@ -2498,9 +2502,11 @@ static s32 wl_inform_ibss(struct brcmf_cfg80211_info *cfg,
brcmf_dbg(CONN, "beacon interval: %d\n", notify_interval);
brcmf_dbg(CONN, "signal: %d\n", notify_signal);
bss = cfg80211_inform_bss(wiphy, notify_channel, bssid,
0, notify_capability, notify_interval,
notify_ie, notify_ielen, notify_signal, GFP_KERNEL);
bss = cfg80211_inform_bss(wiphy, notify_channel,
CFG80211_BSS_FTYPE_UNKNOWN, bssid, 0,
notify_capability, notify_interval,
notify_ie, notify_ielen, notify_signal,
GFP_KERNEL);
if (!bss) {
err = -ENOMEM;

View File

@ -398,7 +398,7 @@ static int cw1200_spi_probe(struct spi_device *func)
return -1;
}
self = kzalloc(sizeof(*self), GFP_KERNEL);
self = devm_kzalloc(&func->dev, sizeof(*self), GFP_KERNEL);
if (!self) {
pr_err("Can't allocate SPI hwbus_priv.");
return -ENOMEM;
@ -424,7 +424,6 @@ static int cw1200_spi_probe(struct spi_device *func)
if (status) {
cw1200_spi_irq_unsubscribe(self);
cw1200_spi_off(plat_data);
kfree(self);
}
return status;
@ -441,7 +440,6 @@ static int cw1200_spi_disconnect(struct spi_device *func)
cw1200_core_release(self->core);
self->core = NULL;
}
kfree(self);
}
cw1200_spi_off(dev_get_platdata(&func->dev));

View File

@ -5552,7 +5552,7 @@ static int ipw_find_adhoc_network(struct ipw_priv *priv,
min(network->ssid_len, priv->essid_len)))) {
char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
strncpy(escaped,
strlcpy(escaped,
print_ssid(ssid, network->ssid,
network->ssid_len),
sizeof(escaped));
@ -5765,7 +5765,7 @@ static int ipw_best_network(struct ipw_priv *priv,
memcmp(network->ssid, priv->essid,
min(network->ssid_len, priv->essid_len)))) {
char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
strncpy(escaped,
strlcpy(escaped,
print_ssid(ssid, network->ssid,
network->ssid_len),
sizeof(escaped));
@ -5782,7 +5782,7 @@ static int ipw_best_network(struct ipw_priv *priv,
* testing everything else. */
if (match->network && match->network->stats.rssi > network->stats.rssi) {
char escaped[IW_ESSID_MAX_SIZE * 2 + 1];
strncpy(escaped,
strlcpy(escaped,
print_ssid(ssid, network->ssid, network->ssid_len),
sizeof(escaped));
IPW_DEBUG_ASSOC("Network '%s (%pM)' excluded because "

View File

@ -85,6 +85,16 @@ config IWLWIFI_BCAST_FILTERING
If unsure, don't enable this option, as some programs might
expect incoming broadcasts for their normal operations.
config IWLWIFI_UAPSD
bool "enable U-APSD by default"
depends on IWLMVM
help
Say Y here to enable U-APSD by default. This may cause
interoperability problems with some APs, manifesting in lower than
expected throughput due to those APs not enabling aggregation
If unsure, say N.
menu "Debugging Options"
config IWLWIFI_DEBUG

View File

@ -580,7 +580,7 @@ turn_off:
* time, or we hadn't time to drain the AC queues.
*/
if (agg_state == IWL_AGG_ON)
iwl_trans_txq_disable(priv->trans, txq_id);
iwl_trans_txq_disable(priv->trans, txq_id, true);
else
IWL_DEBUG_TX_QUEUES(priv, "Don't disable tx agg: %d\n",
agg_state);
@ -686,7 +686,7 @@ int iwlagn_tx_agg_flush(struct iwl_priv *priv, struct ieee80211_vif *vif,
* time, or we hadn't time to drain the AC queues.
*/
if (agg_state == IWL_AGG_ON)
iwl_trans_txq_disable(priv->trans, txq_id);
iwl_trans_txq_disable(priv->trans, txq_id, true);
else
IWL_DEBUG_TX_QUEUES(priv, "Don't disable tx agg: %d\n",
agg_state);
@ -781,7 +781,7 @@ static void iwlagn_check_ratid_empty(struct iwl_priv *priv, int sta_id, u8 tid)
"Can continue DELBA flow ssn = next_recl = %d\n",
tid_data->next_reclaimed);
iwl_trans_txq_disable(priv->trans,
tid_data->agg.txq_id);
tid_data->agg.txq_id, true);
iwlagn_dealloc_agg_txq(priv, tid_data->agg.txq_id);
tid_data->agg.state = IWL_AGG_OFF;
ieee80211_stop_tx_ba_cb_irqsafe(vif, addr, tid);

View File

@ -6,6 +6,7 @@
* GPL LICENSE SUMMARY
*
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -31,6 +32,7 @@
* BSD LICENSE
*
* Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,6 +6,7 @@
* GPL LICENSE SUMMARY
*
* Copyright(c) 2014 Intel Corporation. All rights reserved.
* Copyright(c) 2014 Intel Mobile Communications GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -31,6 +32,7 @@
* BSD LICENSE
*
* Copyright(c) 2014 Intel Corporation. All rights reserved.
* Copyright(c) 2014 Intel Mobile Communications GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -6,6 +6,7 @@
* GPL LICENSE SUMMARY
*
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of version 2 of the GNU General Public License as
@ -31,6 +32,7 @@
* BSD LICENSE
*
* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
* Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

View File

@ -145,6 +145,7 @@ do { \
#define IWL_DL_HCMD 0x00000004
#define IWL_DL_STATE 0x00000008
/* 0x000000F0 - 0x00000010 */
#define IWL_DL_QUOTA 0x00000010
#define IWL_DL_TE 0x00000020
#define IWL_DL_EEPROM 0x00000040
#define IWL_DL_RADIO 0x00000080
@ -189,6 +190,7 @@ do { \
#define IWL_DEBUG_LED(p, f, a...) IWL_DEBUG(p, IWL_DL_LED, f, ## a)
#define IWL_DEBUG_WEP(p, f, a...) IWL_DEBUG(p, IWL_DL_WEP, f, ## a)
#define IWL_DEBUG_HC(p, f, a...) IWL_DEBUG(p, IWL_DL_HCMD, f, ## a)
#define IWL_DEBUG_QUOTA(p, f, a...) IWL_DEBUG(p, IWL_DL_QUOTA, f, ## a)
#define IWL_DEBUG_TE(p, f, a...) IWL_DEBUG(p, IWL_DL_TE, f, ## a)
#define IWL_DEBUG_EEPROM(d, f, a...) IWL_DEBUG_DEV(d, IWL_DL_EEPROM, f, ## a)
#define IWL_DEBUG_CALIB(p, f, a...) IWL_DEBUG(p, IWL_DL_CALIB, f, ## a)

Some files were not shown because too many files have changed in this diff Show More