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crypto: tegra-aes - bitwise vs logical and
The bug here is that: while (eng_busy & (!icq_empty) & dma_busy) is never true because it's using bitwise instead of logical ANDs. The other bitwise AND conditions work as intended but I changed them as well for consistency. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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1 changed files with 3 additions and 3 deletions
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@ -275,7 +275,7 @@ static int aes_start_crypt(struct tegra_aes_dev *dd, u32 in_addr, u32 out_addr,
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value = aes_readl(dd, TEGRA_AES_INTR_STATUS);
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eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD;
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icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD;
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} while (eng_busy & (!icq_empty));
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} while (eng_busy && !icq_empty);
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aes_writel(dd, cmdq[i], TEGRA_AES_ICMDQUE_WR);
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}
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@ -365,7 +365,7 @@ static int aes_set_key(struct tegra_aes_dev *dd)
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eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD;
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icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD;
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dma_busy = value & TEGRA_AES_DMA_BUSY_FIELD;
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} while (eng_busy & (!icq_empty) & dma_busy);
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} while (eng_busy && !icq_empty && dma_busy);
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/* settable command to get key into internal registers */
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value = CMD_SETTABLE << CMDQ_OPCODE_SHIFT |
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@ -379,7 +379,7 @@ static int aes_set_key(struct tegra_aes_dev *dd)
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value = aes_readl(dd, TEGRA_AES_INTR_STATUS);
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eng_busy = value & TEGRA_AES_ENGINE_BUSY_FIELD;
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icq_empty = value & TEGRA_AES_ICQ_EMPTY_FIELD;
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} while (eng_busy & (!icq_empty));
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} while (eng_busy && !icq_empty);
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return 0;
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}
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