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Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM regions. Any code that attempted to use these would wrongly crash due to a CPLB miss. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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1 changed files with 17 additions and 6 deletions
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@ -72,13 +72,24 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
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}
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/* Cover L1 memory. One 4M area for code and data each is enough. */
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if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
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d_tbl[i_d].addr = L1_DATA_A_START;
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d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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if (cpu == 0) {
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if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
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d_tbl[i_d].addr = L1_DATA_A_START;
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d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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}
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i_tbl[i_i].addr = L1_CODE_START;
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i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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}
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i_tbl[i_i].addr = L1_CODE_START;
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i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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#ifdef CONFIG_SMP
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else {
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if (L1_DATA_A_LENGTH || L1_DATA_B_LENGTH) {
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d_tbl[i_d].addr = COREB_L1_DATA_A_START;
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d_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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}
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i_tbl[i_i].addr = COREB_L1_CODE_START;
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i_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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}
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#endif
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first_switched_dcplb = i_d;
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first_switched_icplb = i_i;
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