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x86/entry: Fix assumptions that the HW TSS is at the beginning of cpu_tss
commit 7fb983b4dd
upstream.
A future patch will move SYSENTER_stack to the beginning of cpu_tss
to help detect overflow. Before this can happen, fix several code
paths that hardcode assumptions about the old layout.
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Dave Hansen <dave.hansen@intel.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Borislav Petkov <bpetkov@suse.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: David Laight <David.Laight@aculab.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Eduardo Valentin <eduval@amazon.com>
Cc: Greg KH <gregkh@linuxfoundation.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Juergen Gross <jgross@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rik van Riel <riel@redhat.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: aliguori@amazon.com
Cc: daniel.gruss@iaik.tugraz.at
Cc: hughd@google.com
Cc: keescook@google.com
Link: https://lkml.kernel.org/r/20171204150605.722425540@linutronix.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
487f3ddcd9
commit
5be136953f
6 changed files with 35 additions and 31 deletions
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@ -178,7 +178,7 @@ static inline void set_tssldt_descriptor(void *d, unsigned long addr,
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#endif
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}
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static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
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static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr)
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{
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struct desc_struct *d = get_cpu_gdt_rw(cpu);
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tss_desc tss;
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@ -162,7 +162,7 @@ enum cpuid_regs_idx {
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extern struct cpuinfo_x86 boot_cpu_data;
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extern struct cpuinfo_x86 new_cpu_data;
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extern struct tss_struct doublefault_tss;
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extern struct x86_hw_tss doublefault_tss;
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extern __u32 cpu_caps_cleared[NCAPINTS];
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extern __u32 cpu_caps_set[NCAPINTS];
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@ -252,6 +252,11 @@ static inline void load_cr3(pgd_t *pgdir)
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write_cr3(__sme_pa(pgdir));
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}
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/*
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* Note that while the legacy 'TSS' name comes from 'Task State Segment',
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* on modern x86 CPUs the TSS also holds information important to 64-bit mode,
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* unrelated to the task-switch mechanism:
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*/
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#ifdef CONFIG_X86_32
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/* This is the TSS defined by the hardware. */
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struct x86_hw_tss {
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@ -322,7 +327,7 @@ struct x86_hw_tss {
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#define IO_BITMAP_BITS 65536
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#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
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#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
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#define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
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#define IO_BITMAP_OFFSET (offsetof(struct tss_struct, io_bitmap) - offsetof(struct tss_struct, x86_tss))
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#define INVALID_IO_BITMAP_OFFSET 0x8000
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struct tss_struct {
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@ -1557,7 +1557,7 @@ void cpu_init(void)
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}
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}
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t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
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t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
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/*
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* <= is required because the CPU will access up to
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@ -1576,7 +1576,7 @@ void cpu_init(void)
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* Initialize the TSS. Don't bother initializing sp0, as the initial
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* task never enters user mode.
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*/
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set_tss_desc(cpu, t);
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set_tss_desc(cpu, &t->x86_tss);
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load_TR_desc();
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load_mm_ldt(&init_mm);
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@ -1634,12 +1634,12 @@ void cpu_init(void)
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* Initialize the TSS. Don't bother initializing sp0, as the initial
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* task never enters user mode.
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*/
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set_tss_desc(cpu, t);
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set_tss_desc(cpu, &t->x86_tss);
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load_TR_desc();
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load_mm_ldt(&init_mm);
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t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
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t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;
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#ifdef CONFIG_DOUBLEFAULT
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/* Set up doublefault TSS pointer in the GDT */
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@ -50,25 +50,23 @@ static void doublefault_fn(void)
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cpu_relax();
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}
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struct tss_struct doublefault_tss __cacheline_aligned = {
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.x86_tss = {
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.sp0 = STACK_START,
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.ss0 = __KERNEL_DS,
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.ldt = 0,
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.io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
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struct x86_hw_tss doublefault_tss __cacheline_aligned = {
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.sp0 = STACK_START,
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.ss0 = __KERNEL_DS,
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.ldt = 0,
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.io_bitmap_base = INVALID_IO_BITMAP_OFFSET,
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.ip = (unsigned long) doublefault_fn,
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/* 0x2 bit is always set */
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.flags = X86_EFLAGS_SF | 0x2,
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.sp = STACK_START,
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.es = __USER_DS,
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.cs = __KERNEL_CS,
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.ss = __KERNEL_DS,
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.ds = __USER_DS,
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.fs = __KERNEL_PERCPU,
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.ip = (unsigned long) doublefault_fn,
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/* 0x2 bit is always set */
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.flags = X86_EFLAGS_SF | 0x2,
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.sp = STACK_START,
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.es = __USER_DS,
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.cs = __KERNEL_CS,
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.ss = __KERNEL_DS,
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.ds = __USER_DS,
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.fs = __KERNEL_PERCPU,
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.__cr3 = __pa_nodebug(swapper_pg_dir),
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}
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.__cr3 = __pa_nodebug(swapper_pg_dir),
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};
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/* dummy for do_double_fault() call */
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@ -2295,7 +2295,7 @@ static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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* processors. See 22.2.4.
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*/
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vmcs_writel(HOST_TR_BASE,
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(unsigned long)this_cpu_ptr(&cpu_tss));
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(unsigned long)this_cpu_ptr(&cpu_tss.x86_tss));
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vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
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/*
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@ -165,12 +165,13 @@ static void fix_processor_context(void)
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struct desc_struct *desc = get_cpu_gdt_rw(cpu);
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tss_desc tss;
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#endif
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set_tss_desc(cpu, t); /*
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* This just modifies memory; should not be
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* necessary. But... This is necessary, because
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* 386 hardware has concept of busy TSS or some
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* similar stupidity.
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*/
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/*
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* This just modifies memory; should not be necessary. But... This is
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* necessary, because 386 hardware has concept of busy TSS or some
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* similar stupidity.
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*/
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set_tss_desc(cpu, &t->x86_tss);
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#ifdef CONFIG_X86_64
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memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
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