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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ARM: ixp4xx: Delete the Arcom Vulcan boardfiles
This board is replaced with the corresponding device tree. Cc: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
73907f98d9
commit
5be86f6886
4 changed files with 0 additions and 362 deletions
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@ -116,14 +116,6 @@ config MACH_FSG
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FSG-3 device. For more information on this platform,
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see http://www.nslu2-linux.org/wiki/FSG3/HomePage
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config MACH_ARCOM_VULCAN
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bool
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prompt "Arcom/Eurotech Vulcan"
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depends on IXP4XX_PCI_LEGACY
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help
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Say 'Y' here if you want your kernel to support Arcom's
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Vulcan board.
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#
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# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
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#
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@ -16,7 +16,6 @@ obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
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obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
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obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
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obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
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obj-pci-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-pci.o
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obj-y += common.o
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@ -28,6 +27,5 @@ obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
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obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
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obj-$(CONFIG_MACH_FSG) += fsg-setup.o
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obj-$(CONFIG_MACH_GORAMO_MLR) += goramo_mlr.o
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obj-$(CONFIG_MACH_ARCOM_VULCAN) += vulcan-setup.o
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obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
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@ -1,70 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arch/mach-ixp4xx/vulcan-pci.c
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*
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* Vulcan board-level PCI initialization
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*
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* Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
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*
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* based on ixdp425-pci.c:
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* Copyright (C) 2002 Intel Corporation.
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include "irqs.h"
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/* PCI controller GPIO to IRQ pin mappings */
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#define INTA 2
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#define INTB 3
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void __init vulcan_pci_preinit(void)
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{
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#ifndef CONFIG_IXP4XX_INDIRECT_PCI
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/*
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* Cardbus bridge wants way more than the SoC can actually offer,
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* and leaves the whole PCI bus in a mess. Artificially limit it
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* to 8MB per region. Of course indirect mode doesn't have this
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* limitation...
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*/
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pci_cardbus_mem_size = SZ_8M;
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pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
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(int)(pci_cardbus_mem_size >> 20));
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#endif
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
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ixp4xx_pci_preinit();
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}
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static int __init vulcan_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (slot == 1)
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return IXP4XX_GPIO_IRQ(INTA);
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if (slot == 2)
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return IXP4XX_GPIO_IRQ(INTB);
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return -1;
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}
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struct hw_pci vulcan_pci __initdata = {
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.nr_controllers = 1,
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.ops = &ixp4xx_ops,
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.preinit = vulcan_pci_preinit,
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.setup = ixp4xx_setup,
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.map_irq = vulcan_map_irq,
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};
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int __init vulcan_pci_init(void)
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{
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if (machine_is_arcom_vulcan())
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pci_common_init(&vulcan_pci);
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return 0;
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}
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subsys_initcall(vulcan_pci_init);
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@ -1,282 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/arm/mach-ixp4xx/vulcan-setup.c
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*
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* Arcom/Eurotech Vulcan board-setup
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*
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* Copyright (C) 2010 Marc Zyngier <maz@misterjones.org>
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*
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* based on fsg-setup.c:
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* Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
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*/
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#include <linux/if_ether.h>
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#include <linux/irq.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#include <linux/io.h>
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#include <linux/w1-gpio.h>
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#include <linux/gpio/machine.h>
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#include <linux/mtd/plat-ram.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include "irqs.h"
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static struct flash_platform_data vulcan_flash_data = {
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.map_name = "cfi_probe",
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.width = 2,
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};
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static struct resource vulcan_flash_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device vulcan_flash = {
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.name = "IXP4XX-Flash",
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.id = 0,
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.dev = {
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.platform_data = &vulcan_flash_data,
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},
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.resource = &vulcan_flash_resource,
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.num_resources = 1,
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};
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static struct platdata_mtd_ram vulcan_sram_data = {
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.mapname = "Vulcan SRAM",
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.bankwidth = 1,
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};
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static struct resource vulcan_sram_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device vulcan_sram = {
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.name = "mtd-ram",
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.id = 0,
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.dev = {
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.platform_data = &vulcan_sram_data,
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},
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.resource = &vulcan_sram_resource,
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.num_resources = 1,
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};
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static struct resource vulcan_uart_resources[] = {
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[0] = {
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.start = IXP4XX_UART1_BASE_PHYS,
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.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IXP4XX_UART2_BASE_PHYS,
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.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.flags = IORESOURCE_MEM,
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},
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};
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static struct plat_serial8250_port vulcan_uart_data[] = {
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[0] = {
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.mapbase = IXP4XX_UART1_BASE_PHYS,
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.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
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.irq = IRQ_IXP4XX_UART1,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = IXP4XX_UART_XTAL,
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},
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[1] = {
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.mapbase = IXP4XX_UART2_BASE_PHYS,
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.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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.irq = IRQ_IXP4XX_UART2,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = IXP4XX_UART_XTAL,
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},
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[2] = {
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.irq = IXP4XX_GPIO_IRQ(4),
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.irqflags = IRQF_TRIGGER_LOW,
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.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.uartclk = 1843200,
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},
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[3] = {
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.irq = IXP4XX_GPIO_IRQ(4),
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.irqflags = IRQF_TRIGGER_LOW,
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.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.uartclk = 1843200,
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},
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{ }
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};
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static struct platform_device vulcan_uart = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = vulcan_uart_data,
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},
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.resource = vulcan_uart_resources,
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.num_resources = ARRAY_SIZE(vulcan_uart_resources),
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};
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static struct resource vulcan_npeb_resources[] = {
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{
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.start = IXP4XX_EthB_BASE_PHYS,
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.end = IXP4XX_EthB_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource vulcan_npec_resources[] = {
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{
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.start = IXP4XX_EthC_BASE_PHYS,
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.end = IXP4XX_EthC_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct eth_plat_info vulcan_plat_eth[] = {
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[0] = {
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.phy = 0,
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.rxq = 3,
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.txreadyq = 20,
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},
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[1] = {
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.phy = 1,
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.rxq = 4,
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.txreadyq = 21,
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},
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};
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static struct platform_device vulcan_eth[] = {
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[0] = {
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.name = "ixp4xx_eth",
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.id = IXP4XX_ETH_NPEB,
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.dev = {
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.platform_data = &vulcan_plat_eth[0],
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},
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.num_resources = ARRAY_SIZE(vulcan_npeb_resources),
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.resource = vulcan_npeb_resources,
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},
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[1] = {
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.name = "ixp4xx_eth",
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.id = IXP4XX_ETH_NPEC,
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.dev = {
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.platform_data = &vulcan_plat_eth[1],
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},
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.num_resources = ARRAY_SIZE(vulcan_npec_resources),
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.resource = vulcan_npec_resources,
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},
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};
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static struct resource vulcan_max6369_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device vulcan_max6369 = {
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.name = "max6369_wdt",
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.id = -1,
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.resource = &vulcan_max6369_resource,
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.num_resources = 1,
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};
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static struct gpiod_lookup_table vulcan_w1_gpiod_table = {
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.dev_id = "w1-gpio",
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.table = {
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GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", 14, NULL, 0,
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GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
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},
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};
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static struct w1_gpio_platform_data vulcan_w1_gpio_pdata = {
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/* Intentionally left blank */
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};
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static struct platform_device vulcan_w1_gpio = {
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.name = "w1-gpio",
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.id = 0,
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.dev = {
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.platform_data = &vulcan_w1_gpio_pdata,
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},
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};
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static struct platform_device *vulcan_devices[] __initdata = {
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&vulcan_uart,
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&vulcan_flash,
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&vulcan_sram,
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&vulcan_max6369,
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&vulcan_eth[0],
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&vulcan_eth[1],
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&vulcan_w1_gpio,
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};
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static void __init vulcan_init(void)
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{
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ixp4xx_sys_init();
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/* Flash is spread over both CS0 and CS1 */
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vulcan_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
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vulcan_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
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*IXP4XX_EXP_CS0 = IXP4XX_EXP_BUS_CS_EN |
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IXP4XX_EXP_BUS_STROBE_T(3) |
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IXP4XX_EXP_BUS_SIZE(0xF) |
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IXP4XX_EXP_BUS_BYTE_RD16 |
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IXP4XX_EXP_BUS_WR_EN;
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*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
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/* SRAM on CS2, (256kB, 8bit, writable) */
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vulcan_sram_resource.start = IXP4XX_EXP_BUS_BASE(2);
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vulcan_sram_resource.end = IXP4XX_EXP_BUS_BASE(2) + SZ_256K - 1;
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*IXP4XX_EXP_CS2 = IXP4XX_EXP_BUS_CS_EN |
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IXP4XX_EXP_BUS_STROBE_T(1) |
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IXP4XX_EXP_BUS_HOLD_T(2) |
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IXP4XX_EXP_BUS_SIZE(9) |
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IXP4XX_EXP_BUS_SPLT_EN |
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IXP4XX_EXP_BUS_WR_EN |
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IXP4XX_EXP_BUS_BYTE_EN;
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/* XR16L2551 on CS3 (Moto style, 512 bytes, 8bits, writable) */
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vulcan_uart_resources[2].start = IXP4XX_EXP_BUS_BASE(3);
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vulcan_uart_resources[2].end = IXP4XX_EXP_BUS_BASE(3) + 16 - 1;
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vulcan_uart_data[2].mapbase = vulcan_uart_resources[2].start;
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vulcan_uart_data[3].mapbase = vulcan_uart_data[2].mapbase + 8;
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*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
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IXP4XX_EXP_BUS_STROBE_T(3) |
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IXP4XX_EXP_BUS_CYCLES(IXP4XX_EXP_BUS_CYCLES_MOTOROLA)|
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IXP4XX_EXP_BUS_WR_EN |
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IXP4XX_EXP_BUS_BYTE_EN;
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/* GPIOS on CS4 (512 bytes, 8bits, writable) */
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*IXP4XX_EXP_CS4 = IXP4XX_EXP_BUS_CS_EN |
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IXP4XX_EXP_BUS_WR_EN |
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IXP4XX_EXP_BUS_BYTE_EN;
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/* max6369 on CS5 (512 bytes, 8bits, writable) */
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vulcan_max6369_resource.start = IXP4XX_EXP_BUS_BASE(5);
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vulcan_max6369_resource.end = IXP4XX_EXP_BUS_BASE(5);
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*IXP4XX_EXP_CS5 = IXP4XX_EXP_BUS_CS_EN |
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IXP4XX_EXP_BUS_WR_EN |
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IXP4XX_EXP_BUS_BYTE_EN;
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gpiod_add_lookup_table(&vulcan_w1_gpiod_table);
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platform_add_devices(vulcan_devices, ARRAY_SIZE(vulcan_devices));
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}
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MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
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/* Maintainer: Marc Zyngier <maz@misterjones.org> */
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.map_io = ixp4xx_map_io,
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.init_early = ixp4xx_init_early,
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.init_irq = ixp4xx_init_irq,
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.init_time = ixp4xx_timer_init,
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.atag_offset = 0x100,
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.init_machine = vulcan_init,
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#if defined(CONFIG_PCI)
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.dma_zone_size = SZ_64M,
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#endif
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.restart = ixp4xx_restart,
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MACHINE_END
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