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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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arm64: dts: ipq6018: Add a few device nodes
add i2c, spi, crypto, rng, watchdog, peripheral nodes, also add support for wcss Q6 remoteproc driver and enable hw mutex, smem, mailbox, smp2p and rpmsg drivers Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Link: https://lore.kernel.org/r/1582199446-29890-1-git-send-email-sivaprak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Sivaprakash Murugesan
Bjorn Andersson
parent
058bd0a689
commit
5bf6356212
2 changed files with 260 additions and 0 deletions
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@ -28,3 +28,37 @@ &blsp1_uart3 {
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pinctrl-names = "default";
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status = "ok";
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};
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&i2c_1 {
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pinctrl-0 = <&i2c_1_pins>;
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pinctrl-names = "default";
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status = "ok";
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};
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&spi_0 {
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cs-select = <0>;
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status = "ok";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "n25q128a11";
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spi-max-frequency = <50000000>;
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};
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};
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&tlmm {
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i2c_1_pins: i2c-1-pins {
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pins = "gpio42", "gpio43";
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function = "blsp2_i2c";
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drive-strength = <8>;
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};
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spi_0_pins: spi-0-pins {
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pins = "gpio38", "gpio39", "gpio40", "gpio41";
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function = "blsp0_spi";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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@ -7,6 +7,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
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#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
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/ {
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#address-cells = <2>;
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@ -69,6 +70,18 @@ L2_0: l2-cache {
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};
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};
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firmware {
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scm {
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compatible = "qcom,scm";
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};
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};
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tcsr_mutex: hwlock {
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compatible = "qcom,tcsr-mutex";
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syscon = <&tcsr_mutex_regs 0 0x80>;
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#hwlock-cells = <1>;
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};
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pmuv8: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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@ -89,6 +102,22 @@ tz: tz@48500000 {
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reg = <0x0 0x48500000 0x0 0x00200000>;
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no-map;
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};
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smem_region: memory@4aa00000 {
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reg = <0x0 0x4aa00000 0x0 0x00100000>;
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no-map;
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};
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q6_region: memory@4ab00000 {
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reg = <0x0 0x4ab00000 0x0 0x02800000>;
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no-map;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_region>;
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hwlocks = <&tcsr_mutex 0>;
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};
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soc: soc {
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@ -98,6 +127,36 @@ soc: soc {
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dma-ranges;
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compatible = "simple-bus";
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prng: qrng@e1000 {
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compatible = "qcom,prng-ee";
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reg = <0xe3000 0x1000>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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};
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cryptobam: dma@704000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x00704000 0x20000>;
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interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <1>;
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qcom,controlled-remotely = <1>;
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qcom,config-pipe-trust-reg = <0>;
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};
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crypto: crypto@73a000 {
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compatible = "qcom,crypto-v5.1";
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reg = <0x0073a000 0x6000>;
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clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
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<&gcc GCC_CRYPTO_AXI_CLK>,
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<&gcc GCC_CRYPTO_CLK>;
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clock-names = "iface", "bus", "core";
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dmas = <&cryptobam 2>, <&cryptobam 3>;
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dma-names = "rx", "tx";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq6018-pinctrl";
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reg = <0x01000000 0x300000>;
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@ -125,6 +184,26 @@ gcc: gcc@1800000 {
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#reset-cells = <1>;
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};
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tcsr_mutex_regs: syscon@1905000 {
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compatible = "syscon";
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reg = <0x01905000 0x8000>;
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};
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tcsr_q6: syscon@1945000 {
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compatible = "syscon";
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reg = <0x01945000 0xe000>;
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};
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blsp_dma: dma@7884000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x07884000 0x2b000>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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};
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blsp1_uart3: serial@78b1000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x078b1000 0x200>;
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@ -135,6 +214,66 @@ blsp1_uart3: serial@78b1000 {
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status = "disabled";
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};
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spi_0: spi@78b5000 {
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b5000 0x600>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 12>, <&blsp_dma 13>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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spi_1: spi@78b6000 {
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compatible = "qcom,spi-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b6000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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spi-max-frequency = <50000000>;
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clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
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<&gcc GCC_BLSP1_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp_dma 14>, <&blsp_dma 15>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2c_0: i2c@78b6000 {
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b6000 0x600>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <400000>;
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dmas = <&blsp_dma 15>, <&blsp_dma 14>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
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compatible = "qcom,i2c-qup-v2.2.1";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x078b7000 0x600>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP1_AHB_CLK>,
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<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
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clock-names = "iface", "core";
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clock-frequency = <400000>;
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dmas = <&blsp_dma 17>, <&blsp_dma 16>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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intc: interrupt-controller@b000000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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@ -146,6 +285,21 @@ intc: interrupt-controller@b000000 {
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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watchdog@b017000 {
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compatible = "qcom,kpss-wdt";
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
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reg = <0x0b017000 0x40>;
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clocks = <&sleep_clk>;
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timeout-sec = <10>;
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};
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apcs_glb: mailbox@b111000 {
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compatible = "qcom,ipq8074-apcs-apps-global";
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reg = <0x0b111000 0xc>;
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#mbox-cells = <1>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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@ -213,5 +367,77 @@ frame@b128000 {
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};
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};
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q6v5_wcss: remoteproc@cd00000 {
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compatible = "qcom,ipq8074-wcss-pil";
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reg = <0x0cd00000 0x4040>,
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<0x004ab000 0x20>;
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reg-names = "qdsp6",
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"rmb";
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interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
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<&wcss_smp2p_in 0 0>,
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<&wcss_smp2p_in 1 0>,
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<&wcss_smp2p_in 2 0>,
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<&wcss_smp2p_in 3 0>;
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interrupt-names = "wdog",
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"fatal",
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"ready",
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"handover",
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"stop-ack";
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resets = <&gcc GCC_WCSSAON_RESET>,
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<&gcc GCC_WCSS_BCR>,
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<&gcc GCC_WCSS_Q6_BCR>;
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reset-names = "wcss_aon_reset",
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"wcss_reset",
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"wcss_q6_reset";
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "prng";
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qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
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qcom,smem-states = <&wcss_smp2p_out 0>,
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<&wcss_smp2p_out 1>;
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qcom,smem-state-names = "shutdown",
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"stop";
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memory-region = <&q6_region>;
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glink-edge {
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interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
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qcom,remote-pid = <1>;
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mboxes = <&apcs_glb 8>;
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qrtr_requests {
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qcom,glink-channels = "IPCRTR";
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};
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};
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};
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};
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wcss: wcss-smp2p {
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compatible = "qcom,smp2p";
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qcom,smem = <435>, <428>;
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;
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mboxes = <&apcs_glb 9>;
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qcom,local-pid = <0>;
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qcom,remote-pid = <1>;
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wcss_smp2p_out: master-kernel {
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qcom,entry-name = "master-kernel";
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#qcom,smem-state-cells = <1>;
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};
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wcss_smp2p_in: slave-kernel {
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qcom,entry-name = "slave-kernel";
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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};
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