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Merge branch 'pci/controller/qcom'
- Disable register write access after init for IP v2.3.3, v2.9.0 (Manivannan Sadhasivam) - Use DWC helpers for enabling/disabling writes to DBI registers (Manivannan Sadhasivam) - Hide slot hotplug capability for IP v1.0.0, v1.9.0, v2.1.0, v2.3.2, v2.3.3, v2.7.0, v2.9.0 (Manivannan Sadhasivam) - Reuse v2.3.2 post-init sequence for v2.4.0 (Manivannan Sadhasivam) - * pci/controller/qcom: PCI: qcom: Do not advertise hotplug capability for IP v2.1.0 PCI: qcom: Do not advertise hotplug capability for IP v1.0.0 PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 PCI: qcom: Do not advertise hotplug capability for IP v2.3.2 PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0 PCI: qcom: Do not advertise hotplug capability for IPs v2.7.0 and v1.9.0 PCI: qcom: Disable write access to read only registers for IP v2.9.0 PCI: qcom: Use DWC helpers for modifying the read-only DBI registers PCI: qcom: Disable write access to read only registers for IP v2.3.3
This commit is contained in:
Bjorn Helgaas
commit
5c13b3c19a
1 changed files with 38 additions and 35 deletions
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@ -61,7 +61,6 @@
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/* DBI registers */
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#define AXI_MSTR_RESP_COMP_CTRL0 0x818
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#define AXI_MSTR_RESP_COMP_CTRL1 0x81c
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#define MISC_CONTROL_1_REG 0x8bc
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/* MHI registers */
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#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
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@ -132,9 +131,6 @@
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/* AXI_MSTR_RESP_COMP_CTRL1 register fields */
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#define CFG_BRIDGE_SB_INIT BIT(0)
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/* MISC_CONTROL_1_REG register fields */
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#define DBI_RO_WR_EN 1
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/* PCI_EXP_SLTCAP register fields */
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#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
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#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
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@ -144,7 +140,6 @@
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PCI_EXP_SLTCAP_AIP | \
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PCI_EXP_SLTCAP_PIP | \
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PCI_EXP_SLTCAP_HPS | \
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PCI_EXP_SLTCAP_HPC | \
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PCI_EXP_SLTCAP_EIP | \
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PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
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PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
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@ -274,6 +269,20 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
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return 0;
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}
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static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
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{
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u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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u32 val;
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dw_pcie_dbi_ro_wr_en(pci);
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val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
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val &= ~PCI_EXP_SLTCAP_HPC;
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writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
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dw_pcie_dbi_ro_wr_dis(pci);
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}
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static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
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{
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u32 val;
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@ -429,6 +438,8 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
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writel(CFG_BRIDGE_SB_INIT,
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pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
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qcom_pcie_clear_hpc(pcie->pci);
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return 0;
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}
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@ -512,6 +523,8 @@ static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
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writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
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}
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qcom_pcie_clear_hpc(pcie->pci);
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return 0;
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}
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@ -607,6 +620,8 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
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val |= EN;
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writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
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qcom_pcie_clear_hpc(pcie->pci);
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return 0;
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}
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@ -692,34 +707,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
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return 0;
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}
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static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie)
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{
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u32 val;
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/* enable PCIe clocks and resets */
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val = readl(pcie->parf + PARF_PHY_CTRL);
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val &= ~PHY_TEST_PWR_DOWN;
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writel(val, pcie->parf + PARF_PHY_CTRL);
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/* change DBI base address */
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writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
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/* MAC PHY_POWERDOWN MUX DISABLE */
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val = readl(pcie->parf + PARF_SYS_CTRL);
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val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
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writel(val, pcie->parf + PARF_SYS_CTRL);
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val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
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val |= BYPASS;
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writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
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val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
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val |= EN;
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writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
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return 0;
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}
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static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
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@ -826,7 +813,9 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
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writel(0, pcie->parf + PARF_Q2A_FLUSH);
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writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
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writel(DBI_RO_WR_EN, pci->dbi_base + MISC_CONTROL_1_REG);
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dw_pcie_dbi_ro_wr_en(pci);
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writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
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val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
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@ -836,6 +825,8 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
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writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
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PCI_EXP_DEVCTL2);
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dw_pcie_dbi_ro_wr_dis(pci);
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return 0;
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}
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@ -966,6 +957,13 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
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return ret;
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}
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static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
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{
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qcom_pcie_clear_hpc(pcie->pci);
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return 0;
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}
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static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
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{
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struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
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@ -1136,6 +1134,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
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writel(0, pcie->parf + PARF_Q2A_FLUSH);
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dw_pcie_dbi_ro_wr_en(pci);
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writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
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val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
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@ -1145,6 +1144,8 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
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writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
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PCI_EXP_DEVCTL2);
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dw_pcie_dbi_ro_wr_dis(pci);
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for (i = 0; i < 256; i++)
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writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
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@ -1251,7 +1252,7 @@ static const struct qcom_pcie_ops ops_2_3_2 = {
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static const struct qcom_pcie_ops ops_2_4_0 = {
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.get_resources = qcom_pcie_get_resources_2_4_0,
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.init = qcom_pcie_init_2_4_0,
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.post_init = qcom_pcie_post_init_2_4_0,
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.post_init = qcom_pcie_post_init_2_3_2,
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.deinit = qcom_pcie_deinit_2_4_0,
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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};
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@ -1269,6 +1270,7 @@ static const struct qcom_pcie_ops ops_2_3_3 = {
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static const struct qcom_pcie_ops ops_2_7_0 = {
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.get_resources = qcom_pcie_get_resources_2_7_0,
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.init = qcom_pcie_init_2_7_0,
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.post_init = qcom_pcie_post_init_2_7_0,
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.deinit = qcom_pcie_deinit_2_7_0,
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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};
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@ -1277,6 +1279,7 @@ static const struct qcom_pcie_ops ops_2_7_0 = {
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static const struct qcom_pcie_ops ops_1_9_0 = {
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.get_resources = qcom_pcie_get_resources_2_7_0,
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.init = qcom_pcie_init_2_7_0,
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.post_init = qcom_pcie_post_init_2_7_0,
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.deinit = qcom_pcie_deinit_2_7_0,
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.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
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.config_sid = qcom_pcie_config_sid_1_9_0,
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