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synced 2024-08-26 02:39:48 +00:00
[SCSI] qla4xxx: Fix MBOX intr switching from polling to intr mode for ISP83XX
Issue: Mailbox command timed out after switching from polling mode to interrupt mode. Events:- 1. Mailbox interrupts are disabled 2. FW generates AEN and at same time driver enables Mailbox Interrupt 3. Driver issues new mailbox to Firmware In above case driver will not get AEN interrupts generated by FW in step #2 as FW generated this AEN when interrupts are disabled. During the same time driver enabled the mailbox interrupt, so driver will not poll for interrupt. Driver will never process AENs generated in step #2 and issues new mailbox to FW, but now FW is not able to post mailbox completion as AENs generated before are not processed by driver. Fix: Enable Mailbox / AEN interrupts before initializing FW in case of ISP83XX. This will make sure we process all Mailbox and AENs in interrupt mode. Signed-off-by: Vikas Chaudhary <vikas.chaudhary@qlogic.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
parent
8108de9739
commit
5c19b92ae8
8 changed files with 105 additions and 45 deletions
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@ -1351,31 +1351,58 @@ int qla4_83xx_start_firmware(struct scsi_qla_host *ha)
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/*----------------------Interrupt Related functions ---------------------*/
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void qla4_83xx_disable_intrs(struct scsi_qla_host *ha)
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static void qla4_83xx_disable_iocb_intrs(struct scsi_qla_host *ha)
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{
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if (test_and_clear_bit(AF_83XX_IOCB_INTR_ON, &ha->flags))
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qla4_8xxx_intr_disable(ha);
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}
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static void qla4_83xx_disable_mbox_intrs(struct scsi_qla_host *ha)
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{
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uint32_t mb_int, ret;
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if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
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qla4_8xxx_mbx_intr_disable(ha);
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ret = readl(&ha->qla4_83xx_reg->mbox_int);
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mb_int = ret & ~INT_ENABLE_FW_MB;
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writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
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writel(1, &ha->qla4_83xx_reg->leg_int_mask);
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if (test_and_clear_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) {
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ret = readl(&ha->qla4_83xx_reg->mbox_int);
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mb_int = ret & ~INT_ENABLE_FW_MB;
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writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
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writel(1, &ha->qla4_83xx_reg->leg_int_mask);
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}
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}
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void qla4_83xx_enable_intrs(struct scsi_qla_host *ha)
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void qla4_83xx_disable_intrs(struct scsi_qla_host *ha)
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{
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qla4_83xx_disable_mbox_intrs(ha);
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qla4_83xx_disable_iocb_intrs(ha);
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}
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static void qla4_83xx_enable_iocb_intrs(struct scsi_qla_host *ha)
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{
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if (!test_bit(AF_83XX_IOCB_INTR_ON, &ha->flags)) {
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qla4_8xxx_intr_enable(ha);
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set_bit(AF_83XX_IOCB_INTR_ON, &ha->flags);
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}
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}
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void qla4_83xx_enable_mbox_intrs(struct scsi_qla_host *ha)
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{
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uint32_t mb_int;
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qla4_8xxx_mbx_intr_enable(ha);
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mb_int = INT_ENABLE_FW_MB;
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writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
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writel(0, &ha->qla4_83xx_reg->leg_int_mask);
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set_bit(AF_INTERRUPTS_ON, &ha->flags);
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if (!test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags)) {
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mb_int = INT_ENABLE_FW_MB;
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writel(mb_int, &ha->qla4_83xx_reg->mbox_int);
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writel(0, &ha->qla4_83xx_reg->leg_int_mask);
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set_bit(AF_83XX_MBOX_INTR_ON, &ha->flags);
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}
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}
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void qla4_83xx_enable_intrs(struct scsi_qla_host *ha)
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{
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qla4_83xx_enable_mbox_intrs(ha);
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qla4_83xx_enable_iocb_intrs(ha);
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}
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void qla4_83xx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
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int incount)
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{
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@ -516,6 +516,8 @@ struct scsi_qla_host {
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#define AF_8XXX_RST_OWNER 25 /* 0x02000000 */
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#define AF_82XX_DUMP_READING 26 /* 0x04000000 */
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#define AF_83XX_NO_FW_DUMP 27 /* 0x08000000 */
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#define AF_83XX_IOCB_INTR_ON 28 /* 0x10000000 */
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#define AF_83XX_MBOX_INTR_ON 29 /* 0x20000000 */
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unsigned long dpc_flags;
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@ -253,12 +253,13 @@ void qla4_8xxx_set_rst_ready(struct scsi_qla_host *ha);
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void qla4_8xxx_clear_rst_ready(struct scsi_qla_host *ha);
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int qla4_8xxx_device_bootstrap(struct scsi_qla_host *ha);
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void qla4_8xxx_get_minidump(struct scsi_qla_host *ha);
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int qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha);
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int qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha);
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int qla4_8xxx_intr_disable(struct scsi_qla_host *ha);
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int qla4_8xxx_intr_enable(struct scsi_qla_host *ha);
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int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param);
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int qla4_8xxx_update_idc_reg(struct scsi_qla_host *ha);
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int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha);
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void qla4_83xx_disable_pause(struct scsi_qla_host *ha);
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void qla4_83xx_enable_mbox_intrs(struct scsi_qla_host *ha);
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extern int ql4xextended_error_logging;
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extern int ql4xdontresethba;
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@ -935,6 +935,16 @@ int qla4xxx_initialize_adapter(struct scsi_qla_host *ha, int is_reset)
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if (ha->isp_ops->start_firmware(ha) == QLA_ERROR)
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goto exit_init_hba;
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/*
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* For ISP83XX, mailbox and IOCB interrupts are enabled separately.
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* Mailbox interrupts must be enabled prior to issuing any mailbox
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* command in order to prevent the possibility of losing interrupts
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* while switching from polling to interrupt mode. IOCB interrupts are
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* enabled via isp_ops->enable_intrs.
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*/
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if (is_qla8032(ha))
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qla4_83xx_enable_mbox_intrs(ha);
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if (qla4xxx_about_firmware(ha) == QLA_ERROR)
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goto exit_init_hba;
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@ -1437,11 +1437,14 @@ int qla4xxx_request_irqs(struct scsi_qla_host *ha)
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void qla4xxx_free_irqs(struct scsi_qla_host *ha)
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{
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if (test_bit(AF_MSIX_ENABLED, &ha->flags))
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qla4_8xxx_disable_msix(ha);
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else if (test_and_clear_bit(AF_MSI_ENABLED, &ha->flags)) {
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free_irq(ha->pdev->irq, ha);
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pci_disable_msi(ha->pdev);
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} else if (test_and_clear_bit(AF_INTx_ENABLED, &ha->flags))
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free_irq(ha->pdev->irq, ha);
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if (test_and_clear_bit(AF_IRQ_ATTACHED, &ha->flags)) {
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if (test_bit(AF_MSIX_ENABLED, &ha->flags)) {
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qla4_8xxx_disable_msix(ha);
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} else if (test_and_clear_bit(AF_MSI_ENABLED, &ha->flags)) {
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free_irq(ha->pdev->irq, ha);
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pci_disable_msi(ha->pdev);
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} else if (test_and_clear_bit(AF_INTx_ENABLED, &ha->flags)) {
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free_irq(ha->pdev->irq, ha);
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}
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}
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}
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@ -43,6 +43,30 @@ void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
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}
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}
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/**
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* qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts?
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* @ha: Pointer to host adapter structure.
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* @ret: 1=polling mode, 0=non-polling mode
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**/
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static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
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{
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int rval = 1;
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if (is_qla8032(ha)) {
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if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
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test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
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rval = 0;
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} else {
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if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
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test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
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test_bit(AF_ONLINE, &ha->flags) &&
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!test_bit(AF_HA_REMOVAL, &ha->flags))
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rval = 0;
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}
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return rval;
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}
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/**
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* qla4xxx_mailbox_command - issues mailbox commands
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* @ha: Pointer to host adapter structure.
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@ -153,33 +177,28 @@ int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
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/*
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* Wait for completion: Poll or completion queue
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*/
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if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
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test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
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test_bit(AF_ONLINE, &ha->flags) &&
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!test_bit(AF_HA_REMOVAL, &ha->flags)) {
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/* Do not poll for completion. Use completion queue */
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set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
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wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
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clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
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} else {
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if (qla4xxx_is_intr_poll_mode(ha)) {
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/* Poll for command to complete */
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wait_count = jiffies + MBOX_TOV * HZ;
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while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
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if (time_after_eq(jiffies, wait_count))
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break;
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/*
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* Service the interrupt.
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* The ISR will save the mailbox status registers
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* to a temporary storage location in the adapter
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* structure.
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*/
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spin_lock_irqsave(&ha->hardware_lock, flags);
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ha->isp_ops->process_mailbox_interrupt(ha, outCount);
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spin_unlock_irqrestore(&ha->hardware_lock, flags);
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msleep(10);
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}
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} else {
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/* Do not poll for completion. Use completion queue */
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set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
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wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
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clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
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}
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/* Check for mailbox timeout. */
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@ -3463,7 +3463,7 @@ int qla4_8xxx_get_sys_info(struct scsi_qla_host *ha)
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/* Interrupt handling helpers. */
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int qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
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int qla4_8xxx_intr_enable(struct scsi_qla_host *ha)
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{
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uint32_t mbox_cmd[MBOX_REG_COUNT];
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uint32_t mbox_sts[MBOX_REG_COUNT];
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@ -3484,7 +3484,7 @@ int qla4_8xxx_mbx_intr_enable(struct scsi_qla_host *ha)
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return QLA_SUCCESS;
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}
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int qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
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int qla4_8xxx_intr_disable(struct scsi_qla_host *ha)
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{
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uint32_t mbox_cmd[MBOX_REG_COUNT];
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uint32_t mbox_sts[MBOX_REG_COUNT];
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@ -3509,7 +3509,7 @@ int qla4_8xxx_mbx_intr_disable(struct scsi_qla_host *ha)
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void
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qla4_82xx_enable_intrs(struct scsi_qla_host *ha)
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{
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qla4_8xxx_mbx_intr_enable(ha);
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qla4_8xxx_intr_enable(ha);
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spin_lock_irq(&ha->hardware_lock);
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/* BIT 10 - reset */
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@ -3522,7 +3522,7 @@ void
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qla4_82xx_disable_intrs(struct scsi_qla_host *ha)
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{
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if (test_and_clear_bit(AF_INTERRUPTS_ON, &ha->flags))
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qla4_8xxx_mbx_intr_disable(ha);
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qla4_8xxx_intr_disable(ha);
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spin_lock_irq(&ha->hardware_lock);
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/* BIT 10 - set */
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@ -2978,6 +2978,7 @@ static int qla4xxx_recover_adapter(struct scsi_qla_host *ha)
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if (status == QLA_SUCCESS) {
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if (!test_bit(AF_FW_RECOVERY, &ha->flags))
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qla4xxx_cmd_wait(ha);
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ha->isp_ops->disable_intrs(ha);
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qla4xxx_process_aen(ha, FLUSH_DDB_CHANGED_AENS);
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qla4xxx_abort_active_cmds(ha, DID_RESET << 16);
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@ -3508,10 +3509,8 @@ static void qla4xxx_free_adapter(struct scsi_qla_host *ha)
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{
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qla4xxx_abort_active_cmds(ha, DID_NO_CONNECT << 16);
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if (test_bit(AF_INTERRUPTS_ON, &ha->flags)) {
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/* Turn-off interrupts on the card. */
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ha->isp_ops->disable_intrs(ha);
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}
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/* Turn-off interrupts on the card. */
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ha->isp_ops->disable_intrs(ha);
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if (is_qla40XX(ha)) {
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writel(set_rmask(CSR_SCSI_PROCESSOR_INTR),
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@ -3547,8 +3546,7 @@ static void qla4xxx_free_adapter(struct scsi_qla_host *ha)
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}
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/* Detach interrupts */
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if (test_and_clear_bit(AF_IRQ_ATTACHED, &ha->flags))
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qla4xxx_free_irqs(ha);
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qla4xxx_free_irqs(ha);
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/* free extra memory */
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qla4xxx_mem_free(ha);
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