mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-06 16:49:22 +00:00
i.MX clock changes for
- Fix reparenting of UART clocks by initializing only the ones associated to stdout. - Correct the PCIE clocks for i.MX8MP and i.MX8MQ. - Make LPCG and SCU clocks return on registering failure -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdRlgxHYCb3ovKt456LNSLBEEo7YFAmBqHW8ACgkQ6LNSLBEE o7YSMA/8DuAo6cIfP3tFM+dHPB2OqqdbZOl1sLiOVs0iIte8rDjE5gm20M8mfLBO Jq1XAueUCXcH9jWaOwY6CSWyKaB2lSGCAR/DY19PcgCMHYWy+d4PcM2VfU04HzWK y85PneTWE4eIKUMDICGbnBRfw8uLfQQS7OoxvBM3Q4So9HNLvuGWwC8Zq/E3wD24 Ab4zcl+IjjccF/sjTgdwiFSa2looOpML0pSqdB8zKkJ27p4zsLxQktiQS1Mukh26 G99FrGKxJYY41bwzo+m6dSFVUpIMR0fg+MZNqCm2G5Vlz5Ot7JU+mHPZVtqgfYJ6 86KYs5TEunnNCDk2aDecYWeRG1/tAwbl6Qs4RUe7KTGJPn+gIyZTqKv7C14rOLTj a4ZzlwbWZ9jnAjFcZCi8Gc6Vp5RqZmVt/1ixQdg/S+KdbtHKKM4SIBLxgU96jpqL 2HLnYcUsoiFCM/tEgWOrqCTEdVUH5evW1umWn9k6jypXRtFTC2n0W+MJ8oMNXz2O rGmHmynlDmv5bKiwLFXfgChbCZqA/vLA8nnzRmX7kxIBaowD88aNJx4h6ksINbN1 py7/l0sNlWYz8K6B9QOkJi0N7CWO3BdgNoVpiURwr6Wr3xJHrCT+vKHpbvPn4eCF 3DGx96e5zYu2UEGbC5tI0wz+nLUfVKaCl6slK+M5ZAnnx8sC7xU= =BdIb -----END PGP SIGNATURE----- Merge tag 'clk-imx-5.13' of https://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx Pull i.MX clk driver updates from Abel Vesa: - Fix reparenting of UART clocks by initializing only the ones associated to stdout - Correct the PCIE clocks for i.MX8MP and i.MX8MQ - Make LPCG and SCU clocks return on registering failure * tag 'clk-imx-5.13' of https://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux: clk: imx: Reference preceded by free clk: imx8mq: Correct the pcie1 sels clk: imx8mp: Remove the none exist pcie clocks clk: imx: Fix reparenting of UARTs not associated with stdout
This commit is contained in:
Stephen Boyd
commit
5c55197cbf
19 changed files with 58 additions and 272 deletions
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@ -73,16 +73,6 @@ enum mx25_clks {
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static struct clk *clk[clk_max];
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static struct clk ** const uart_clks[] __initconst = {
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&clk[uart_ipg_per],
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&clk[uart1_ipg],
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&clk[uart2_ipg],
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&clk[uart3_ipg],
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&clk[uart4_ipg],
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&clk[uart5_ipg],
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NULL
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};
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static int __init __mx25_clocks_init(void __iomem *ccm_base)
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{
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BUG_ON(!ccm_base);
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@ -228,7 +218,7 @@ static int __init __mx25_clocks_init(void __iomem *ccm_base)
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*/
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clk_set_parent(clk[cko_sel], clk[ipg]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(6);
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return 0;
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}
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@ -49,17 +49,6 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
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static struct clk *clk[IMX27_CLK_MAX];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks[] __initconst = {
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&clk[IMX27_CLK_PER1_GATE],
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&clk[IMX27_CLK_UART1_IPG_GATE],
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&clk[IMX27_CLK_UART2_IPG_GATE],
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&clk[IMX27_CLK_UART3_IPG_GATE],
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&clk[IMX27_CLK_UART4_IPG_GATE],
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&clk[IMX27_CLK_UART5_IPG_GATE],
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&clk[IMX27_CLK_UART6_IPG_GATE],
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NULL
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};
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static void __init _mx27_clocks_init(unsigned long fref)
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{
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BUG_ON(!ccm);
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@ -176,7 +165,7 @@ static void __init _mx27_clocks_init(unsigned long fref)
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clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(7);
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imx_print_silicon_rev("i.MX27", mx27_revision());
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}
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@ -82,14 +82,6 @@ enum mx35_clks {
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static struct clk *clk[clk_max];
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static struct clk ** const uart_clks[] __initconst = {
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&clk[ipg],
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&clk[uart1_gate],
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&clk[uart2_gate],
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&clk[uart3_gate],
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NULL
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};
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static void __init _mx35_clocks_init(void)
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{
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void __iomem *base;
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@ -243,7 +235,7 @@ static void __init _mx35_clocks_init(void)
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*/
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clk_prepare_enable(clk[scc_gate]);
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(4);
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imx_print_silicon_rev("i.MX35", mx35_revision());
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}
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@ -128,30 +128,6 @@ static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_
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static struct clk *clk[IMX5_CLK_END];
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static struct clk_onecell_data clk_data;
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static struct clk ** const uart_clks_mx51[] __initconst = {
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&clk[IMX5_CLK_UART1_IPG_GATE],
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&clk[IMX5_CLK_UART1_PER_GATE],
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&clk[IMX5_CLK_UART2_IPG_GATE],
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&clk[IMX5_CLK_UART2_PER_GATE],
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&clk[IMX5_CLK_UART3_IPG_GATE],
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&clk[IMX5_CLK_UART3_PER_GATE],
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NULL
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};
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static struct clk ** const uart_clks_mx50_mx53[] __initconst = {
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&clk[IMX5_CLK_UART1_IPG_GATE],
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&clk[IMX5_CLK_UART1_PER_GATE],
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&clk[IMX5_CLK_UART2_IPG_GATE],
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&clk[IMX5_CLK_UART2_PER_GATE],
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&clk[IMX5_CLK_UART3_IPG_GATE],
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&clk[IMX5_CLK_UART3_PER_GATE],
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&clk[IMX5_CLK_UART4_IPG_GATE],
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&clk[IMX5_CLK_UART4_PER_GATE],
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&clk[IMX5_CLK_UART5_IPG_GATE],
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&clk[IMX5_CLK_UART5_PER_GATE],
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NULL
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};
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static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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{
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clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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@ -382,7 +358,7 @@ static void __init mx50_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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imx_register_uart_clocks(uart_clks_mx50_mx53);
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imx_register_uart_clocks(5);
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}
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CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
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@ -488,7 +464,7 @@ static void __init mx51_clocks_init(struct device_node *np)
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val |= 1 << 23;
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writel(val, MXC_CCM_CLPCR);
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imx_register_uart_clocks(uart_clks_mx51);
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imx_register_uart_clocks(3);
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}
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CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
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@ -633,6 +609,6 @@ static void __init mx53_clocks_init(struct device_node *np)
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r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
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clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
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imx_register_uart_clocks(uart_clks_mx50_mx53);
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imx_register_uart_clocks(5);
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}
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CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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@ -140,13 +140,6 @@ static inline int clk_on_imx6dl(void)
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return of_machine_is_compatible("fsl,imx6dl");
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}
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static const int uart_clk_ids[] __initconst = {
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IMX6QDL_CLK_UART_IPG,
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IMX6QDL_CLK_UART_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static int ldb_di_sel_by_clock_id(int clock_id)
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{
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switch (clock_id) {
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@ -440,7 +433,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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struct device_node *np;
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void __iomem *anatop_base, *base;
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int ret;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6QDL_CLK_END), GFP_KERNEL);
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@ -982,12 +974,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
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hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
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}
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(1);
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}
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CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
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@ -179,19 +179,11 @@ void imx6sl_set_wait_clk(bool enter)
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imx6sl_enable_pll_arm(false);
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}
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static const int uart_clk_ids[] __initconst = {
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IMX6SL_CLK_UART,
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IMX6SL_CLK_UART_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int ret;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6SL_CLK_END), GFP_KERNEL);
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@ -448,12 +440,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
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clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk,
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hws[IMX6SL_CLK_PLL2_PFD2]->clk);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(2);
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}
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CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
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@ -76,26 +76,10 @@ static u32 share_count_ssi1;
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static u32 share_count_ssi2;
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static u32 share_count_ssi3;
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static const int uart_clk_ids[] __initconst = {
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IMX6SLL_CLK_UART1_IPG,
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IMX6SLL_CLK_UART1_SERIAL,
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IMX6SLL_CLK_UART2_IPG,
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IMX6SLL_CLK_UART2_SERIAL,
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IMX6SLL_CLK_UART3_IPG,
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IMX6SLL_CLK_UART3_SERIAL,
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IMX6SLL_CLK_UART4_IPG,
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IMX6SLL_CLK_UART4_SERIAL,
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IMX6SLL_CLK_UART5_IPG,
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IMX6SLL_CLK_UART5_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6SLL_CLK_END), GFP_KERNEL);
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@ -356,13 +340,7 @@ static void __init imx6sll_clocks_init(struct device_node *ccm_node)
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(5);
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/* Lower the AHB clock rate before changing the clock source. */
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clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000);
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@ -117,18 +117,10 @@ static u32 share_count_ssi3;
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static u32 share_count_sai1;
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static u32 share_count_sai2;
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static const int uart_clk_ids[] __initconst = {
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IMX6SX_CLK_UART_IPG,
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IMX6SX_CLK_UART_SERIAL,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX6SX_CLK_CLK_END), GFP_KERNEL);
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@ -556,12 +548,6 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
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clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
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clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(2);
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}
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CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
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@ -377,23 +377,10 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_
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static struct clk_hw **hws;
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static struct clk_hw_onecell_data *clk_hw_data;
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static const int uart_clk_ids[] __initconst = {
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IMX7D_UART1_ROOT_CLK,
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IMX7D_UART2_ROOT_CLK,
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IMX7D_UART3_ROOT_CLK,
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IMX7D_UART4_ROOT_CLK,
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IMX7D_UART5_ROOT_CLK,
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IMX7D_UART6_ROOT_CLK,
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IMX7D_UART7_ROOT_CLK,
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};
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static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1] __initdata;
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static void __init imx7d_clocks_init(struct device_node *ccm_node)
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{
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struct device_node *np;
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void __iomem *base;
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int i;
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clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
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IMX7D_CLK_END), GFP_KERNEL);
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@ -897,14 +884,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
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hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1);
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hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1);
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for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
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int index = uart_clk_ids[i];
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uart_clks[i] = &hws[index]->clk;
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}
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imx_register_uart_clocks(uart_clks);
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imx_register_uart_clocks(7);
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}
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CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
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@ -43,19 +43,6 @@ static const struct clk_div_table ulp_div_table[] = {
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{ /* sentinel */ },
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};
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static const int pcc2_uart_clk_ids[] __initconst = {
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IMX7ULP_CLK_LPUART4,
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IMX7ULP_CLK_LPUART5,
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};
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static const int pcc3_uart_clk_ids[] __initconst = {
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IMX7ULP_CLK_LPUART6,
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IMX7ULP_CLK_LPUART7,
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};
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static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
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static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
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static void __init imx7ulp_clk_scg1_init(struct device_node *np)
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{
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struct clk_hw_onecell_data *clk_data;
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@ -150,7 +137,6 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
|
|||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw **hws;
|
||||
void __iomem *base;
|
||||
int i;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
|
||||
GFP_KERNEL);
|
||||
|
|
@ -190,13 +176,7 @@ static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
|
|||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
|
||||
int index = pcc2_uart_clk_ids[i];
|
||||
|
||||
pcc2_uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(pcc2_uart_clks);
|
||||
imx_register_uart_clocks(2);
|
||||
}
|
||||
CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
|
||||
|
||||
|
|
@ -205,7 +185,6 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
|
|||
struct clk_hw_onecell_data *clk_data;
|
||||
struct clk_hw **hws;
|
||||
void __iomem *base;
|
||||
int i;
|
||||
|
||||
clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
|
||||
GFP_KERNEL);
|
||||
|
|
@ -244,13 +223,7 @@ static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
|
|||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
|
||||
int index = pcc3_uart_clk_ids[i];
|
||||
|
||||
pcc3_uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(pcc3_uart_clks);
|
||||
imx_register_uart_clocks(7);
|
||||
}
|
||||
CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
|
||||
|
||||
|
|
|
|||
|
|
@ -296,20 +296,12 @@ static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "
|
|||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MM_CLK_UART1_ROOT,
|
||||
IMX8MM_CLK_UART2_ROOT,
|
||||
IMX8MM_CLK_UART3_ROOT,
|
||||
IMX8MM_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mm_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret, i;
|
||||
int ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MM_CLK_END), GFP_KERNEL);
|
||||
|
|
@ -634,13 +626,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -289,20 +289,12 @@ static const char * const clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "
|
|||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MN_CLK_UART1_ROOT,
|
||||
IMX8MN_CLK_UART2_ROOT,
|
||||
IMX8MN_CLK_UART3_ROOT,
|
||||
IMX8MN_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mn_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int ret, i;
|
||||
int ret;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MN_CLK_END), GFP_KERNEL);
|
||||
|
|
@ -585,13 +577,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys
|
|||
"sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out",
|
||||
"sys_pll2_250m", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
|
||||
"clk_ext1", "clk_ext2", "clk_ext3",
|
||||
"clk_ext4", "sys_pll1_400m", };
|
||||
|
||||
static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m",
|
||||
"sys_pll1_160m", "sys_pll1_200m", };
|
||||
|
|
@ -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll2_100m",
|
|||
"sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out",
|
||||
"clk_ext3", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m",
|
||||
"sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m",
|
||||
"sys_pll2_333m", "sys_pll3_out", };
|
||||
|
||||
static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m",
|
||||
"clk_ext1", "clk_ext2", "clk_ext3",
|
||||
"clk_ext4", "sys_pll1_400m", };
|
||||
|
||||
static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
|
||||
"sys_pll3_out", "sys_pll2_100m",
|
||||
"sys_pll1_80m", "sys_pll1_160m",
|
||||
|
|
@ -414,20 +402,11 @@ static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_r
|
|||
static struct clk_hw **hws;
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MP_CLK_UART1_ROOT,
|
||||
IMX8MP_CLK_UART2_ROOT,
|
||||
IMX8MP_CLK_UART3_ROOT,
|
||||
IMX8MP_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_clks[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mp_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np;
|
||||
void __iomem *anatop_base, *ccm_base;
|
||||
int i;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mp-anatop");
|
||||
anatop_base = of_iomap(np, 0);
|
||||
|
|
@ -585,7 +564,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
|
||||
hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);
|
||||
hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280);
|
||||
hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm_base + 0xa380);
|
||||
hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400);
|
||||
hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480);
|
||||
hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, ccm_base + 0xa500);
|
||||
|
|
@ -643,8 +621,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
|
||||
hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00);
|
||||
hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80);
|
||||
hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
|
||||
hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
|
||||
hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
|
||||
hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180);
|
||||
hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ccm_base + 0xc200);
|
||||
|
|
@ -737,13 +713,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_clks[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_clks);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -113,12 +113,12 @@ static const char * const imx8mq_disp_dtrc_sels[] = {"osc_25m", "vpu_pll_out", "
|
|||
static const char * const imx8mq_disp_dc8000_sels[] = {"osc_25m", "vpu_pll_out", "sys1_pll_800m", "sys2_pll_1000m", "sys1_pll_160m", "sys2_pll_100m", "sys3_pll_out", "audio_pll2_out", };
|
||||
|
||||
static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m", "sys2_pll_200m", "sys1_pll_266m",
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_250m", "sys3_pll_out", };
|
||||
"sys1_pll_800m", "sys2_pll_500m", "sys2_pll_333m", "sys3_pll_out", };
|
||||
|
||||
static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
|
||||
"clk_ext3", "clk_ext4", };
|
||||
|
||||
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out",
|
||||
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out",
|
||||
"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
|
||||
|
||||
static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };
|
||||
|
|
@ -281,20 +281,12 @@ static const char * const pllout_monitor_sels[] = {"osc_25m", "osc_27m", "dummy"
|
|||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
static struct clk_hw **hws;
|
||||
|
||||
static const int uart_clk_ids[] = {
|
||||
IMX8MQ_CLK_UART1_ROOT,
|
||||
IMX8MQ_CLK_UART2_ROOT,
|
||||
IMX8MQ_CLK_UART3_ROOT,
|
||||
IMX8MQ_CLK_UART4_ROOT,
|
||||
};
|
||||
static struct clk **uart_hws[ARRAY_SIZE(uart_clk_ids) + 1];
|
||||
|
||||
static int imx8mq_clocks_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
void __iomem *base;
|
||||
int err, i;
|
||||
int err;
|
||||
|
||||
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
|
||||
IMX8MQ_CLK_END), GFP_KERNEL);
|
||||
|
|
@ -629,13 +621,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
goto unregister_hws;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(uart_clk_ids); i++) {
|
||||
int index = uart_clk_ids[i];
|
||||
|
||||
uart_hws[i] = &hws[index]->clk;
|
||||
}
|
||||
|
||||
imx_register_uart_clocks(uart_hws);
|
||||
imx_register_uart_clocks(4);
|
||||
|
||||
return 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -114,6 +114,7 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
|
|||
if (ret) {
|
||||
kfree(clk);
|
||||
hw = ERR_PTR(ret);
|
||||
return hw;
|
||||
}
|
||||
|
||||
if (dev)
|
||||
|
|
|
|||
|
|
@ -426,6 +426,7 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
|
|||
if (ret) {
|
||||
kfree(clk);
|
||||
hw = ERR_PTR(ret);
|
||||
return hw;
|
||||
}
|
||||
|
||||
if (dev)
|
||||
|
|
|
|||
|
|
@ -147,8 +147,10 @@ void imx_cscmr1_fixup(u32 *val)
|
|||
}
|
||||
|
||||
#ifndef MODULE
|
||||
static int imx_keep_uart_clocks;
|
||||
static struct clk ** const *imx_uart_clocks;
|
||||
|
||||
static bool imx_keep_uart_clocks;
|
||||
static int imx_enabled_uart_clocks;
|
||||
static struct clk **imx_uart_clocks;
|
||||
|
||||
static int __init imx_keep_uart_clocks_param(char *str)
|
||||
{
|
||||
|
|
@ -161,24 +163,45 @@ __setup_param("earlycon", imx_keep_uart_earlycon,
|
|||
__setup_param("earlyprintk", imx_keep_uart_earlyprintk,
|
||||
imx_keep_uart_clocks_param, 0);
|
||||
|
||||
void imx_register_uart_clocks(struct clk ** const clks[])
|
||||
void imx_register_uart_clocks(unsigned int clk_count)
|
||||
{
|
||||
imx_enabled_uart_clocks = 0;
|
||||
|
||||
/* i.MX boards use device trees now. For build tests without CONFIG_OF, do nothing */
|
||||
#ifdef CONFIG_OF
|
||||
if (imx_keep_uart_clocks) {
|
||||
int i;
|
||||
|
||||
imx_uart_clocks = clks;
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_prepare_enable(*imx_uart_clocks[i]);
|
||||
imx_uart_clocks = kcalloc(clk_count, sizeof(struct clk *), GFP_KERNEL);
|
||||
|
||||
if (!of_stdout)
|
||||
return;
|
||||
|
||||
for (i = 0; i < clk_count; i++) {
|
||||
imx_uart_clocks[imx_enabled_uart_clocks] = of_clk_get(of_stdout, i);
|
||||
|
||||
/* Stop if there are no more of_stdout references */
|
||||
if (IS_ERR(imx_uart_clocks[imx_enabled_uart_clocks]))
|
||||
return;
|
||||
|
||||
/* Only enable the clock if it's not NULL */
|
||||
if (imx_uart_clocks[imx_enabled_uart_clocks])
|
||||
clk_prepare_enable(imx_uart_clocks[imx_enabled_uart_clocks++]);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static int __init imx_clk_disable_uart(void)
|
||||
{
|
||||
if (imx_keep_uart_clocks && imx_uart_clocks) {
|
||||
if (imx_keep_uart_clocks && imx_enabled_uart_clocks) {
|
||||
int i;
|
||||
|
||||
for (i = 0; imx_uart_clocks[i]; i++)
|
||||
clk_disable_unprepare(*imx_uart_clocks[i]);
|
||||
for (i = 0; i < imx_enabled_uart_clocks; i++) {
|
||||
clk_disable_unprepare(imx_uart_clocks[i]);
|
||||
clk_put(imx_uart_clocks[i]);
|
||||
}
|
||||
kfree(imx_uart_clocks);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -11,9 +11,9 @@ extern spinlock_t imx_ccm_lock;
|
|||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
|
||||
#ifndef MODULE
|
||||
void imx_register_uart_clocks(struct clk ** const clks[]);
|
||||
void imx_register_uart_clocks(unsigned int clk_count);
|
||||
#else
|
||||
static inline void imx_register_uart_clocks(struct clk ** const clks[])
|
||||
static inline void imx_register_uart_clocks(unsigned int clk_count)
|
||||
{
|
||||
}
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||||
#endif
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||||
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|||
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@ -125,7 +125,6 @@
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#define IMX8MP_CLK_CAN1 116
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||||
#define IMX8MP_CLK_CAN2 117
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||||
#define IMX8MP_CLK_MEMREPAIR 118
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#define IMX8MP_CLK_PCIE_PHY 119
|
||||
#define IMX8MP_CLK_PCIE_AUX 120
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#define IMX8MP_CLK_I2C5 121
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#define IMX8MP_CLK_I2C6 122
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@ -182,8 +181,6 @@
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#define IMX8MP_CLK_MEDIA_CAM2_PIX 173
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#define IMX8MP_CLK_MEDIA_LDB 174
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#define IMX8MP_CLK_MEDIA_MIPI_CSI2_ESC 175
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||||
#define IMX8MP_CLK_PCIE2_CTRL 176
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||||
#define IMX8MP_CLK_PCIE2_PHY 177
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||||
#define IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE 178
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||||
#define IMX8MP_CLK_ECSPI3 179
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||||
#define IMX8MP_CLK_PDM 180
|
||||
|
|
|
|||
Loading…
Reference in a new issue