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drm/amd/amdgpu: add vega10/raven mmhub/athub golden settings
Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 23 additions and 0 deletions
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@ -32,6 +32,8 @@
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#include "vega10/DC/dce_12_0_offset.h"
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#include "vega10/DC/dce_12_0_sh_mask.h"
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#include "vega10/vega10_enum.h"
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#include "vega10/MMHUB/mmhub_1_0_offset.h"
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#include "vega10/ATHUB/athub_1_0_offset.h"
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#include "soc15_common.h"
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@ -71,6 +73,18 @@ static const u32 golden_settings_vega10_hdp[] =
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0xf6e, 0x0fffffff, 0x00000000,
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};
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static const u32 golden_settings_mmhub_1_0_0[] =
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{
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SOC15_REG_OFFSET(MMHUB, 0, mmDAGB1_WRCLI2), 0x00000007, 0xfe5fe0fa,
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SOC15_REG_OFFSET(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0), 0x00000030, 0x55555565
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};
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static const u32 golden_settings_athub_1_0_0[] =
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{
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SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL), 0x0000ff00, 0x00000800,
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SOC15_REG_OFFSET(ATHUB, 0, mmRPB_ARB_CNTL2), 0x00ff00ff, 0x00080008
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};
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static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
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unsigned type,
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@ -665,8 +679,17 @@ static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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amdgpu_program_register_sequence(adev,
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golden_settings_mmhub_1_0_0,
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(const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
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amdgpu_program_register_sequence(adev,
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golden_settings_athub_1_0_0,
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(const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
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break;
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case CHIP_RAVEN:
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amdgpu_program_register_sequence(adev,
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golden_settings_athub_1_0_0,
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(const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
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break;
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default:
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break;
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