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ASoC: amd: vangogh: refactor i2s master mode clock sequence code
Refactor I2S Master mode clock programming sequence code. This will also fix the i2s clocks restore issue during system level resume. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Link: https://lore.kernel.org/r/20220223071959.13539-2-Vijendar.Mukunda@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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parent
4b0bec6088
commit
5ca4cf2c83
2 changed files with 36 additions and 19 deletions
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@ -88,10 +88,9 @@ static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
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struct snd_soc_card *card;
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struct acp5x_platform_info *pinfo;
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struct i2s_dev_data *adata;
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union acp_i2stdm_mstrclkgen mclkgen;
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u32 val;
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u32 reg_val, frmt_reg, master_reg;
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u32 reg_val, frmt_reg;
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u32 lrclk_div_val, bclk_div_val;
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lrclk_div_val = 0;
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@ -160,20 +159,6 @@ static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
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acp_writel(val, rtd->acp5x_base + reg_val);
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if (adata->master_mode) {
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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master_reg = ACP_I2STDM2_MSTRCLKGEN;
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break;
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case I2S_SP_INSTANCE:
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default:
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master_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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}
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mclkgen.bits.i2stdm_master_mode = 0x1;
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if (adata->tdm_mode)
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mclkgen.bits.i2stdm_format_mode = 0x01;
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else
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mclkgen.bits.i2stdm_format_mode = 0x0;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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switch (params_rate(params)) {
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@ -238,9 +223,8 @@ static int acp5x_i2s_hwparams(struct snd_pcm_substream *substream,
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default:
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return -EINVAL;
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}
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mclkgen.bits.i2stdm_bclk_div_val = bclk_div_val;
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mclkgen.bits.i2stdm_lrclk_div_val = lrclk_div_val;
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acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
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rtd->lrclk_div = lrclk_div_val;
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rtd->bclk_div = bclk_div_val;
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}
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return 0;
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}
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@ -249,9 +233,11 @@ static int acp5x_i2s_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct i2s_stream_instance *rtd;
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struct i2s_dev_data *adata;
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u32 ret, val, period_bytes, reg_val, ier_val, water_val;
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u32 buf_size, buf_reg;
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adata = snd_soc_dai_get_drvdata(dai);
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rtd = substream->runtime->private_data;
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period_bytes = frames_to_bytes(substream->runtime,
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substream->runtime->period_size);
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@ -300,6 +286,8 @@ static int acp5x_i2s_trigger(struct snd_pcm_substream *substream,
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}
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acp_writel(period_bytes, rtd->acp5x_base + water_val);
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acp_writel(buf_size, rtd->acp5x_base + buf_reg);
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if (adata->master_mode)
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acp5x_set_i2s_clk(adata, rtd);
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val = acp_readl(rtd->acp5x_base + reg_val);
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val = val | BIT(0);
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acp_writel(val, rtd->acp5x_base + reg_val);
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@ -105,6 +105,8 @@ struct i2s_stream_instance {
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dma_addr_t dma_addr;
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u64 bytescount;
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void __iomem *acp5x_base;
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u32 lrclk_div;
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u32 bclk_div;
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};
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union acp_dma_count {
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@ -191,3 +193,30 @@ static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd,
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}
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return byte_count.bytescount;
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}
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static inline void acp5x_set_i2s_clk(struct i2s_dev_data *adata,
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struct i2s_stream_instance *rtd)
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{
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union acp_i2stdm_mstrclkgen mclkgen;
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u32 master_reg;
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switch (rtd->i2s_instance) {
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case I2S_HS_INSTANCE:
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master_reg = ACP_I2STDM2_MSTRCLKGEN;
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break;
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case I2S_SP_INSTANCE:
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default:
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master_reg = ACP_I2STDM0_MSTRCLKGEN;
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break;
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}
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mclkgen.bits.i2stdm_master_mode = 0x1;
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if (adata->tdm_mode)
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mclkgen.bits.i2stdm_format_mode = 0x01;
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else
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mclkgen.bits.i2stdm_format_mode = 0x00;
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mclkgen.bits.i2stdm_bclk_div_val = rtd->bclk_div;
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mclkgen.bits.i2stdm_lrclk_div_val = rtd->lrclk_div;
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acp_writel(mclkgen.u32_all, rtd->acp5x_base + master_reg);
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}
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