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KVM: PPC: Book3S HV: XIVE: Add a global reset control
This control is to be used by the H_INT_RESET hcall from QEMU. Its purpose is to clear all configuration of the sources and EQs. This is necessary in case of a kexec (for a kdump kernel for instance) to make sure that no remaining configuration is left from the previous boot setup so that the new kernel can start safely from a clean state. The queue 7 is ignored when the XIVE device is configured to run in single escalation mode. Prio 7 is used by escalations. The XIVE VP is kept enabled as the vCPU is still active and connected to the XIVE device. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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3 changed files with 91 additions and 0 deletions
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@ -17,6 +17,11 @@ the legacy interrupt mode, referred as XICS (POWER7/8).
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1. KVM_DEV_XIVE_GRP_CTRL
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Provides global controls on the device
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Attributes:
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1.1 KVM_DEV_XIVE_RESET (write only)
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Resets the interrupt controller configuration for sources and event
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queues. To be used by kexec and kdump.
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Errors: none
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2. KVM_DEV_XIVE_GRP_SOURCE (write only)
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Initializes a new source in the XIVE device and mask it.
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@ -679,6 +679,7 @@ struct kvm_ppc_cpu_char {
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/* POWER9 XIVE Native Interrupt Controller */
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#define KVM_DEV_XIVE_GRP_CTRL 1
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#define KVM_DEV_XIVE_RESET 1
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#define KVM_DEV_XIVE_GRP_SOURCE 2 /* 64-bit source identifier */
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#define KVM_DEV_XIVE_GRP_SOURCE_CONFIG 3 /* 64-bit source identifier */
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#define KVM_DEV_XIVE_GRP_EQ_CONFIG 4 /* 64-bit EQ identifier */
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@ -572,6 +572,83 @@ static int kvmppc_xive_native_get_queue_config(struct kvmppc_xive *xive,
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return 0;
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}
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static void kvmppc_xive_reset_sources(struct kvmppc_xive_src_block *sb)
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{
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int i;
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for (i = 0; i < KVMPPC_XICS_IRQ_PER_ICS; i++) {
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struct kvmppc_xive_irq_state *state = &sb->irq_state[i];
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if (!state->valid)
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continue;
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if (state->act_priority == MASKED)
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continue;
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state->eisn = 0;
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state->act_server = 0;
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state->act_priority = MASKED;
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xive_vm_esb_load(&state->ipi_data, XIVE_ESB_SET_PQ_01);
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xive_native_configure_irq(state->ipi_number, 0, MASKED, 0);
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if (state->pt_number) {
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xive_vm_esb_load(state->pt_data, XIVE_ESB_SET_PQ_01);
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xive_native_configure_irq(state->pt_number,
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0, MASKED, 0);
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}
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}
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}
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static int kvmppc_xive_reset(struct kvmppc_xive *xive)
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{
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struct kvm *kvm = xive->kvm;
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struct kvm_vcpu *vcpu;
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unsigned int i;
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pr_devel("%s\n", __func__);
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mutex_lock(&kvm->lock);
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kvm_for_each_vcpu(i, vcpu, kvm) {
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struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
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unsigned int prio;
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if (!xc)
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continue;
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kvmppc_xive_disable_vcpu_interrupts(vcpu);
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for (prio = 0; prio < KVMPPC_XIVE_Q_COUNT; prio++) {
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/* Single escalation, no queue 7 */
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if (prio == 7 && xive->single_escalation)
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break;
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if (xc->esc_virq[prio]) {
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free_irq(xc->esc_virq[prio], vcpu);
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irq_dispose_mapping(xc->esc_virq[prio]);
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kfree(xc->esc_virq_names[prio]);
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xc->esc_virq[prio] = 0;
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}
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kvmppc_xive_native_cleanup_queue(vcpu, prio);
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}
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}
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for (i = 0; i <= xive->max_sbid; i++) {
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struct kvmppc_xive_src_block *sb = xive->src_blocks[i];
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if (sb) {
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arch_spin_lock(&sb->lock);
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kvmppc_xive_reset_sources(sb);
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arch_spin_unlock(&sb->lock);
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}
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}
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mutex_unlock(&kvm->lock);
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return 0;
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}
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static int kvmppc_xive_native_set_attr(struct kvm_device *dev,
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struct kvm_device_attr *attr)
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{
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@ -579,6 +656,10 @@ static int kvmppc_xive_native_set_attr(struct kvm_device *dev,
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switch (attr->group) {
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case KVM_DEV_XIVE_GRP_CTRL:
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switch (attr->attr) {
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case KVM_DEV_XIVE_RESET:
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return kvmppc_xive_reset(xive);
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}
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break;
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case KVM_DEV_XIVE_GRP_SOURCE:
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return kvmppc_xive_native_set_source(xive, attr->attr,
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@ -611,6 +692,10 @@ static int kvmppc_xive_native_has_attr(struct kvm_device *dev,
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{
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switch (attr->group) {
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case KVM_DEV_XIVE_GRP_CTRL:
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switch (attr->attr) {
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case KVM_DEV_XIVE_RESET:
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return 0;
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}
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break;
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case KVM_DEV_XIVE_GRP_SOURCE:
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case KVM_DEV_XIVE_GRP_SOURCE_CONFIG:
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