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habanalabs: add debugfs write64/read64
Allow debug user to write/read 64-bit data through debugfs. This will expedite the dump process of the (large) internal memories of the device done during debug. Signed-off-by: Moti Haimovski <mhaimovski@habana.ai> Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
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4 changed files with 179 additions and 0 deletions
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@ -43,6 +43,20 @@ Description: Allows the root user to read or write directly through the
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If the IOMMU is disabled, it also allows the root user to read
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or write from the host a device VA of a host mapped memory
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What: /sys/kernel/debug/habanalabs/hl<n>/data64
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Date: Jan 2020
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KernelVersion: 5.6
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Contact: oded.gabbay@gmail.com
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Description: Allows the root user to read or write 64 bit data directly
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through the device's PCI bar. Writing to this file generates a
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write transaction while reading from the file generates a read
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transaction. This custom interface is needed (instead of using
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the generic Linux user-space PCI mapping) because the DDR bar
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is very small compared to the DDR memory and only the driver can
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move the bar before and after the transaction.
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If the IOMMU is disabled, it also allows the root user to read
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or write from the host a device VA of a host mapped memory
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What: /sys/kernel/debug/habanalabs/hl<n>/device
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Date: Jan 2019
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KernelVersion: 5.1
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@ -710,6 +710,65 @@ static ssize_t hl_data_write32(struct file *f, const char __user *buf,
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return count;
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}
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static ssize_t hl_data_read64(struct file *f, char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
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struct hl_device *hdev = entry->hdev;
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char tmp_buf[32];
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u64 addr = entry->addr;
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u64 val;
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ssize_t rc;
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if (*ppos)
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return 0;
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if (hl_is_device_va(hdev, addr)) {
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rc = device_va_to_pa(hdev, addr, &addr);
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if (rc)
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return rc;
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}
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rc = hdev->asic_funcs->debugfs_read64(hdev, addr, &val);
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if (rc) {
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dev_err(hdev->dev, "Failed to read from 0x%010llx\n", addr);
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return rc;
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}
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sprintf(tmp_buf, "0x%016llx\n", val);
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return simple_read_from_buffer(buf, count, ppos, tmp_buf,
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strlen(tmp_buf));
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}
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static ssize_t hl_data_write64(struct file *f, const char __user *buf,
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size_t count, loff_t *ppos)
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{
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struct hl_dbg_device_entry *entry = file_inode(f)->i_private;
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struct hl_device *hdev = entry->hdev;
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u64 addr = entry->addr;
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u64 value;
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ssize_t rc;
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rc = kstrtoull_from_user(buf, count, 16, &value);
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if (rc)
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return rc;
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if (hl_is_device_va(hdev, addr)) {
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rc = device_va_to_pa(hdev, addr, &addr);
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if (rc)
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return rc;
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}
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rc = hdev->asic_funcs->debugfs_write64(hdev, addr, value);
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if (rc) {
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dev_err(hdev->dev, "Failed to write 0x%016llx to 0x%010llx\n",
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value, addr);
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return rc;
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}
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return count;
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}
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static ssize_t hl_get_power_state(struct file *f, char __user *buf,
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size_t count, loff_t *ppos)
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{
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@ -917,6 +976,12 @@ static const struct file_operations hl_data32b_fops = {
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.write = hl_data_write32
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};
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static const struct file_operations hl_data64b_fops = {
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.owner = THIS_MODULE,
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.read = hl_data_read64,
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.write = hl_data_write64
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};
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static const struct file_operations hl_i2c_data_fops = {
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.owner = THIS_MODULE,
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.read = hl_i2c_data_read,
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@ -1030,6 +1095,12 @@ void hl_debugfs_add_device(struct hl_device *hdev)
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dev_entry,
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&hl_data32b_fops);
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debugfs_create_file("data64",
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0644,
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dev_entry->root,
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dev_entry,
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&hl_data64b_fops);
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debugfs_create_file("set_power_state",
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0200,
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dev_entry->root,
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@ -4180,6 +4180,96 @@ static int goya_debugfs_write32(struct hl_device *hdev, u64 addr, u32 val)
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return rc;
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}
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static int goya_debugfs_read64(struct hl_device *hdev, u64 addr, u64 *val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 ddr_bar_addr;
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int rc = 0;
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if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
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u32 val_l = RREG32(addr - CFG_BASE);
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u32 val_h = RREG32(addr + sizeof(u32) - CFG_BASE);
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*val = (((u64) val_h) << 32) | val_l;
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} else if ((addr >= SRAM_BASE_ADDR) &&
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(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
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*val = readq(hdev->pcie_bar[SRAM_CFG_BAR_ID] +
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(addr - SRAM_BASE_ADDR));
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} else if ((addr >= DRAM_PHYS_BASE) &&
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(addr <=
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DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64))) {
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u64 bar_base_addr = DRAM_PHYS_BASE +
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(addr & ~(prop->dram_pci_bar_size - 0x1ull));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
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if (ddr_bar_addr != U64_MAX) {
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*val = readq(hdev->pcie_bar[DDR_BAR_ID] +
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(addr - bar_base_addr));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev,
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ddr_bar_addr);
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}
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if (ddr_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
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*val = *(u64 *) phys_to_virt(addr - HOST_PHYS_BASE);
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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static int goya_debugfs_write64(struct hl_device *hdev, u64 addr, u64 val)
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{
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struct asic_fixed_properties *prop = &hdev->asic_prop;
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u64 ddr_bar_addr;
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int rc = 0;
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if ((addr >= CFG_BASE) && (addr <= CFG_BASE + CFG_SIZE - sizeof(u64))) {
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WREG32(addr - CFG_BASE, lower_32_bits(val));
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WREG32(addr + sizeof(u32) - CFG_BASE, upper_32_bits(val));
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} else if ((addr >= SRAM_BASE_ADDR) &&
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(addr <= SRAM_BASE_ADDR + SRAM_SIZE - sizeof(u64))) {
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writeq(val, hdev->pcie_bar[SRAM_CFG_BAR_ID] +
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(addr - SRAM_BASE_ADDR));
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} else if ((addr >= DRAM_PHYS_BASE) &&
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(addr <=
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DRAM_PHYS_BASE + hdev->asic_prop.dram_size - sizeof(u64))) {
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u64 bar_base_addr = DRAM_PHYS_BASE +
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(addr & ~(prop->dram_pci_bar_size - 0x1ull));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev, bar_base_addr);
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if (ddr_bar_addr != U64_MAX) {
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writeq(val, hdev->pcie_bar[DDR_BAR_ID] +
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(addr - bar_base_addr));
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ddr_bar_addr = goya_set_ddr_bar_base(hdev,
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ddr_bar_addr);
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}
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if (ddr_bar_addr == U64_MAX)
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rc = -EIO;
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} else if (addr >= HOST_PHYS_BASE && !iommu_present(&pci_bus_type)) {
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*(u64 *) phys_to_virt(addr - HOST_PHYS_BASE) = val;
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} else {
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rc = -EFAULT;
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}
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return rc;
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}
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static u64 goya_read_pte(struct hl_device *hdev, u64 addr)
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{
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struct goya_device *goya = hdev->asic_specific;
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@ -5186,6 +5276,8 @@ static const struct hl_asic_funcs goya_funcs = {
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.restore_phase_topology = goya_restore_phase_topology,
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.debugfs_read32 = goya_debugfs_read32,
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.debugfs_write32 = goya_debugfs_write32,
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.debugfs_read64 = goya_debugfs_read64,
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.debugfs_write64 = goya_debugfs_write64,
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.add_device_attr = goya_add_device_attr,
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.handle_eqe = goya_handle_eqe,
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.set_pll_profile = goya_set_pll_profile,
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@ -582,6 +582,8 @@ struct hl_asic_funcs {
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void (*restore_phase_topology)(struct hl_device *hdev);
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int (*debugfs_read32)(struct hl_device *hdev, u64 addr, u32 *val);
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int (*debugfs_write32)(struct hl_device *hdev, u64 addr, u32 val);
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int (*debugfs_read64)(struct hl_device *hdev, u64 addr, u64 *val);
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int (*debugfs_write64)(struct hl_device *hdev, u64 addr, u64 val);
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void (*add_device_attr)(struct hl_device *hdev,
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struct attribute_group *dev_attr_grp);
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void (*handle_eqe)(struct hl_device *hdev,
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