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drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers
Tiger Lake has a new register offset for DC5 and DC6 residency counters. v2: - Rename registers since they are not in the CSR memory range (requested by Anshuman) - Fix type (requested by Matthew) Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190726002412.5827-2-lucas.demarchi@intel.com
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01158da721
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2 changed files with 15 additions and 8 deletions
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@ -2465,6 +2465,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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intel_wakeref_t wakeref;
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struct intel_csr *csr;
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i915_reg_t dc5_reg, dc6_reg = {};
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if (!HAS_CSR(dev_priv))
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return -ENODEV;
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@ -2482,15 +2483,19 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
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seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
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CSR_VERSION_MINOR(csr->version));
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if (WARN_ON(INTEL_GEN(dev_priv) > 11))
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goto out;
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if (INTEL_GEN(dev_priv) >= 12) {
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dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
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dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
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} else {
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dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
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SKL_CSR_DC3_DC5_COUNT;
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if (!IS_GEN9_LP(dev_priv))
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dc6_reg = SKL_CSR_DC5_DC6_COUNT;
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}
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seq_printf(m, "DC3 -> DC5 count: %d\n",
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I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
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SKL_CSR_DC3_DC5_COUNT));
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if (!IS_GEN9_LP(dev_priv))
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seq_printf(m, "DC5 -> DC6 count: %d\n",
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I915_READ(SKL_CSR_DC5_DC6_COUNT));
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seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg));
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if (dc6_reg.reg)
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seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg));
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out:
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seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
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@ -7271,6 +7271,8 @@ enum {
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#define SKL_CSR_DC3_DC5_COUNT _MMIO(0x80030)
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#define SKL_CSR_DC5_DC6_COUNT _MMIO(0x8002C)
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#define BXT_CSR_DC3_DC5_COUNT _MMIO(0x80038)
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#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
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#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
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/* interrupts */
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#define DE_MASTER_IRQ_CONTROL (1 << 31)
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