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remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout 

The MT8195 SCP core 1 watchdog timeout needs to be handled in the
SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout
IRQ is wired on the same IRQ entry for core 0 watchdog timeout.
MT8195 SCP has a watchdog status register to identify the watchdog
timeout source when IRQ triggered.

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230901080935.14571-12-tinghan.shen@mediatek.com
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
This commit is contained in:
Tinghan Shen 2023-09-01 16:09:32 +08:00 committed by Mathieu Poirier
parent c01fb97cf2
commit 5d5cfce480
2 changed files with 29 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/remoteproc/mtk_common.h
View File

@ -55,6 +55,10 @@
#define MT8192_CORE0_WDT_IRQ 0x10030
#define MT8192_CORE0_WDT_CFG 0x10034
#define MT8195_SYS_STATUS 0x4004
#define MT8195_CORE0_WDT BIT(16)
#define MT8195_CORE1_WDT BIT(17)
#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
#define MT8195_CPU1_SRAM_PD 0x1084
@ -63,6 +67,7 @@
#define MT8195_CORE1_SW_RSTN_CLR 0x20000
#define MT8195_CORE1_SW_RSTN_SET 0x20004
#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
#define MT8195_CORE1_WDT_IRQ 0x20030
#define MT8195_CORE1_WDT_CFG 0x20034
#define MT8195_SEC_CTRL 0x85000

25
drivers/remoteproc/mtk_scp.c
View File

@ -222,6 +222,29 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
}
}
static void mt8195_scp_irq_handler(struct mtk_scp *scp)
{
u32 scp_to_host;
scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET);
if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
scp_ipi_handler(scp);
} else {
u32 reason = readl(scp->cluster->reg_base + MT8195_SYS_STATUS);
if (reason & MT8195_CORE0_WDT)
writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
if (reason & MT8195_CORE1_WDT)
writel(1, scp->cluster->reg_base + MT8195_CORE1_WDT_IRQ);
scp_wdt_handler(scp, reason);
}
writel(scp_to_host, scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR);
}
static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp)
{
u32 scp_to_host;
@ -1256,7 +1279,7 @@ static const struct mtk_scp_of_data mt8192_of_data = {
static const struct mtk_scp_of_data mt8195_of_data = {
.scp_clk_get = mt8195_scp_clk_get,
.scp_before_load = mt8195_scp_before_load,
.scp_irq_handler = mt8192_scp_irq_handler,
.scp_irq_handler = mt8195_scp_irq_handler,
.scp_reset_assert = mt8192_scp_reset_assert,
.scp_reset_deassert = mt8192_scp_reset_deassert,
.scp_stop = mt8195_scp_stop,