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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 02:39:48 +00:00
net: ethernet: ti: cpsw: move links on h/w registers to cpsw_common
The pointers on h/w registers are common for every cpsw_private instance, so no need to hold them for every ndev. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@linaro.org> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
56e31bd893
commit
5d8d0d4d46
1 changed files with 53 additions and 44 deletions
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@ -365,6 +365,10 @@ static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
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struct cpsw_common {
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struct device *dev;
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struct cpsw_ss_regs __iomem *regs;
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struct cpsw_wr_regs __iomem *wr_regs;
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u8 __iomem *hw_stats;
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struct cpsw_host_regs __iomem *host_port_regs;
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};
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struct cpsw_priv {
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@ -373,10 +377,6 @@ struct cpsw_priv {
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struct napi_struct napi_tx;
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struct device *dev;
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struct cpsw_platform_data data;
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struct cpsw_ss_regs __iomem *regs;
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struct cpsw_wr_regs __iomem *wr_regs;
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u8 __iomem *hw_stats;
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struct cpsw_host_regs __iomem *host_port_regs;
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u32 msg_enable;
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u32 version;
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u32 coal_intvl;
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@ -656,8 +656,10 @@ static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
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static void cpsw_intr_enable(struct cpsw_priv *priv)
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{
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__raw_writel(0xFF, &priv->wr_regs->tx_en);
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__raw_writel(0xFF, &priv->wr_regs->rx_en);
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struct cpsw_common *cpsw = priv->cpsw;
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__raw_writel(0xFF, &cpsw->wr_regs->tx_en);
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__raw_writel(0xFF, &cpsw->wr_regs->rx_en);
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cpdma_ctlr_int_ctrl(priv->dma, true);
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return;
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@ -665,8 +667,10 @@ static void cpsw_intr_enable(struct cpsw_priv *priv)
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static void cpsw_intr_disable(struct cpsw_priv *priv)
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{
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__raw_writel(0, &priv->wr_regs->tx_en);
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__raw_writel(0, &priv->wr_regs->rx_en);
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struct cpsw_common *cpsw = priv->cpsw;
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__raw_writel(0, &cpsw->wr_regs->tx_en);
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__raw_writel(0, &cpsw->wr_regs->rx_en);
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cpdma_ctlr_int_ctrl(priv->dma, false);
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return;
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@ -750,8 +754,9 @@ static void cpsw_rx_handler(void *token, int len, int status)
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static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
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{
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struct cpsw_priv *priv = dev_id;
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struct cpsw_common *cpsw = priv->cpsw;
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writel(0, &priv->wr_regs->tx_en);
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writel(0, &cpsw->wr_regs->tx_en);
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cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
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if (priv->quirk_irq) {
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@ -766,9 +771,10 @@ static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
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static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
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{
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struct cpsw_priv *priv = dev_id;
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struct cpsw_common *cpsw = priv->cpsw;
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cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
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writel(0, &priv->wr_regs->rx_en);
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writel(0, &cpsw->wr_regs->rx_en);
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if (priv->quirk_irq) {
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disable_irq_nosync(priv->irqs_table[0]);
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@ -783,11 +789,12 @@ static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
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{
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struct cpsw_priv *priv = napi_to_priv(napi_tx);
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int num_tx;
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struct cpsw_common *cpsw = priv->cpsw;
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num_tx = cpdma_chan_process(priv->txch, budget);
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if (num_tx < budget) {
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napi_complete(napi_tx);
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writel(0xff, &priv->wr_regs->tx_en);
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writel(0xff, &cpsw->wr_regs->tx_en);
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if (priv->quirk_irq && priv->tx_irq_disabled) {
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priv->tx_irq_disabled = false;
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enable_irq(priv->irqs_table[1]);
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@ -801,11 +808,12 @@ static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
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{
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struct cpsw_priv *priv = napi_to_priv(napi_rx);
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int num_rx;
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struct cpsw_common *cpsw = priv->cpsw;
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num_rx = cpdma_chan_process(priv->rxch, budget);
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if (num_rx < budget) {
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napi_complete(napi_rx);
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writel(0xff, &priv->wr_regs->rx_en);
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writel(0xff, &cpsw->wr_regs->rx_en);
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if (priv->quirk_irq && priv->rx_irq_disabled) {
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priv->rx_irq_disabled = false;
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enable_irq(priv->irqs_table[0]);
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@ -925,10 +933,11 @@ static int cpsw_set_coalesce(struct net_device *ndev,
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u32 prescale = 0;
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u32 addnl_dvdr = 1;
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u32 coal_intvl = 0;
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struct cpsw_common *cpsw = priv->cpsw;
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coal_intvl = coal->rx_coalesce_usecs;
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int_ctrl = readl(&priv->wr_regs->int_control);
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int_ctrl = readl(&cpsw->wr_regs->int_control);
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prescale = priv->bus_freq_mhz * 4;
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if (!coal->rx_coalesce_usecs) {
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@ -957,15 +966,15 @@ static int cpsw_set_coalesce(struct net_device *ndev,
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}
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num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
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writel(num_interrupts, &priv->wr_regs->rx_imax);
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writel(num_interrupts, &priv->wr_regs->tx_imax);
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writel(num_interrupts, &cpsw->wr_regs->rx_imax);
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writel(num_interrupts, &cpsw->wr_regs->tx_imax);
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int_ctrl |= CPSW_INTPACEEN;
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int_ctrl &= (~CPSW_INTPRESCALE_MASK);
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int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
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update_return:
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writel(int_ctrl, &priv->wr_regs->int_control);
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writel(int_ctrl, &cpsw->wr_regs->int_control);
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cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
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if (priv->data.dual_emac) {
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@ -1017,6 +1026,7 @@ static void cpsw_get_ethtool_stats(struct net_device *ndev,
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u32 val;
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u8 *p;
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int i;
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struct cpsw_common *cpsw = priv->cpsw;
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/* Collect Davinci CPDMA stats for Rx and Tx Channel */
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cpdma_chan_get_stats(priv->rxch, &rx_stats);
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@ -1025,7 +1035,7 @@ static void cpsw_get_ethtool_stats(struct net_device *ndev,
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for (i = 0; i < CPSW_STATS_LEN; i++) {
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switch (cpsw_gstrings_stats[i].type) {
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case CPSW_STATS:
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val = readl(priv->hw_stats +
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val = readl(cpsw->hw_stats +
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cpsw_gstrings_stats[i].stat_offset);
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data[i] = val;
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break;
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@ -1164,11 +1174,12 @@ static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
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u32 reg;
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int i;
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int unreg_mcast_mask;
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struct cpsw_common *cpsw = priv->cpsw;
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reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
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CPSW2_PORT_VLAN;
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writel(vlan, &priv->host_port_regs->port_vlan);
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writel(vlan, &cpsw->host_port_regs->port_vlan);
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for (i = 0; i < priv->data.slaves; i++)
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slave_write(priv->slaves + i, vlan, reg);
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@ -1185,27 +1196,28 @@ static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
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static void cpsw_init_host_port(struct cpsw_priv *priv)
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{
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u32 control_reg;
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u32 fifo_mode;
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u32 control_reg;
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struct cpsw_common *cpsw = priv->cpsw;
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/* soft reset the controller and initialize ale */
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soft_reset("cpsw", &priv->regs->soft_reset);
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soft_reset("cpsw", &cpsw->regs->soft_reset);
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cpsw_ale_start(priv->ale);
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/* switch to vlan unaware mode */
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cpsw_ale_control_set(priv->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
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CPSW_ALE_VLAN_AWARE);
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control_reg = readl(&priv->regs->control);
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control_reg = readl(&cpsw->regs->control);
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control_reg |= CPSW_VLAN_AWARE;
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writel(control_reg, &priv->regs->control);
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writel(control_reg, &cpsw->regs->control);
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fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
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CPSW_FIFO_NORMAL_MODE;
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writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
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writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
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/* setup host port priority mapping */
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__raw_writel(CPDMA_TX_PRIORITY_MAP,
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&priv->host_port_regs->cpdma_tx_pri_map);
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__raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
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&cpsw->host_port_regs->cpdma_tx_pri_map);
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__raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
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cpsw_ale_control_set(priv->ale, HOST_PORT_NUM,
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ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
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cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
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/* disable priority elevation */
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__raw_writel(0, &priv->regs->ptype);
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__raw_writel(0, &cpsw->regs->ptype);
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/* enable statistics collection only on all ports */
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__raw_writel(0x7, &priv->regs->stat_port_en);
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__raw_writel(0x7, &cpsw->regs->stat_port_en);
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/* Enable internal fifo flow control */
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writel(0x7, &priv->regs->flow_control);
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writel(0x7, &cpsw->regs->flow_control);
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napi_enable(&priv_sl0->napi_rx);
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napi_enable(&priv_sl0->napi_tx);
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@ -1443,6 +1455,7 @@ static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
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static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
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{
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struct cpsw_slave *slave;
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struct cpsw_common *cpsw = priv->cpsw;
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u32 ctrl, mtype;
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if (priv->data.dual_emac)
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@ -1477,7 +1490,7 @@ static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
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slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
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slave_write(slave, ctrl, CPSW2_CONTROL);
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__raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
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__raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
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}
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static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
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@ -1980,7 +1993,8 @@ static const struct ethtool_ops cpsw_ethtool_ops = {
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static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
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u32 slave_reg_ofs, u32 sliver_reg_ofs)
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{
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void __iomem *regs = priv->regs;
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struct cpsw_common *cpsw = priv->cpsw;
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void __iomem *regs = cpsw->regs;
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int slave_num = slave->slave_num;
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struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
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@ -2190,11 +2204,6 @@ static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
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priv_sl2->slaves = priv->slaves;
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priv_sl2->coal_intvl = 0;
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priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
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priv_sl2->regs = priv->regs;
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priv_sl2->host_port_regs = priv->host_port_regs;
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priv_sl2->wr_regs = priv->wr_regs;
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priv_sl2->hw_stats = priv->hw_stats;
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priv_sl2->dma = priv->dma;
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priv_sl2->txch = priv->txch;
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priv_sl2->rxch = priv->rxch;
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@ -2363,7 +2372,7 @@ static int cpsw_probe(struct platform_device *pdev)
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ret = PTR_ERR(ss_regs);
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goto clean_runtime_disable_ret;
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}
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priv->regs = ss_regs;
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cpsw->regs = ss_regs;
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/* Need to enable clocks with runtime PM api to access module
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* registers
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@ -2373,13 +2382,13 @@ static int cpsw_probe(struct platform_device *pdev)
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pm_runtime_put_noidle(&pdev->dev);
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goto clean_runtime_disable_ret;
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}
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priv->version = readl(&priv->regs->id_ver);
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priv->version = readl(&cpsw->regs->id_ver);
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pm_runtime_put_sync(&pdev->dev);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->wr_regs)) {
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ret = PTR_ERR(priv->wr_regs);
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cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(cpsw->wr_regs)) {
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ret = PTR_ERR(cpsw->wr_regs);
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goto clean_runtime_disable_ret;
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}
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@ -2388,9 +2397,9 @@ static int cpsw_probe(struct platform_device *pdev)
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switch (priv->version) {
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case CPSW_VERSION_1:
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priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
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cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
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priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
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priv->hw_stats = ss_regs + CPSW1_HW_STATS;
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cpsw->hw_stats = ss_regs + CPSW1_HW_STATS;
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dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
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dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
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ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
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case CPSW_VERSION_2:
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case CPSW_VERSION_3:
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case CPSW_VERSION_4:
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priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
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cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
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priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
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priv->hw_stats = ss_regs + CPSW2_HW_STATS;
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cpsw->hw_stats = ss_regs + CPSW2_HW_STATS;
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dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
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dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
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ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
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