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drm/amd/pp: Add and initialize OD_dpm_table for CI/VI.
Add initial infrastructure for manual dpm control. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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2 changed files with 89 additions and 0 deletions
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@ -793,6 +793,76 @@ static int smu7_setup_dpm_tables_v1(struct pp_hwmgr *hwmgr)
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return 0;
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}
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static int smu7_get_voltage_dependency_table(
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const struct phm_ppt_v1_clock_voltage_dependency_table *allowed_dep_table,
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_table)
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{
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uint8_t i = 0;
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PP_ASSERT_WITH_CODE((0 != allowed_dep_table->count),
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"Voltage Lookup Table empty",
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return -EINVAL);
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dep_table->count = allowed_dep_table->count;
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for (i=0; i<dep_table->count; i++) {
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dep_table->entries[i].clk = allowed_dep_table->entries[i].clk;
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dep_table->entries[i].vddInd = allowed_dep_table->entries[i].vddInd;
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dep_table->entries[i].vdd_offset = allowed_dep_table->entries[i].vdd_offset;
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dep_table->entries[i].vddc = allowed_dep_table->entries[i].vddc;
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dep_table->entries[i].vddgfx = allowed_dep_table->entries[i].vddgfx;
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dep_table->entries[i].vddci = allowed_dep_table->entries[i].vddci;
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dep_table->entries[i].mvdd = allowed_dep_table->entries[i].mvdd;
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dep_table->entries[i].phases = allowed_dep_table->entries[i].phases;
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dep_table->entries[i].cks_enable = allowed_dep_table->entries[i].cks_enable;
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dep_table->entries[i].cks_voffset = allowed_dep_table->entries[i].cks_voffset;
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}
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return 0;
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}
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static int smu7_odn_initial_default_setting(struct pp_hwmgr *hwmgr)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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struct smu7_odn_dpm_table *odn_table = &(data->odn_dpm_table);
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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uint32_t i;
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_sclk_table;
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struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table;
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if (table_info == NULL)
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return -EINVAL;
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dep_sclk_table = table_info->vdd_dep_on_sclk;
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dep_mclk_table = table_info->vdd_dep_on_mclk;
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odn_table->odn_core_clock_dpm_levels.num_of_pl =
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data->golden_dpm_table.sclk_table.count;
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for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
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odn_table->odn_core_clock_dpm_levels.entries[i].clock =
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data->golden_dpm_table.sclk_table.dpm_levels[i].value;
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odn_table->odn_core_clock_dpm_levels.entries[i].enabled = true;
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odn_table->odn_core_clock_dpm_levels.entries[i].vddc = dep_sclk_table->entries[i].vddc;
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}
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smu7_get_voltage_dependency_table(dep_sclk_table,
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(struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_sclk));
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odn_table->odn_memory_clock_dpm_levels.num_of_pl =
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data->golden_dpm_table.mclk_table.count;
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for (i=0; i<data->golden_dpm_table.sclk_table.count; i++) {
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odn_table->odn_memory_clock_dpm_levels.entries[i].clock =
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data->golden_dpm_table.mclk_table.dpm_levels[i].value;
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odn_table->odn_memory_clock_dpm_levels.entries[i].enabled = true;
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odn_table->odn_memory_clock_dpm_levels.entries[i].vddc = dep_mclk_table->entries[i].vddc;
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}
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smu7_get_voltage_dependency_table(dep_mclk_table,
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(struct phm_ppt_v1_clock_voltage_dependency_table *)&(odn_table->vdd_dependency_on_mclk));
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return 0;
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}
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static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
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{
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struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
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@ -809,6 +879,11 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
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/* save a copy of the default DPM table */
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memcpy(&(data->golden_dpm_table), &(data->dpm_table),
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sizeof(struct smu7_dpm_table));
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/* initialize ODN table */
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if (hwmgr->od_enabled)
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smu7_odn_initial_default_setting(hwmgr);
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return 0;
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}
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@ -173,9 +173,23 @@ struct smu7_pcie_perf_range {
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uint16_t min;
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};
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struct smu7_odn_clock_voltage_dependency_table {
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uint32_t count;
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phm_ppt_v1_clock_voltage_dependency_record entries[MAX_REGULAR_DPM_NUMBER];
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};
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struct smu7_odn_dpm_table {
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struct phm_odn_clock_levels odn_core_clock_dpm_levels;
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struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
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struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
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struct smu7_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
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uint32_t odn_mclk_min_limit;
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};
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struct smu7_hwmgr {
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struct smu7_dpm_table dpm_table;
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struct smu7_dpm_table golden_dpm_table;
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struct smu7_odn_dpm_table odn_dpm_table;
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uint32_t voting_rights_clients[8];
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uint32_t static_screen_threshold_unit;
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