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drm/i915: remove GRAPHICS_VER == 10
Replace all remaining handling of GRAPHICS_VER {==,>=} 10 with {==,>=} 11. With the removal of CNL, there is no platform with graphics version equals 10. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210728215946.1573015-24-lucas.demarchi@intel.com
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parent
4c6b302121
commit
5dae69a9fd
5 changed files with 13 additions and 19 deletions
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@ -447,7 +447,6 @@ static int i915_gem_init_stolen(struct intel_memory_region *mem)
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break;
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case 8:
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case 9:
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case 10:
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if (IS_LP(i915))
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chv_get_stolen_reserved(i915, uncore,
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&reserved_base, &reserved_size);
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@ -1055,7 +1055,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
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if (GRAPHICS_VER(dev_priv) == 9 || GRAPHICS_VER(dev_priv) == 10) {
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if (GRAPHICS_VER(dev_priv) == 9) {
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u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
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GAMW_ECO_ENABLE_64K_IPS_FIELD;
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@ -538,20 +538,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
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max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
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rp_state_cap >> 16) & 0xff;
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max_freq *= (IS_GEN9_BC(dev_priv) ||
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GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
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GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
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intel_gpu_freq(rps, max_freq));
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max_freq = (rp_state_cap & 0xff00) >> 8;
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max_freq *= (IS_GEN9_BC(dev_priv) ||
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GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
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GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
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intel_gpu_freq(rps, max_freq));
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max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
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rp_state_cap >> 0) & 0xff;
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max_freq *= (IS_GEN9_BC(dev_priv) ||
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GRAPHICS_VER(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
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GRAPHICS_VER(dev_priv) >= 11 ? GEN9_FREQ_SCALER : 1);
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seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
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intel_gpu_freq(rps, max_freq));
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seq_printf(m, "Max overclocked frequency: %dMHz\n",
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@ -1597,7 +1597,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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IS_SKL_GT4(dev_priv))
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#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
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#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 10 || \
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#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
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IS_GEMINILAKE(dev_priv) || \
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IS_KABYLAKE(dev_priv))
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@ -1256,7 +1256,6 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
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case 8:
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case 9:
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case 10:
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if (intel_engine_uses_guc(ce->engine)) {
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/*
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* When using GuC, the context descriptor we write in
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@ -2580,7 +2579,7 @@ static void gen8_disable_metric_set(struct i915_perf_stream *stream)
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intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
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}
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static void gen10_disable_metric_set(struct i915_perf_stream *stream)
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static void gen11_disable_metric_set(struct i915_perf_stream *stream)
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{
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struct intel_uncore *uncore = stream->uncore;
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@ -3887,7 +3886,7 @@ static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
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REG_IN_RANGE(addr, RPM_CONFIG0, NOA_CONFIG(8));
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}
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static bool gen10_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
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static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
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{
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return gen8_is_valid_mux_addr(perf, addr) ||
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REG_EQUAL(addr, GEN10_NOA_WRITE_HIGH) ||
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@ -4395,27 +4394,23 @@ void i915_perf_init(struct drm_i915_private *i915)
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perf->gen8_valid_ctx_bit = BIT(16);
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}
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} else if (IS_GRAPHICS_VER(i915, 10, 11)) {
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} else if (GRAPHICS_VER(i915) == 11) {
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perf->ops.is_valid_b_counter_reg =
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gen7_is_valid_b_counter_addr;
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perf->ops.is_valid_mux_reg =
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gen10_is_valid_mux_addr;
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gen11_is_valid_mux_addr;
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perf->ops.is_valid_flex_reg =
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gen8_is_valid_flex_addr;
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perf->ops.oa_enable = gen8_oa_enable;
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perf->ops.oa_disable = gen8_oa_disable;
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perf->ops.enable_metric_set = gen8_enable_metric_set;
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perf->ops.disable_metric_set = gen10_disable_metric_set;
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perf->ops.disable_metric_set = gen11_disable_metric_set;
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perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
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if (GRAPHICS_VER(i915) == 10) {
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perf->ctx_oactxctrl_offset = 0x128;
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perf->ctx_flexeu0_offset = 0x3de;
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} else {
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perf->ctx_oactxctrl_offset = 0x124;
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perf->ctx_flexeu0_offset = 0x78e;
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}
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perf->ctx_oactxctrl_offset = 0x124;
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perf->ctx_flexeu0_offset = 0x78e;
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perf->gen8_valid_ctx_bit = BIT(16);
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} else if (GRAPHICS_VER(i915) == 12) {
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perf->ops.is_valid_b_counter_reg =
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