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KVM: selftests: Convert AMX test to use X86_PROPRETY_XXX

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Add and use x86 "properties" for the myriad AMX CPUID values that are
validated by the AMX test.  Drop most of the test's single-usage
helpers so that the asserts more precisely capture what check failed.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Link: https://lore.kernel.org/r/20221006005125.680782-8-seanjc@google.com
This commit is contained in:
Sean Christopherson 2022-10-06 00:51:20 +00:00
parent 40854713e3
commit 5dc19f1c7d
2 changed files with 31 additions and 79 deletions
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9
tools/testing/selftests/kvm/include/x86_64/processor.h
View file

@ -200,6 +200,15 @@ struct kvm_x86_cpu_property {
})
#define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31)
#define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31)
#define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31)
#define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31)
#define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31)
#define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15)
#define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
#define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15)
#define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31)
#define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15)
#define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31)

101
tools/testing/selftests/kvm/x86_64/amx_test.c
View file

@ -39,11 +39,6 @@
#define XFEATURE_MASK_XTILEDATA (1 << XFEATURE_XTILEDATA)
#define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILECFG | XFEATURE_MASK_XTILEDATA)
#define TILE_CPUID 0x1d
#define XSTATE_CPUID 0xd
#define TILE_PALETTE_CPUID_SUBLEAVE 0x1
#define XSTATE_USER_STATE_SUBLEAVE 0x0
#define XSAVE_HDR_OFFSET 512
struct xsave_data {
@ -129,71 +124,26 @@ static bool check_xsave_supports_xtile(void)
return __xgetbv(0) & XFEATURE_MASK_XTILE;
}
static bool enum_xtile_config(void)
static void check_xtile_info(void)
{
u32 eax, ebx, ecx, edx;
GUEST_ASSERT(this_cpu_has_p(X86_PROPERTY_XSTATE_MAX_SIZE_XCR0));
GUEST_ASSERT(this_cpu_property(X86_PROPERTY_XSTATE_MAX_SIZE_XCR0) <= XSAVE_SIZE);
__cpuid(TILE_CPUID, TILE_PALETTE_CPUID_SUBLEAVE, &eax, &ebx, &ecx, &edx);
if (!eax || !ebx || !ecx)
return false;
xtile.xsave_offset = this_cpu_property(X86_PROPERTY_XSTATE_TILE_OFFSET);
GUEST_ASSERT(xtile.xsave_offset == 2816);
xtile.xsave_size = this_cpu_property(X86_PROPERTY_XSTATE_TILE_SIZE);
GUEST_ASSERT(xtile.xsave_size == 8192);
GUEST_ASSERT(sizeof(struct tile_data) >= xtile.xsave_size);
xtile.max_names = ebx >> 16;
if (xtile.max_names < NUM_TILES)
return false;
xtile.bytes_per_tile = eax >> 16;
if (xtile.bytes_per_tile < TILE_SIZE)
return false;
xtile.bytes_per_row = ebx;
xtile.max_rows = ecx;
return true;
}
static bool enum_xsave_tile(void)
{
u32 eax, ebx, ecx, edx;
__cpuid(XSTATE_CPUID, XFEATURE_XTILEDATA, &eax, &ebx, &ecx, &edx);
if (!eax || !ebx)
return false;
xtile.xsave_offset = ebx;
xtile.xsave_size = eax;
return true;
}
static bool check_xsave_size(void)
{
u32 eax, ebx, ecx, edx;
bool valid = false;
__cpuid(XSTATE_CPUID, XSTATE_USER_STATE_SUBLEAVE, &eax, &ebx, &ecx, &edx);
if (ebx && ebx <= XSAVE_SIZE)
valid = true;
return valid;
}
static bool check_xtile_info(void)
{
bool ret = false;
if (!check_xsave_size())
return ret;
if (!enum_xsave_tile())
return ret;
if (!enum_xtile_config())
return ret;
if (sizeof(struct tile_data) >= xtile.xsave_size)
ret = true;
return ret;
GUEST_ASSERT(this_cpu_has_p(X86_PROPERTY_AMX_NR_TILE_REGS));
xtile.max_names = this_cpu_property(X86_PROPERTY_AMX_NR_TILE_REGS);
GUEST_ASSERT(xtile.max_names == 8);
xtile.bytes_per_tile = this_cpu_property(X86_PROPERTY_AMX_BYTES_PER_TILE);
GUEST_ASSERT(xtile.bytes_per_tile == 1024);
xtile.bytes_per_row = this_cpu_property(X86_PROPERTY_AMX_BYTES_PER_ROW);
GUEST_ASSERT(xtile.bytes_per_row == 64);
xtile.max_rows = this_cpu_property(X86_PROPERTY_AMX_MAX_ROWS);
GUEST_ASSERT(xtile.max_rows == 16);
}
static void set_tilecfg(struct tile_config *cfg)
@ -238,16 +188,8 @@ static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
{
init_regs();
check_cpuid_xsave();
GUEST_ASSERT(check_xsave_supports_xtile());
GUEST_ASSERT(check_xtile_info());
/* check xtile configs */
GUEST_ASSERT(xtile.xsave_offset == 2816);
GUEST_ASSERT(xtile.xsave_size == 8192);
GUEST_ASSERT(xtile.max_names == 8);
GUEST_ASSERT(xtile.bytes_per_tile == 1024);
GUEST_ASSERT(xtile.bytes_per_row == 64);
GUEST_ASSERT(xtile.max_rows == 16);
check_xsave_supports_xtile();
check_xtile_info();
GUEST_SYNC(1);
/* xfd=0, enable amx */
@ -317,8 +259,9 @@ int main(int argc, char *argv[])
TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XTILECFG));
TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XTILEDATA));
/* Get xsave/restore max size */
xsave_restore_size = kvm_get_supported_cpuid_entry(0xd)->ecx;
TEST_ASSERT(kvm_cpu_has_p(X86_PROPERTY_XSTATE_MAX_SIZE),
"KVM should enumerate max XSAVE size when XSAVE is supported");
xsave_restore_size = kvm_cpu_property(X86_PROPERTY_XSTATE_MAX_SIZE);
run = vcpu->run;
vcpu_regs_get(vcpu, &regs1);