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net/mlx5: Expose MPEGC (Management PCIe General Configuration) structures
This patch exposes PRM layout for handling MPEGC (Management PCIe General Configuration). This will be used in the downstream patch for configuring MPEGC via the driver. Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com> Reviewed-by: Moshe Shemesh <moshe@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
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eff8ea8f24
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2 changed files with 22 additions and 2 deletions
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@ -145,6 +145,7 @@ enum {
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MLX5_REG_MPCNT = 0x9051,
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MLX5_REG_MPCNT = 0x9051,
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MLX5_REG_MTPPS = 0x9053,
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MLX5_REG_MTPPS = 0x9053,
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MLX5_REG_MTPPSE = 0x9054,
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MLX5_REG_MTPPSE = 0x9054,
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MLX5_REG_MPEGC = 0x9056,
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MLX5_REG_MCQI = 0x9061,
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MLX5_REG_MCQI = 0x9061,
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MLX5_REG_MCC = 0x9062,
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MLX5_REG_MCC = 0x9062,
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MLX5_REG_MCDA = 0x9063,
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MLX5_REG_MCDA = 0x9063,
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@ -8049,6 +8049,19 @@ struct mlx5_ifc_peir_reg_bits {
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u8 error_type[0x8];
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u8 error_type[0x8];
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};
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};
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struct mlx5_ifc_mpegc_reg_bits {
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u8 reserved_at_0[0x30];
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u8 field_select[0x10];
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u8 tx_overflow_sense[0x1];
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u8 mark_cqe[0x1];
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u8 mark_cnp[0x1];
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u8 reserved_at_43[0x1b];
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u8 tx_lossy_overflow_oper[0x2];
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u8 reserved_at_60[0x100];
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};
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struct mlx5_ifc_pcam_enhanced_features_bits {
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struct mlx5_ifc_pcam_enhanced_features_bits {
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u8 reserved_at_0[0x6d];
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u8 reserved_at_0[0x6d];
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u8 rx_icrc_encapsulated_counter[0x1];
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u8 rx_icrc_encapsulated_counter[0x1];
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@ -8097,7 +8110,11 @@ struct mlx5_ifc_pcam_reg_bits {
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};
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};
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struct mlx5_ifc_mcam_enhanced_features_bits {
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struct mlx5_ifc_mcam_enhanced_features_bits {
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u8 reserved_at_0[0x7b];
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u8 reserved_at_0[0x74];
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u8 mark_tx_action_cnp[0x1];
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u8 mark_tx_action_cqe[0x1];
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u8 dynamic_tx_overflow[0x1];
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u8 reserved_at_77[0x4];
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u8 pcie_outbound_stalled[0x1];
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u8 pcie_outbound_stalled[0x1];
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u8 tx_overflow_buffer_pkt[0x1];
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u8 tx_overflow_buffer_pkt[0x1];
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u8 mtpps_enh_out_per_adj[0x1];
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u8 mtpps_enh_out_per_adj[0x1];
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@ -8112,7 +8129,9 @@ struct mlx5_ifc_mcam_access_reg_bits {
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u8 mcqi[0x1];
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u8 mcqi[0x1];
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u8 reserved_at_1f[0x1];
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u8 reserved_at_1f[0x1];
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u8 regs_95_to_68[0x1c];
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u8 regs_95_to_87[0x9];
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u8 mpegc[0x1];
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u8 regs_85_to_68[0x12];
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u8 tracer_registers[0x4];
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u8 tracer_registers[0x4];
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u8 regs_63_to_32[0x20];
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u8 regs_63_to_32[0x20];
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