mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-21 08:19:28 +00:00
amdgpu and panel/misc fixes.
-----BEGIN PGP SIGNATURE----- iQIbBAABAgAGBQJbf4GtAAoJEAx081l5xIa+WzsP8gNAadlpbPP3zmMoVwCKPeOR YZBeJxc/C9EXR8PfsMzo5kuUFm6rf7F9hYCaqmJj+exKCEGSwRAsHxBk2Ll9PbHm 7iFf7HjnGlU6swRtHOniLV2c1XxyUJGafkHBET6/SarqHfTW3QvaGTAxAKmxpNSr qY7m1SyU1JKV2sw9N4xODLMRvoG/Y0OaiAgzOkUTbrSNomCfWVTGV/Pat7pDh/3z jbeeTGaMLYJISKWBMfTeN4lxex+b2txGAMBs5OQvwetD4bvsstbp1tdkB7KNmISm RrOJOTlD2ZhZ/Yo2i3JETa3v6nhAw6+zeOq7o/eiBtnkKSYb57hL42toKx/k4YV4 pdTnkImrYtVOzFj39MvByISSD0XaM7nuP769DkGsRjlPa1O5LnpDcawsNuc+brqY wQQ/CBhh614YfTcQKRoKkeZSr5CjuQILwX5VVQFiL7DJaHXpfqK7IXUQ99zF1SF+ V9Byb6BZpfDYEsN9biqxGTqIYEs8FWi9NP7uK8vQeMaT+9P5/ntVQVIfl5rhp3W8 RtZc1F5NBVc3XTJOcgpcfyM5gz7L31NDHbWRxgIsCMWDFfmTxxSirJSc8EE+2fqn EtNzuzcVKBmTvUrcQsuclC4iymDAOnCjSwdSVTg19loi84y9UKx7BIg1pqYku3hA Yihn27r0Ftyd4cXdgu4= =kMpO -----END PGP SIGNATURE----- Merge tag 'drm-next-2018-08-24' of git://anongit.freedesktop.org/drm/drm Pull drm fixes from Dave Airlie: "Just a couple of fixes" One MAINTAINERS address change, two panels fixes, and set of amdgpu fixes (build fixes, display fixes and some others)" * tag 'drm-next-2018-08-24' of git://anongit.freedesktop.org/drm/drm: drm/edid: Add 6 bpc quirk for SDC panel in Lenovo B50-80 drm/amd/display: Don't build DCN1 when kcov is enabled Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86" drm/amdgpu/display: disable eDP fast boot optimization on DCE8 drm/amdgpu: fix amdgpu_amdkfd_remove_eviction_fence v3 drm/amdgpu: fix incorrect use of drm_file->pid drm/amdgpu: fix incorrect use of fcheck drm/powerplay: enable dpm under pass-through drm/amdgpu: access register without KIQ drm/amdgpu: set correct base for THM/NBIF/MP1 IP drm/amd/display: fix dentist did ranges drm/amd/display: make dp_ss_off optional drm/amd/display: fix dp_ss_control vbios flag parsing drm/amd/display: Do not retain link settings MAINTAINERS: drm-misc: Change seanpaul's email address drm/panel: simple: tv123wam: Add unprepare delay
This commit is contained in:
commit
5e8704ac1c
35 changed files with 166 additions and 147 deletions
|
@ -4752,7 +4752,7 @@ F: include/linux/vga*
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DRM DRIVERS AND MISC GPU PATCHES
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M: Gustavo Padovan <gustavo@padovan.org>
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M: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
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M: Sean Paul <seanpaul@chromium.org>
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M: Sean Paul <sean@poorly.run>
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W: https://01.org/linuxgraphics/gfx-docs/maintainer-tools/drm-misc.html
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S: Maintained
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T: git git://anongit.freedesktop.org/drm/drm-misc
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@ -206,11 +206,9 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
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struct amdgpu_amdkfd_fence ***ef_list,
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unsigned int *ef_count)
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{
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struct reservation_object_list *fobj;
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struct reservation_object *resv;
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unsigned int i = 0, j = 0, k = 0, shared_count;
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unsigned int count = 0;
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struct amdgpu_amdkfd_fence **fence_list;
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struct reservation_object *resv = bo->tbo.resv;
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struct reservation_object_list *old, *new;
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unsigned int i, j, k;
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if (!ef && !ef_list)
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return -EINVAL;
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@ -220,76 +218,67 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo,
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*ef_count = 0;
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}
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resv = bo->tbo.resv;
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fobj = reservation_object_get_list(resv);
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if (!fobj)
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old = reservation_object_get_list(resv);
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if (!old)
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return 0;
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preempt_disable();
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write_seqcount_begin(&resv->seq);
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/* Go through all the shared fences in the resevation object. If
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* ef is specified and it exists in the list, remove it and reduce the
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* count. If ef is not specified, then get the count of eviction fences
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* present.
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*/
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shared_count = fobj->shared_count;
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for (i = 0; i < shared_count; ++i) {
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struct dma_fence *f;
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f = rcu_dereference_protected(fobj->shared[i],
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reservation_object_held(resv));
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if (ef) {
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if (f->context == ef->base.context) {
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dma_fence_put(f);
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fobj->shared_count--;
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} else {
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RCU_INIT_POINTER(fobj->shared[j++], f);
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}
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} else if (to_amdgpu_amdkfd_fence(f))
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count++;
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}
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write_seqcount_end(&resv->seq);
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preempt_enable();
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if (ef || !count)
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return 0;
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/* Alloc memory for count number of eviction fence pointers. Fill the
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* ef_list array and ef_count
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*/
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fence_list = kcalloc(count, sizeof(struct amdgpu_amdkfd_fence *),
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GFP_KERNEL);
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if (!fence_list)
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new = kmalloc(offsetof(typeof(*new), shared[old->shared_max]),
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GFP_KERNEL);
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if (!new)
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return -ENOMEM;
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preempt_disable();
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write_seqcount_begin(&resv->seq);
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j = 0;
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for (i = 0; i < shared_count; ++i) {
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/* Go through all the shared fences in the resevation object and sort
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* the interesting ones to the end of the list.
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*/
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for (i = 0, j = old->shared_count, k = 0; i < old->shared_count; ++i) {
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struct dma_fence *f;
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struct amdgpu_amdkfd_fence *efence;
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f = rcu_dereference_protected(fobj->shared[i],
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reservation_object_held(resv));
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f = rcu_dereference_protected(old->shared[i],
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reservation_object_held(resv));
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efence = to_amdgpu_amdkfd_fence(f);
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if (efence) {
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fence_list[k++] = efence;
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fobj->shared_count--;
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} else {
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RCU_INIT_POINTER(fobj->shared[j++], f);
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if ((ef && f->context == ef->base.context) ||
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(!ef && to_amdgpu_amdkfd_fence(f)))
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RCU_INIT_POINTER(new->shared[--j], f);
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else
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RCU_INIT_POINTER(new->shared[k++], f);
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}
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new->shared_max = old->shared_max;
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new->shared_count = k;
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if (!ef) {
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unsigned int count = old->shared_count - j;
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/* Alloc memory for count number of eviction fence pointers.
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* Fill the ef_list array and ef_count
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*/
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*ef_list = kcalloc(count, sizeof(**ef_list), GFP_KERNEL);
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*ef_count = count;
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if (!*ef_list) {
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kfree(new);
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return -ENOMEM;
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}
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}
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/* Install the new fence list, seqcount provides the barriers */
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preempt_disable();
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write_seqcount_begin(&resv->seq);
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RCU_INIT_POINTER(resv->fence, new);
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write_seqcount_end(&resv->seq);
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preempt_enable();
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*ef_list = fence_list;
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*ef_count = k;
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/* Drop the references to the removed fences or move them to ef_list */
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for (i = j, k = 0; i < old->shared_count; ++i) {
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struct dma_fence *f;
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f = rcu_dereference_protected(new->shared[i],
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reservation_object_held(resv));
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if (!ef)
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(*ef_list)[k++] = to_amdgpu_amdkfd_fence(f);
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else
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dma_fence_put(f);
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}
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kfree_rcu(old, rcu);
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return 0;
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}
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@ -2274,7 +2274,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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#ifdef CONFIG_X86
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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case CHIP_RAVEN:
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#endif
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return amdgpu_dc != 0;
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@ -53,9 +53,8 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
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int fd,
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enum drm_sched_priority priority)
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{
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struct file *filp = fcheck(fd);
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struct file *filp = fget(fd);
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struct drm_file *file;
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struct pid *pid;
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struct amdgpu_fpriv *fpriv;
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struct amdgpu_ctx *ctx;
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uint32_t id;
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@ -63,20 +62,12 @@ static int amdgpu_sched_process_priority_override(struct amdgpu_device *adev,
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if (!filp)
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return -EINVAL;
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pid = get_pid(((struct drm_file *)filp->private_data)->pid);
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file = filp->private_data;
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fpriv = file->driver_priv;
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idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
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amdgpu_ctx_priority_override(ctx, priority);
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mutex_lock(&adev->ddev->filelist_mutex);
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list_for_each_entry(file, &adev->ddev->filelist, lhead) {
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if (file->pid != pid)
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continue;
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fpriv = file->driver_priv;
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idr_for_each_entry(&fpriv->ctx_mgr.ctx_handles, ctx, id)
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amdgpu_ctx_priority_override(ctx, priority);
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}
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mutex_unlock(&adev->ddev->filelist_mutex);
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put_pid(pid);
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fput(filp);
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return 0;
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}
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@ -38,6 +38,7 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
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adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
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adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
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adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
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adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
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adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
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adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
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@ -46,6 +47,8 @@ int vega20_reg_base_init(struct amdgpu_device *adev)
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adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
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adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
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adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
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adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
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adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
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}
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return 0;
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}
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@ -112,8 +112,8 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
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u32 r;
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spin_lock_irqsave(&adev->smc_idx_lock, flags);
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WREG32(mmSMC_IND_INDEX_11, (reg));
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r = RREG32(mmSMC_IND_DATA_11);
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WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg));
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r = RREG32_NO_KIQ(mmSMC_IND_DATA_11);
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spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
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return r;
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}
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@ -4,11 +4,17 @@ menu "Display Engine Configuration"
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config DRM_AMD_DC
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bool "AMD DC - Enable new display engine"
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default y
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select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
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help
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Choose this option if you want to use the new display engine
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support for AMDGPU. This adds required support for Vega and
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Raven ASICs.
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config DRM_AMD_DC_DCN1_0
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def_bool n
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help
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RV family support for display engine
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config DEBUG_KERNEL_DC
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bool "Enable kgdb break in DC"
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depends on DRM_AMD_DC
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|
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@ -58,9 +58,7 @@
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_edid.h>
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#include "modules/inc/mod_freesync.h"
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#ifdef CONFIG_X86
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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#include "ivsrcid/irqsrcs_dcn_1_0.h"
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#include "dcn/dcn_1_0_offset.h"
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|
@ -1192,7 +1190,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
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return 0;
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}
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#ifdef CONFIG_X86
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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/* Register IRQ sources and initialize IRQ callbacks */
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static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
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{
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|
@ -1532,7 +1530,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
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|||
goto fail;
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||||
}
|
||||
break;
|
||||
#ifdef CONFIG_X86
|
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#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
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case CHIP_RAVEN:
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if (dcn10_register_irq_handlers(dm->adev)) {
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DRM_ERROR("DM: Failed to initialize IRQ\n");
|
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|
@ -1716,7 +1714,7 @@ static int dm_early_init(void *handle)
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adev->mode_info.num_dig = 6;
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adev->mode_info.plane_type = dm_plane_type_default;
|
||||
break;
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
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case CHIP_RAVEN:
|
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adev->mode_info.num_crtc = 4;
|
||||
adev->mode_info.num_hpd = 4;
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
DC_LIBS = basics bios calcs dce gpio i2caux irq virtual
|
||||
|
||||
ifdef CONFIG_X86
|
||||
ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
DC_LIBS += dcn10 dml
|
||||
endif
|
||||
|
||||
|
|
|
@ -55,7 +55,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
|
|||
case DCE_VERSION_11_22:
|
||||
*h = dal_cmd_tbl_helper_dce112_get_table2();
|
||||
return true;
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case DCN_VERSION_1_0:
|
||||
*h = dal_cmd_tbl_helper_dce112_get_table2();
|
||||
return true;
|
||||
|
|
|
@ -38,7 +38,7 @@ CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare
|
|||
|
||||
BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o
|
||||
|
||||
ifdef CONFIG_X86
|
||||
ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o
|
||||
endif
|
||||
|
||||
|
|
|
@ -52,6 +52,8 @@
|
|||
#include "dm_helpers.h"
|
||||
#include "mem_input.h"
|
||||
#include "hubp.h"
|
||||
|
||||
#include "dc_link_dp.h"
|
||||
#define DC_LOGGER \
|
||||
dc->ctx->logger
|
||||
|
||||
|
@ -419,8 +421,17 @@ void dc_link_set_preferred_link_settings(struct dc *dc,
|
|||
struct dc_link_settings *link_setting,
|
||||
struct dc_link *link)
|
||||
{
|
||||
link->preferred_link_setting = *link_setting;
|
||||
dp_retrain_link_dp_test(link, link_setting, false);
|
||||
struct dc_link_settings store_settings = *link_setting;
|
||||
struct dc_stream_state *link_stream =
|
||||
link->dc->current_state->res_ctx.pipe_ctx[0].stream;
|
||||
|
||||
link->preferred_link_setting = store_settings;
|
||||
if (link_stream)
|
||||
decide_link_settings(link_stream, &store_settings);
|
||||
|
||||
if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
|
||||
(store_settings.link_rate != LINK_RATE_UNKNOWN))
|
||||
dp_retrain_link_dp_test(link, &store_settings, false);
|
||||
}
|
||||
|
||||
void dc_link_enable_hpd(const struct dc_link *link)
|
||||
|
@ -476,7 +487,7 @@ static void destruct(struct dc *dc)
|
|||
kfree(dc->bw_dceip);
|
||||
dc->bw_dceip = NULL;
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
kfree(dc->dcn_soc);
|
||||
dc->dcn_soc = NULL;
|
||||
|
||||
|
@ -492,7 +503,7 @@ static bool construct(struct dc *dc,
|
|||
struct dc_context *dc_ctx;
|
||||
struct bw_calcs_dceip *dc_dceip;
|
||||
struct bw_calcs_vbios *dc_vbios;
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
struct dcn_soc_bounding_box *dcn_soc;
|
||||
struct dcn_ip_params *dcn_ip;
|
||||
#endif
|
||||
|
@ -514,7 +525,7 @@ static bool construct(struct dc *dc,
|
|||
}
|
||||
|
||||
dc->bw_vbios = dc_vbios;
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL);
|
||||
if (!dcn_soc) {
|
||||
dm_error("%s: failed to create dcn_soc\n", __func__);
|
||||
|
|
|
@ -348,7 +348,7 @@ void context_clock_trace(
|
|||
struct dc *dc,
|
||||
struct dc_state *context)
|
||||
{
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
DC_LOGGER_INIT(dc->ctx->logger);
|
||||
CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n"
|
||||
"dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n",
|
||||
|
|
|
@ -1039,9 +1039,6 @@ static bool construct(
|
|||
|
||||
link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
|
||||
|
||||
if (dc_ctx->dc_bios->integrated_info)
|
||||
link->dp_ss_off = !!dc_ctx->dc_bios->integrated_info->dp_ss_control;
|
||||
|
||||
if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
|
||||
dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
|
||||
__func__, init_params->connector_index,
|
||||
|
@ -1049,6 +1046,9 @@ static bool construct(
|
|||
goto create_fail;
|
||||
}
|
||||
|
||||
if (link->dc->res_pool->funcs->link_init)
|
||||
link->dc->res_pool->funcs->link_init(link);
|
||||
|
||||
hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
|
||||
|
||||
if (hpd_gpio != NULL)
|
||||
|
|
|
@ -41,7 +41,7 @@
|
|||
#include "dce100/dce100_resource.h"
|
||||
#include "dce110/dce110_resource.h"
|
||||
#include "dce112/dce112_resource.h"
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#include "dcn10/dcn10_resource.h"
|
||||
#endif
|
||||
#include "dce120/dce120_resource.h"
|
||||
|
@ -85,7 +85,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
|
|||
case FAMILY_AI:
|
||||
dc_version = DCE_VERSION_12_0;
|
||||
break;
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case FAMILY_RV:
|
||||
dc_version = DCN_VERSION_1_0;
|
||||
break;
|
||||
|
@ -136,7 +136,7 @@ struct resource_pool *dc_create_resource_pool(
|
|||
num_virtual_links, dc);
|
||||
break;
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case DCN_VERSION_1_0:
|
||||
res_pool = dcn10_create_resource_pool(
|
||||
num_virtual_links, dc);
|
||||
|
@ -1251,7 +1251,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream(
|
|||
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
static int acquire_first_split_pipe(
|
||||
struct resource_context *res_ctx,
|
||||
const struct resource_pool *pool,
|
||||
|
@ -1322,7 +1322,7 @@ bool dc_add_plane_to_context(
|
|||
|
||||
free_pipe = acquire_free_pipe_for_stream(context, pool, stream);
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
if (!free_pipe) {
|
||||
int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
|
||||
if (pipe_idx >= 0)
|
||||
|
@ -1920,7 +1920,7 @@ enum dc_status resource_map_pool_resources(
|
|||
/* acquire new resources */
|
||||
pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
if (pipe_idx < 0)
|
||||
pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
|
||||
#endif
|
||||
|
|
|
@ -294,7 +294,7 @@ struct dc {
|
|||
/* Inputs into BW and WM calculations. */
|
||||
struct bw_calcs_dceip *bw_dceip;
|
||||
struct bw_calcs_vbios *bw_vbios;
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
struct dcn_soc_bounding_box *dcn_soc;
|
||||
struct dcn_ip_params *dcn_ip;
|
||||
struct display_mode_lib dml;
|
||||
|
|
|
@ -592,7 +592,7 @@ static uint32_t dce110_get_pix_clk_dividers(
|
|||
case DCE_VERSION_11_2:
|
||||
case DCE_VERSION_11_22:
|
||||
case DCE_VERSION_12_0:
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case DCN_VERSION_1_0:
|
||||
#endif
|
||||
|
||||
|
@ -909,7 +909,7 @@ static bool dce110_program_pix_clk(
|
|||
struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source);
|
||||
struct bp_pixel_clock_parameters bp_pc_params = {0};
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) {
|
||||
unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
|
||||
unsigned dp_dto_ref_kHz = 700000;
|
||||
|
@ -982,7 +982,7 @@ static bool dce110_program_pix_clk(
|
|||
case DCE_VERSION_11_2:
|
||||
case DCE_VERSION_11_22:
|
||||
case DCE_VERSION_12_0:
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case DCN_VERSION_1_0:
|
||||
#endif
|
||||
|
||||
|
|
|
@ -55,7 +55,7 @@
|
|||
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\
|
||||
CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh)
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
|
||||
#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \
|
||||
SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\
|
||||
|
|
|
@ -30,7 +30,7 @@
|
|||
#include "bios_parser_interface.h"
|
||||
#include "dc.h"
|
||||
#include "dmcu.h"
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#include "dcn_calcs.h"
|
||||
#endif
|
||||
#include "core_types.h"
|
||||
|
@ -106,7 +106,8 @@ enum dentist_base_divider_id {
|
|||
DENTIST_BASE_DID_1 = 0x08,
|
||||
DENTIST_BASE_DID_2 = 0x40,
|
||||
DENTIST_BASE_DID_3 = 0x60,
|
||||
DENTIST_MAX_DID = 0x80
|
||||
DENTIST_BASE_DID_4 = 0x7e,
|
||||
DENTIST_MAX_DID = 0x7f
|
||||
};
|
||||
|
||||
/* Starting point and step size for each divider range.*/
|
||||
|
@ -117,6 +118,8 @@ enum dentist_divider_range {
|
|||
DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
|
||||
DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
|
||||
DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
|
||||
DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
|
||||
DENTIST_DIVIDER_RANGE_4_STEP = 264, /* 66.00 */
|
||||
DENTIST_DIVIDER_RANGE_SCALE_FACTOR = 4
|
||||
};
|
||||
|
||||
|
@ -133,9 +136,12 @@ static int dentist_get_divider_from_did(int did)
|
|||
} else if (did < DENTIST_BASE_DID_3) {
|
||||
return DENTIST_DIVIDER_RANGE_2_START + DENTIST_DIVIDER_RANGE_2_STEP
|
||||
* (did - DENTIST_BASE_DID_2);
|
||||
} else {
|
||||
} else if (did < DENTIST_BASE_DID_4) {
|
||||
return DENTIST_DIVIDER_RANGE_3_START + DENTIST_DIVIDER_RANGE_3_STEP
|
||||
* (did - DENTIST_BASE_DID_3);
|
||||
} else {
|
||||
return DENTIST_DIVIDER_RANGE_4_START + DENTIST_DIVIDER_RANGE_4_STEP
|
||||
* (did - DENTIST_BASE_DID_4);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -478,7 +484,7 @@ static void dce12_update_clocks(struct dccg *dccg,
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks)
|
||||
{
|
||||
bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
|
||||
|
@ -668,7 +674,7 @@ static void dce_update_clocks(struct dccg *dccg,
|
|||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
static const struct display_clock_funcs dcn1_funcs = {
|
||||
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
|
||||
.set_dispclk = dce112_set_clock,
|
||||
|
@ -823,7 +829,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx)
|
|||
return &clk_dce->base;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
struct dccg *dcn1_dccg_create(struct dc_context *ctx)
|
||||
{
|
||||
struct dc_debug_options *debug = &ctx->dc->debug;
|
||||
|
|
|
@ -111,7 +111,7 @@ struct dccg *dce112_dccg_create(
|
|||
|
||||
struct dccg *dce120_dccg_create(struct dc_context *ctx);
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
struct dccg *dcn1_dccg_create(struct dc_context *ctx);
|
||||
#endif
|
||||
|
||||
|
|
|
@ -316,7 +316,7 @@ static void dce_get_psr_wait_loop(
|
|||
return;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
static void dcn10_get_dmcu_state(struct dmcu *dmcu)
|
||||
{
|
||||
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
|
||||
|
@ -743,7 +743,7 @@ static const struct dmcu_funcs dce_funcs = {
|
|||
.is_dmcu_initialized = dce_is_dmcu_initialized
|
||||
};
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
static const struct dmcu_funcs dcn10_funcs = {
|
||||
.dmcu_init = dcn10_dmcu_init,
|
||||
.load_iram = dcn10_dmcu_load_iram,
|
||||
|
@ -795,7 +795,7 @@ struct dmcu *dce_dmcu_create(
|
|||
return &dmcu_dce->base;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
struct dmcu *dcn10_dmcu_create(
|
||||
struct dc_context *ctx,
|
||||
const struct dce_dmcu_registers *regs,
|
||||
|
|
|
@ -135,7 +135,7 @@ static void dce110_update_generic_info_packet(
|
|||
AFMT_GENERIC0_UPDATE, (packet_index == 0),
|
||||
AFMT_GENERIC2_UPDATE, (packet_index == 2));
|
||||
}
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
if (REG(AFMT_VBI_PACKET_CONTROL1)) {
|
||||
switch (packet_index) {
|
||||
case 0:
|
||||
|
@ -229,7 +229,7 @@ static void dce110_update_hdmi_info_packet(
|
|||
HDMI_GENERIC1_SEND, send,
|
||||
HDMI_GENERIC1_LINE, line);
|
||||
break;
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case 4:
|
||||
if (REG(HDMI_GENERIC_PACKET_CONTROL2))
|
||||
REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2,
|
||||
|
@ -274,7 +274,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
|
|||
struct dc_crtc_timing *crtc_timing,
|
||||
enum dc_color_space output_color_space)
|
||||
{
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
uint32_t h_active_start;
|
||||
uint32_t v_active_start;
|
||||
uint32_t misc0 = 0;
|
||||
|
@ -317,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
|
|||
if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN)
|
||||
REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
if (enc110->se_mask->DP_VID_N_MUL)
|
||||
REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
|
||||
#endif
|
||||
|
@ -328,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
|
|||
break;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
if (REG(DP_MSA_MISC))
|
||||
misc1 = REG_READ(DP_MSA_MISC);
|
||||
#endif
|
||||
|
@ -362,7 +362,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
|
|||
/* set dynamic range and YCbCr range */
|
||||
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
switch (crtc_timing->display_color_depth) {
|
||||
case COLOR_DEPTH_666:
|
||||
colorimetry_bpc = 0;
|
||||
|
@ -441,7 +441,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
|
|||
DP_DYN_RANGE, dynamic_range_rgb,
|
||||
DP_YCBCR_RANGE, dynamic_range_ycbcr);
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
if (REG(DP_MSA_COLORIMETRY))
|
||||
REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0);
|
||||
|
||||
|
@ -476,7 +476,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute(
|
|||
crtc_timing->v_front_porch;
|
||||
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
/* start at begining of left border */
|
||||
if (REG(DP_MSA_TIMING_PARAM2))
|
||||
REG_SET_2(DP_MSA_TIMING_PARAM2, 0,
|
||||
|
@ -751,7 +751,7 @@ static void dce110_stream_encoder_update_hdmi_info_packets(
|
|||
dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
if (enc110->se_mask->HDMI_DB_DISABLE) {
|
||||
/* for bring up, disable dp double TODO */
|
||||
if (REG(HDMI_DB_CONTROL))
|
||||
|
@ -789,7 +789,7 @@ static void dce110_stream_encoder_stop_hdmi_info_packets(
|
|||
HDMI_GENERIC1_LINE, 0,
|
||||
HDMI_GENERIC1_SEND, 0);
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
/* stop generic packets 2 & 3 on HDMI */
|
||||
if (REG(HDMI_GENERIC_PACKET_CONTROL2))
|
||||
REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0,
|
||||
|
|
|
@ -1250,7 +1250,7 @@ static void program_scaler(const struct dc *dc,
|
|||
{
|
||||
struct tg_color color = {0};
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
/* TOFPGA */
|
||||
if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
|
||||
return;
|
||||
|
@ -1588,7 +1588,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
|
|||
bool can_eDP_fast_boot_optimize = false;
|
||||
|
||||
if (edp_link) {
|
||||
can_eDP_fast_boot_optimize =
|
||||
/* this seems to cause blank screens on DCE8 */
|
||||
if ((dc->ctx->dce_version == DCE_VERSION_8_0) ||
|
||||
(dc->ctx->dce_version == DCE_VERSION_8_1) ||
|
||||
(dc->ctx->dce_version == DCE_VERSION_8_3))
|
||||
can_eDP_fast_boot_optimize = false;
|
||||
else
|
||||
can_eDP_fast_boot_optimize =
|
||||
edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc);
|
||||
}
|
||||
|
||||
|
|
|
@ -61,7 +61,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120)
|
|||
###############################################################################
|
||||
# DCN 1x
|
||||
###############################################################################
|
||||
ifdef CONFIG_X86
|
||||
ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o
|
||||
|
||||
AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
#include "dce80/hw_factory_dce80.h"
|
||||
#include "dce110/hw_factory_dce110.h"
|
||||
#include "dce120/hw_factory_dce120.h"
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#include "dcn10/hw_factory_dcn10.h"
|
||||
#endif
|
||||
|
||||
|
@ -81,7 +81,7 @@ bool dal_hw_factory_init(
|
|||
case DCE_VERSION_12_0:
|
||||
dal_hw_factory_dce120_init(factory);
|
||||
return true;
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case DCN_VERSION_1_0:
|
||||
dal_hw_factory_dcn10_init(factory);
|
||||
return true;
|
||||
|
|
|
@ -43,7 +43,7 @@
|
|||
#include "dce80/hw_translate_dce80.h"
|
||||
#include "dce110/hw_translate_dce110.h"
|
||||
#include "dce120/hw_translate_dce120.h"
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#include "dcn10/hw_translate_dcn10.h"
|
||||
#endif
|
||||
|
||||
|
@ -78,7 +78,7 @@ bool dal_hw_translate_init(
|
|||
case DCE_VERSION_12_0:
|
||||
dal_hw_translate_dce120_init(translate);
|
||||
return true;
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case DCN_VERSION_1_0:
|
||||
dal_hw_translate_dcn10_init(translate);
|
||||
return true;
|
||||
|
|
|
@ -71,7 +71,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112)
|
|||
###############################################################################
|
||||
# DCN 1.0 family
|
||||
###############################################################################
|
||||
ifdef CONFIG_X86
|
||||
ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
I2CAUX_DCN1 = i2caux_dcn10.o
|
||||
|
||||
AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1))
|
||||
|
|
|
@ -59,7 +59,7 @@
|
|||
|
||||
#include "dce120/i2caux_dce120.h"
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#include "dcn10/i2caux_dcn10.h"
|
||||
#endif
|
||||
|
||||
|
@ -91,7 +91,7 @@ struct i2caux *dal_i2caux_create(
|
|||
return dal_i2caux_dce100_create(ctx);
|
||||
case DCE_VERSION_12_0:
|
||||
return dal_i2caux_dce120_create(ctx);
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
case DCN_VERSION_1_0:
|
||||
return dal_i2caux_dcn10_create(ctx);
|
||||
#endif
|
||||
|
|
|
@ -33,7 +33,7 @@
|
|||
#include "dc_bios_types.h"
|
||||
#include "mem_input.h"
|
||||
#include "hubp.h"
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#include "mpc.h"
|
||||
#endif
|
||||
|
||||
|
@ -92,6 +92,7 @@ struct resource_context;
|
|||
|
||||
struct resource_funcs {
|
||||
void (*destroy)(struct resource_pool **pool);
|
||||
void (*link_init)(struct dc_link *link);
|
||||
struct link_encoder *(*link_enc_create)(
|
||||
const struct encoder_init_data *init);
|
||||
|
||||
|
@ -221,7 +222,7 @@ struct pipe_ctx {
|
|||
struct pipe_ctx *top_pipe;
|
||||
struct pipe_ctx *bottom_pipe;
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
struct _vcs_dpi_display_dlg_regs_st dlg_regs;
|
||||
struct _vcs_dpi_display_ttu_regs_st ttu_regs;
|
||||
struct _vcs_dpi_display_rq_regs_st rq_regs;
|
||||
|
@ -276,7 +277,7 @@ struct dc_state {
|
|||
|
||||
/* Note: these are big structures, do *not* put on stack! */
|
||||
struct dm_pp_display_configuration pp_display_cfg;
|
||||
#ifdef CONFIG_X86
|
||||
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
struct dcn_bw_internal_vars dcn_bw_vars;
|
||||
#endif
|
||||
|
||||
|
|
|
@ -60,7 +60,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12)
|
|||
###############################################################################
|
||||
# DCN 1x
|
||||
###############################################################################
|
||||
ifdef CONFIG_X86
|
||||
ifdef CONFIG_DRM_AMD_DC_DCN1_0
|
||||
IRQ_DCN1 = irq_service_dcn10.o
|
||||
|
||||
AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))
|
||||
|
|
|
@ -36,7 +36,7 @@
|
|||
#include "dce120/irq_service_dce120.h"
|
||||
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#include "dcn10/irq_service_dcn10.h"
|
||||
#endif
|
||||
|
||||
|
|
|
@ -48,7 +48,7 @@
|
|||
|
||||
#define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__)
|
||||
|
||||
#ifdef CONFIG_X86
|
||||
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
|
||||
#include <asm/fpu/api.h>
|
||||
#endif
|
||||
|
||||
|
|
|
@ -75,10 +75,12 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
|
|||
|
||||
int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct amdgpu_device *adev = NULL;
|
||||
int ret = -EINVAL;;
|
||||
PHM_FUNC_CHECK(hwmgr);
|
||||
adev = hwmgr->adev;
|
||||
|
||||
if (smum_is_dpm_running(hwmgr)) {
|
||||
if (smum_is_dpm_running(hwmgr) && !amdgpu_passthrough(adev)) {
|
||||
pr_info("dpm has been enabled\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -116,6 +116,9 @@ static const struct edid_quirk {
|
|||
/* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
|
||||
{ "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
|
||||
|
||||
/* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
|
||||
{ "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
|
||||
|
||||
/* Belinea 10 15 55 */
|
||||
{ "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
|
||||
{ "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
|
||||
|
|
|
@ -1385,6 +1385,9 @@ static const struct panel_desc innolux_tv123wam = {
|
|||
.width = 259,
|
||||
.height = 173,
|
||||
},
|
||||
.delay = {
|
||||
.unprepare = 500,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct drm_display_mode innolux_zj070na_01p_mode = {
|
||||
|
|
Loading…
Reference in a new issue