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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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arm64: dts: uniphier: Align node names for SoC-dependent controller and PHYs with bindings
The node names for SoC-dependent controllers and PHYs should be generic ones according to the DT schemas. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Link: https://lore.kernel.org/r/20230207023514.29783-6-hayashi.kunihiko@socionext.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Kunihiko Hayashi
Arnd Bergmann
parent
1ae6e6bc72
commit
5ebfa90bdd
3 changed files with 56 additions and 56 deletions
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@ -313,12 +313,12 @@ evea_hp: endpoint {
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};
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};
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adamv@57920000 {
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syscon@57920000 {
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compatible = "socionext,uniphier-ld11-adamv",
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"simple-mfd", "syscon";
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reg = <0x57920000 0x1000>;
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adamv_rst: reset {
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adamv_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-adamv-reset";
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#reset-cells = <1>;
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};
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@ -417,28 +417,28 @@ smpctrl@59801000 {
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reg = <0x59801000 0x400>;
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};
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sdctrl@59810000 {
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syscon@59810000 {
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compatible = "socionext,uniphier-ld11-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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sd_rst: reset {
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sd_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-sd-reset";
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#reset-cells = <1>;
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};
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};
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perictrl@59820000 {
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syscon@59820000 {
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compatible = "socionext,uniphier-ld11-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock {
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peri_clk: clock-controller {
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compatible = "socionext,uniphier-ld11-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset {
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peri_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-peri-reset";
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#reset-cells = <1>;
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};
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@ -511,24 +511,24 @@ usb2: usb@5a820100 {
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has-transaction-translator;
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};
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mioctrl@5b3e0000 {
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syscon@5b3e0000 {
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compatible = "socionext,uniphier-ld11-mioctrl",
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"simple-mfd", "syscon";
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reg = <0x5b3e0000 0x800>;
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mio_clk: clock {
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mio_clk: clock-controller {
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compatible = "socionext,uniphier-ld11-mio-clock";
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#clock-cells = <1>;
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};
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mio_rst: reset {
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mio_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-mio-reset";
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#reset-cells = <1>;
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resets = <&sys_rst 7>;
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};
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};
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soc_glue: soc-glue@5f800000 {
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soc_glue: syscon@5f800000 {
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compatible = "socionext,uniphier-ld11-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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@ -537,7 +537,7 @@ pinctrl: pinctrl {
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compatible = "socionext,uniphier-ld11-pinctrl";
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};
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usb-controller {
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usb-hub {
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compatible = "socionext,uniphier-ld11-usb2-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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@ -559,7 +559,7 @@ usb_phy2: phy@2 {
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};
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};
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soc-glue@5f900000 {
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syscon@5f900000 {
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compatible = "socionext,uniphier-ld11-soc-glue-debug",
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"simple-mfd";
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#address-cells = <1>;
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@ -601,17 +601,17 @@ gic: interrupt-controller@5fe00000 {
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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sysctrl@61840000 {
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syscon@61840000 {
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compatible = "socionext,uniphier-ld11-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x10000>;
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sys_clk: clock {
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sys_clk: clock-controller {
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compatible = "socionext,uniphier-ld11-clock";
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#clock-cells = <1>;
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};
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sys_rst: reset {
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sys_rst: reset-controller {
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compatible = "socionext,uniphier-ld11-reset";
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#reset-cells = <1>;
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};
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@ -444,12 +444,12 @@ evea_hp: endpoint {
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};
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};
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adamv@57920000 {
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syscon@57920000 {
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compatible = "socionext,uniphier-ld20-adamv",
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"simple-mfd", "syscon";
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reg = <0x57920000 0x1000>;
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adamv_rst: reset {
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adamv_rst: reset-controller {
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compatible = "socionext,uniphier-ld20-adamv-reset";
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#reset-cells = <1>;
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};
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@ -548,33 +548,33 @@ smpctrl@59801000 {
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reg = <0x59801000 0x400>;
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};
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sdctrl@59810000 {
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syscon@59810000 {
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compatible = "socionext,uniphier-ld20-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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sd_clk: clock {
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sd_clk: clock-controller {
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compatible = "socionext,uniphier-ld20-sd-clock";
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#clock-cells = <1>;
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};
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sd_rst: reset {
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sd_rst: reset-controller {
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compatible = "socionext,uniphier-ld20-sd-reset";
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#reset-cells = <1>;
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};
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};
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perictrl@59820000 {
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syscon@59820000 {
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compatible = "socionext,uniphier-ld20-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock {
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peri_clk: clock-controller {
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compatible = "socionext,uniphier-ld20-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset {
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peri_rst: reset-controller {
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compatible = "socionext,uniphier-ld20-peri-reset";
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#reset-cells = <1>;
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};
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@ -613,7 +613,7 @@ sd: mmc@5a400000 {
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cap-sd-highspeed;
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};
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soc_glue: soc-glue@5f800000 {
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soc_glue: syscon@5f800000 {
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compatible = "socionext,uniphier-ld20-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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@ -623,7 +623,7 @@ pinctrl: pinctrl {
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};
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};
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soc-glue@5f900000 {
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syscon@5f900000 {
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compatible = "socionext,uniphier-ld20-soc-glue-debug",
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"simple-mfd";
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#address-cells = <1>;
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@ -709,17 +709,17 @@ gic: interrupt-controller@5fe00000 {
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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sysctrl@61840000 {
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syscon@61840000 {
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compatible = "socionext,uniphier-ld20-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x10000>;
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sys_clk: clock {
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sys_clk: clock-controller {
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compatible = "socionext,uniphier-ld20-clock";
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#clock-cells = <1>;
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};
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sys_rst: reset {
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sys_rst: reset-controller {
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compatible = "socionext,uniphier-ld20-reset";
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#reset-cells = <1>;
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};
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@ -782,7 +782,7 @@ usb-controller@65b00000 {
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_rst: reset@0 {
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usb_rst: reset-controller@0 {
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compatible = "socionext,uniphier-ld20-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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@ -828,7 +828,7 @@ usb_vbus3: regulator@130 {
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resets = <&sys_rst 14>;
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};
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usb_hsphy0: hs-phy@200 {
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usb_hsphy0: phy@200 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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@ -842,7 +842,7 @@ usb_hsphy0: hs-phy@200 {
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<&usb_hs_i0>;
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};
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usb_hsphy1: hs-phy@210 {
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usb_hsphy1: phy@210 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x210 0x10>;
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#phy-cells = <0>;
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@ -856,7 +856,7 @@ usb_hsphy1: hs-phy@210 {
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<&usb_hs_i0>;
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};
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usb_hsphy2: hs-phy@220 {
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usb_hsphy2: phy@220 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x220 0x10>;
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#phy-cells = <0>;
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@ -870,7 +870,7 @@ usb_hsphy2: hs-phy@220 {
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<&usb_hs_i2>;
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};
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usb_hsphy3: hs-phy@230 {
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usb_hsphy3: phy@230 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x230 0x10>;
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#phy-cells = <0>;
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@ -884,7 +884,7 @@ usb_hsphy3: hs-phy@230 {
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<&usb_hs_i2>;
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};
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usb_ssphy0: ss-phy@300 {
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usb_ssphy0: phy@300 {
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compatible = "socionext,uniphier-ld20-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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@ -895,7 +895,7 @@ usb_ssphy0: ss-phy@300 {
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vbus-supply = <&usb_vbus0>;
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};
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usb_ssphy1: ss-phy@310 {
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usb_ssphy1: phy@310 {
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compatible = "socionext,uniphier-ld20-usb3-ssphy";
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reg = <0x310 0x10>;
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#phy-cells = <0>;
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@ -370,33 +370,33 @@ smpctrl@59801000 {
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reg = <0x59801000 0x400>;
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};
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sdctrl@59810000 {
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syscon@59810000 {
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compatible = "socionext,uniphier-pxs3-sdctrl",
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"simple-mfd", "syscon";
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reg = <0x59810000 0x400>;
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sd_clk: clock {
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sd_clk: clock-controller {
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compatible = "socionext,uniphier-pxs3-sd-clock";
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#clock-cells = <1>;
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};
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sd_rst: reset {
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sd_rst: reset-controller {
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compatible = "socionext,uniphier-pxs3-sd-reset";
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#reset-cells = <1>;
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};
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};
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perictrl@59820000 {
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syscon@59820000 {
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compatible = "socionext,uniphier-pxs3-perictrl",
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"simple-mfd", "syscon";
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reg = <0x59820000 0x200>;
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peri_clk: clock {
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peri_clk: clock-controller {
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compatible = "socionext,uniphier-pxs3-peri-clock";
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#clock-cells = <1>;
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};
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peri_rst: reset {
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peri_rst: reset-controller {
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compatible = "socionext,uniphier-pxs3-peri-reset";
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#reset-cells = <1>;
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};
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@ -439,7 +439,7 @@ sd: mmc@5a400000 {
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sd-uhs-sdr50;
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};
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soc_glue: soc-glue@5f800000 {
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soc_glue: syscon@5f800000 {
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compatible = "socionext,uniphier-pxs3-soc-glue",
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"simple-mfd", "syscon";
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reg = <0x5f800000 0x2000>;
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@ -449,7 +449,7 @@ pinctrl: pinctrl {
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};
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};
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soc-glue@5f900000 {
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syscon@5f900000 {
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compatible = "socionext,uniphier-pxs3-soc-glue-debug",
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"simple-mfd";
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#address-cells = <1>;
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@ -535,17 +535,17 @@ gic: interrupt-controller@5fe00000 {
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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sysctrl@61840000 {
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syscon@61840000 {
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compatible = "socionext,uniphier-pxs3-sysctrl",
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"simple-mfd", "syscon";
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reg = <0x61840000 0x10000>;
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sys_clk: clock {
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sys_clk: clock-controller {
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compatible = "socionext,uniphier-pxs3-clock";
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#clock-cells = <1>;
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};
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sys_rst: reset {
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sys_rst: reset-controller {
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compatible = "socionext,uniphier-pxs3-reset";
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#reset-cells = <1>;
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};
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@ -707,7 +707,7 @@ usb-controller@65b00000 {
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb0_rst: reset@0 {
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usb0_rst: reset-controller@0 {
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compatible = "socionext,uniphier-pxs3-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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@ -735,7 +735,7 @@ usb0_vbus1: regulator@110 {
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resets = <&sys_rst 12>;
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};
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usb0_hsphy0: hs-phy@200 {
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usb0_hsphy0: phy@200 {
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compatible = "socionext,uniphier-pxs3-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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@ -749,7 +749,7 @@ usb0_hsphy0: hs-phy@200 {
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<&usb_hs_i0>;
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};
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usb0_hsphy1: hs-phy@210 {
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usb0_hsphy1: phy@210 {
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compatible = "socionext,uniphier-pxs3-usb3-hsphy";
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reg = <0x210 0x10>;
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#phy-cells = <0>;
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@ -763,7 +763,7 @@ usb0_hsphy1: hs-phy@210 {
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<&usb_hs_i0>;
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};
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usb0_ssphy0: ss-phy@300 {
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usb0_ssphy0: phy@300 {
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compatible = "socionext,uniphier-pxs3-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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@ -774,7 +774,7 @@ usb0_ssphy0: ss-phy@300 {
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vbus-supply = <&usb0_vbus0>;
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};
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usb0_ssphy1: ss-phy@310 {
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usb0_ssphy1: phy@310 {
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compatible = "socionext,uniphier-pxs3-usb3-ssphy";
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reg = <0x310 0x10>;
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#phy-cells = <0>;
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@ -809,7 +809,7 @@ usb-controller@65d00000 {
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#size-cells = <1>;
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ranges = <0 0x65d00000 0x400>;
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usb1_rst: reset@0 {
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usb1_rst: reset-controller@0 {
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compatible = "socionext,uniphier-pxs3-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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@ -837,7 +837,7 @@ usb1_vbus1: regulator@110 {
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resets = <&sys_rst 13>;
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};
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usb1_hsphy0: hs-phy@200 {
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usb1_hsphy0: phy@200 {
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compatible = "socionext,uniphier-pxs3-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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@ -852,7 +852,7 @@ usb1_hsphy0: hs-phy@200 {
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<&usb_hs_i2>;
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};
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usb1_hsphy1: hs-phy@210 {
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usb1_hsphy1: phy@210 {
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compatible = "socionext,uniphier-pxs3-usb3-hsphy";
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reg = <0x210 0x10>;
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#phy-cells = <0>;
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@ -867,7 +867,7 @@ usb1_hsphy1: hs-phy@210 {
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<&usb_hs_i2>;
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};
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usb1_ssphy0: ss-phy@300 {
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usb1_ssphy0: phy@300 {
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compatible = "socionext,uniphier-pxs3-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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||||
|
|
|
|||
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Reference in a new issue