net: stmmac: add clocks management for gmac driver
This patch intends to add clocks management for stmmac driver: If CONFIG_PM enabled: 1. Keep clocks disabled after driver probed. 2. Enable clocks when up the net device, and disable clocks when down the net device. If CONFIG_PM disabled: Keep clocks always enabled after driver probed. Note: 1. It is fine for ethtool, since the way of implementing ethtool_ops::begin in stmmac is only can be accessed when interface is enabled, so the clocks are ticked. 2. The MDIO bus has a different life cycle to the MAC, need ensure clocks are enabled when _mdio_read/write() need clocks, because these functions can be called while the interface it not opened. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Joakim Zhang
David S. Miller
parent
91de5ac99a
commit
5ec5582343
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@ -272,6 +272,7 @@ void stmmac_disable_eee_mode(struct stmmac_priv *priv);
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bool stmmac_eee_init(struct stmmac_priv *priv);
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int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
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int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
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int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
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#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
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void stmmac_selftest_run(struct net_device *dev,
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@ -28,6 +28,7 @@
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#include <linux/if_vlan.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/prefetch.h>
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#include <linux/pinctrl/consumer.h>
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#ifdef CONFIG_DEBUG_FS
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@ -113,6 +114,28 @@ static void stmmac_exit_fs(struct net_device *dev);
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#define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC))
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int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled)
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{
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int ret = 0;
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if (enabled) {
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ret = clk_prepare_enable(priv->plat->stmmac_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(priv->plat->pclk);
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if (ret) {
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clk_disable_unprepare(priv->plat->stmmac_clk);
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return ret;
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}
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} else {
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clk_disable_unprepare(priv->plat->stmmac_clk);
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clk_disable_unprepare(priv->plat->pclk);
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}
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return ret;
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}
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EXPORT_SYMBOL_GPL(stmmac_bus_clks_config);
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/**
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* stmmac_verify_args - verify the driver parameters.
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* Description: it checks the driver parameters and set a default in case of
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@ -2896,6 +2919,12 @@ static int stmmac_open(struct net_device *dev)
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u32 chan;
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int ret;
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ret = pm_runtime_get_sync(priv->device);
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if (ret < 0) {
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pm_runtime_put_noidle(priv->device);
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return ret;
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}
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if (priv->hw->pcs != STMMAC_PCS_TBI &&
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priv->hw->pcs != STMMAC_PCS_RTBI &&
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priv->hw->xpcs_args.an_mode != DW_AN_C73) {
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@ -2904,7 +2933,7 @@ static int stmmac_open(struct net_device *dev)
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netdev_err(priv->dev,
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"%s: Cannot attach to PHY (error: %d)\n",
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__func__, ret);
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return ret;
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goto init_phy_error;
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}
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}
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@ -3020,6 +3049,8 @@ init_error:
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free_dma_desc_resources(priv);
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dma_desc_error:
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phylink_disconnect_phy(priv->phylink);
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init_phy_error:
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pm_runtime_put(priv->device);
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return ret;
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}
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@ -3070,6 +3101,8 @@ static int stmmac_release(struct net_device *dev)
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stmmac_release_ptp(priv);
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pm_runtime_put(priv->device);
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return 0;
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}
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@ -4706,6 +4739,12 @@ static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid
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bool is_double = false;
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int ret;
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ret = pm_runtime_get_sync(priv->device);
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if (ret < 0) {
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pm_runtime_put_noidle(priv->device);
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return ret;
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}
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if (be16_to_cpu(proto) == ETH_P_8021AD)
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is_double = true;
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@ -4739,10 +4778,15 @@ static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vi
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if (priv->hw->num_vlan) {
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ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid);
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if (ret)
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return ret;
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goto del_vlan_error;
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}
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return stmmac_vlan_update(priv, is_double);
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ret = stmmac_vlan_update(priv, is_double);
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del_vlan_error:
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pm_runtime_put(priv->device);
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return ret;
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}
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static const struct net_device_ops stmmac_netdev_ops = {
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@ -5181,6 +5225,10 @@ int stmmac_dvr_probe(struct device *device,
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stmmac_check_pcs_mode(priv);
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pm_runtime_get_noresume(device);
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pm_runtime_set_active(device);
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pm_runtime_enable(device);
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if (priv->hw->pcs != STMMAC_PCS_TBI &&
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priv->hw->pcs != STMMAC_PCS_RTBI) {
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/* MDIO bus Registration */
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@ -5218,6 +5266,11 @@ int stmmac_dvr_probe(struct device *device,
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stmmac_init_fs(ndev);
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#endif
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/* Let pm_runtime_put() disable the clocks.
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* If CONFIG_PM is not enabled, the clocks will stay powered.
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*/
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pm_runtime_put(device);
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return ret;
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error_serdes_powerup:
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@ -5232,6 +5285,7 @@ error_mdio_register:
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stmmac_napi_del(ndev);
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error_hw_init:
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destroy_workqueue(priv->wq);
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stmmac_bus_clks_config(priv, false);
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return ret;
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}
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@ -5267,8 +5321,8 @@ int stmmac_dvr_remove(struct device *dev)
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phylink_destroy(priv->phylink);
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if (priv->plat->stmmac_rst)
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reset_control_assert(priv->plat->stmmac_rst);
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clk_disable_unprepare(priv->plat->pclk);
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clk_disable_unprepare(priv->plat->stmmac_clk);
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pm_runtime_put(dev);
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pm_runtime_disable(dev);
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if (priv->hw->pcs != STMMAC_PCS_TBI &&
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priv->hw->pcs != STMMAC_PCS_RTBI)
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stmmac_mdio_unregister(ndev);
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@ -5291,6 +5345,7 @@ int stmmac_suspend(struct device *dev)
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struct net_device *ndev = dev_get_drvdata(dev);
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struct stmmac_priv *priv = netdev_priv(ndev);
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u32 chan;
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int ret;
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if (!ndev || !netif_running(ndev))
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return 0;
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@ -5334,8 +5389,9 @@ int stmmac_suspend(struct device *dev)
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pinctrl_pm_select_sleep_state(priv->device);
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/* Disable clock in case of PWM is off */
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clk_disable_unprepare(priv->plat->clk_ptp_ref);
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clk_disable_unprepare(priv->plat->pclk);
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clk_disable_unprepare(priv->plat->stmmac_clk);
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ret = pm_runtime_force_suspend(dev);
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if (ret)
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return ret;
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}
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mutex_unlock(&priv->lock);
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@ -5401,8 +5457,9 @@ int stmmac_resume(struct device *dev)
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} else {
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pinctrl_pm_select_default_state(priv->device);
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/* enable the clk previously disabled */
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clk_prepare_enable(priv->plat->stmmac_clk);
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clk_prepare_enable(priv->plat->pclk);
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ret = pm_runtime_force_resume(dev);
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if (ret)
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return ret;
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if (priv->plat->clk_ptp_ref)
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clk_prepare_enable(priv->plat->clk_ptp_ref);
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/* reset the phy so that it's ready */
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@ -15,6 +15,7 @@
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#include <linux/iopoll.h>
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#include <linux/mii.h>
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#include <linux/of_mdio.h>
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#include <linux/pm_runtime.h>
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#include <linux/phy.h>
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#include <linux/property.h>
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#include <linux/slab.h>
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@ -87,21 +88,29 @@ static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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u32 tmp, addr, value = MII_XGMAC_BUSY;
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int ret;
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ret = pm_runtime_get_sync(priv->device);
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if (ret < 0) {
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pm_runtime_put_noidle(priv->device);
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return ret;
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}
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000))
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return -EBUSY;
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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if (phyreg & MII_ADDR_C45) {
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phyreg &= ~MII_ADDR_C45;
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ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
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if (ret)
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return ret;
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goto err_disable_clks;
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} else {
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ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
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if (ret)
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return ret;
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goto err_disable_clks;
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value |= MII_XGMAC_SADDR;
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}
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@ -112,8 +121,10 @@ static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000))
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return -EBUSY;
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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/* Set the MII address register to read */
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writel(addr, priv->ioaddr + mii_address);
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@ -121,11 +132,18 @@ static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000))
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return -EBUSY;
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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/* Read the data from the MII data register */
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return readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
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ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
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err_disable_clks:
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pm_runtime_put(priv->device);
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return ret;
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}
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static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,
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@ -138,21 +156,29 @@ static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,
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u32 addr, tmp, value = MII_XGMAC_BUSY;
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int ret;
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ret = pm_runtime_get_sync(priv->device);
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if (ret < 0) {
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pm_runtime_put_noidle(priv->device);
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return ret;
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}
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000))
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return -EBUSY;
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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if (phyreg & MII_ADDR_C45) {
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phyreg &= ~MII_ADDR_C45;
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ret = stmmac_xgmac2_c45_format(priv, phyaddr, phyreg, &addr);
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if (ret)
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return ret;
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goto err_disable_clks;
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} else {
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ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
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if (ret)
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return ret;
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goto err_disable_clks;
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value |= MII_XGMAC_SADDR;
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}
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@ -164,16 +190,23 @@ static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000))
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return -EBUSY;
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!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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/* Set the MII address register to write */
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writel(addr, priv->ioaddr + mii_address);
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writel(value, priv->ioaddr + mii_data);
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/* Wait until any existing MII operation is complete */
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return readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000);
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ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp,
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!(tmp & MII_XGMAC_BUSY), 100, 10000);
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err_disable_clks:
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pm_runtime_put(priv->device);
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return ret;
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}
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/**
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@ -196,6 +229,12 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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int data = 0;
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u32 v;
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data = pm_runtime_get_sync(priv->device);
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if (data < 0) {
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pm_runtime_put_noidle(priv->device);
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return data;
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}
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value |= (phyaddr << priv->hw->mii.addr_shift)
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& priv->hw->mii.addr_mask;
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value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
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@ -216,19 +255,26 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
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}
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000))
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return -EBUSY;
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100, 10000)) {
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data = -EBUSY;
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goto err_disable_clks;
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}
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writel(data, priv->ioaddr + mii_data);
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writel(value, priv->ioaddr + mii_address);
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000))
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return -EBUSY;
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100, 10000)) {
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data = -EBUSY;
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goto err_disable_clks;
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}
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/* Read the data from the MII data register */
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data = (int)readl(priv->ioaddr + mii_data) & MII_DATA_MASK;
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err_disable_clks:
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pm_runtime_put(priv->device);
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return data;
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}
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@ -247,10 +293,16 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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struct stmmac_priv *priv = netdev_priv(ndev);
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unsigned int mii_address = priv->hw->mii.addr;
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unsigned int mii_data = priv->hw->mii.data;
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int ret, data = phydata;
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u32 value = MII_BUSY;
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int data = phydata;
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u32 v;
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ret = pm_runtime_get_sync(priv->device);
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if (ret < 0) {
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pm_runtime_put_noidle(priv->device);
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return ret;
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}
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value |= (phyaddr << priv->hw->mii.addr_shift)
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& priv->hw->mii.addr_mask;
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value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
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@ -275,16 +327,23 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
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/* Wait until any existing MII operation is complete */
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if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000))
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return -EBUSY;
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100, 10000)) {
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ret = -EBUSY;
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goto err_disable_clks;
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}
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/* Set the MII address register to write */
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writel(data, priv->ioaddr + mii_data);
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writel(value, priv->ioaddr + mii_address);
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/* Wait until any existing MII operation is complete */
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return readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000);
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ret = readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
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100, 10000);
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err_disable_clks:
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pm_runtime_put(priv->device);
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return ret;
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}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -744,10 +744,30 @@ static int stmmac_pltfr_resume(struct device *dev)
|
|||
|
||||
return stmmac_resume(dev);
|
||||
}
|
||||
|
||||
static int stmmac_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct net_device *ndev = dev_get_drvdata(dev);
|
||||
struct stmmac_priv *priv = netdev_priv(ndev);
|
||||
|
||||
stmmac_bus_clks_config(priv, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stmmac_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct net_device *ndev = dev_get_drvdata(dev);
|
||||
struct stmmac_priv *priv = netdev_priv(ndev);
|
||||
|
||||
return stmmac_bus_clks_config(priv, true);
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
SIMPLE_DEV_PM_OPS(stmmac_pltfr_pm_ops, stmmac_pltfr_suspend,
|
||||
stmmac_pltfr_resume);
|
||||
const struct dev_pm_ops stmmac_pltfr_pm_ops = {
|
||||
SET_SYSTEM_SLEEP_PM_OPS(stmmac_pltfr_suspend, stmmac_pltfr_resume)
|
||||
SET_RUNTIME_PM_OPS(stmmac_runtime_suspend, stmmac_runtime_resume, NULL)
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(stmmac_pltfr_pm_ops);
|
||||
|
||||
MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet platform support");
|
||||
|
|
|
|||
Loading…
Reference in New Issue