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drm/amd/pp: Add stable Pstate clk display support in debugfs
The additional output are: PSTATE_SCLK and PSTATE_MCLK value in MHz as: 300 MHz (PSTATE_SCLK) 300 MHz (PSTATE_MCLK) Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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dd70949d90
commit
5ed8d656d6
3 changed files with 20 additions and 9 deletions
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@ -1591,6 +1591,10 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
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seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
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seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
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seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
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seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
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seq_printf(m, "\t%u mV (VDDGFX)\n", value);
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if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
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@ -122,6 +122,8 @@ enum amd_pp_sensors {
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AMDGPU_PP_SENSOR_VCE_POWER,
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AMDGPU_PP_SENSOR_UVD_POWER,
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AMDGPU_PP_SENSOR_GPU_POWER,
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AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
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AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
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};
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enum amd_pp_task {
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@ -992,23 +992,28 @@ static int pp_dpm_read_sensor(void *handle, int idx,
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int ret = 0;
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ret = pp_check(pp_handle);
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if (ret)
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return ret;
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if (value == NULL)
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return -EINVAL;
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hwmgr = pp_handle->hwmgr;
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if (hwmgr->hwmgr_func->read_sensor == NULL) {
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pr_info("%s was not implemented.\n", __func__);
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switch (idx) {
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case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
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*((uint32_t *)value) = hwmgr->pstate_sclk;
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return 0;
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}
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case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
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*((uint32_t *)value) = hwmgr->pstate_mclk;
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return 0;
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default:
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mutex_lock(&pp_handle->pp_lock);
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ret = hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value, size);
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mutex_unlock(&pp_handle->pp_lock);
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return ret;
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}
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}
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static struct amd_vce_state*
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pp_dpm_get_vce_clock_state(void *handle, unsigned idx)
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