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x86/insn: Fix vector instruction decoding on big endian cross-compiles
Running instruction decoder posttest on an s390 host with an x86 target with allyesconfig shows errors. Instructions used in a couple of kernel objects could not be correctly decoded on big endian system. insn_decoder_test: warning: objdump says 6 bytes, but insn_get_length() says 5 insn_decoder_test: warning: Found an x86 instruction decoder bug, please report this. insn_decoder_test: warning: ffffffff831eb4e1: 62 d1 fd 48 7f 04 24 vmovdqa64 %zmm0,(%r12) insn_decoder_test: warning: objdump says 7 bytes, but insn_get_length() says 6 insn_decoder_test: warning: Found an x86 instruction decoder bug, please report this. insn_decoder_test: warning: ffffffff831eb4e8: 62 51 fd 48 7f 44 24 01 vmovdqa64 %zmm8,0x40(%r12) insn_decoder_test: warning: objdump says 8 bytes, but insn_get_length() says 6 This is because in a few places instruction field bytes are set directly with further usage of "value". To address that introduce and use a insn_set_byte() helper, which correctly updates "value" on big endian systems. Signed-off-by: Vasily Gorbik <gor@linux.ibm.com> Acked-by: Masami Hiramatsu <mhiramat@kernel.org> Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
This commit is contained in:
Vasily Gorbik
Josh Poimboeuf
parent
7786032e52
commit
5ed934e57e
4 changed files with 42 additions and 18 deletions
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@ -30,6 +30,12 @@ static inline void insn_field_set(struct insn_field *p, insn_value_t v,
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p->nbytes = n;
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}
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static inline void insn_set_byte(struct insn_field *p, unsigned char n,
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insn_byte_t v)
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{
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p->bytes[n] = v;
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}
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#else
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struct insn_field {
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@ -51,6 +57,12 @@ static inline void insn_field_set(struct insn_field *p, insn_value_t v,
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p->nbytes = n;
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}
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static inline void insn_set_byte(struct insn_field *p, unsigned char n,
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insn_byte_t v)
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{
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p->bytes[n] = v;
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p->value = __le32_to_cpu(p->little);
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}
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#endif
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struct insn {
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@ -161,9 +161,9 @@ void insn_get_prefixes(struct insn *insn)
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b = insn->prefixes.bytes[3];
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for (i = 0; i < nb; i++)
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if (prefixes->bytes[i] == lb)
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prefixes->bytes[i] = b;
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insn_set_byte(prefixes, i, b);
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}
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insn->prefixes.bytes[3] = lb;
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insn_set_byte(&insn->prefixes, 3, lb);
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}
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/* Decode REX prefix */
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@ -194,13 +194,13 @@ void insn_get_prefixes(struct insn *insn)
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if (X86_MODRM_MOD(b2) != 3)
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goto vex_end;
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}
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insn->vex_prefix.bytes[0] = b;
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insn->vex_prefix.bytes[1] = b2;
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insn_set_byte(&insn->vex_prefix, 0, b);
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insn_set_byte(&insn->vex_prefix, 1, b2);
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if (inat_is_evex_prefix(attr)) {
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b2 = peek_nbyte_next(insn_byte_t, insn, 2);
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insn->vex_prefix.bytes[2] = b2;
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insn_set_byte(&insn->vex_prefix, 2, b2);
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b2 = peek_nbyte_next(insn_byte_t, insn, 3);
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insn->vex_prefix.bytes[3] = b2;
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insn_set_byte(&insn->vex_prefix, 3, b2);
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insn->vex_prefix.nbytes = 4;
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insn->next_byte += 4;
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if (insn->x86_64 && X86_VEX_W(b2))
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@ -208,7 +208,7 @@ void insn_get_prefixes(struct insn *insn)
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insn->opnd_bytes = 8;
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} else if (inat_is_vex3_prefix(attr)) {
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b2 = peek_nbyte_next(insn_byte_t, insn, 2);
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insn->vex_prefix.bytes[2] = b2;
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insn_set_byte(&insn->vex_prefix, 2, b2);
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insn->vex_prefix.nbytes = 3;
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insn->next_byte += 3;
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if (insn->x86_64 && X86_VEX_W(b2))
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@ -220,7 +220,7 @@ void insn_get_prefixes(struct insn *insn)
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* Makes it easier to decode vex.W, vex.vvvv,
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* vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
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*/
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insn->vex_prefix.bytes[2] = b2 & 0x7f;
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insn_set_byte(&insn->vex_prefix, 2, b2 & 0x7f);
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insn->vex_prefix.nbytes = 2;
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insn->next_byte += 2;
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}
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@ -256,7 +256,7 @@ void insn_get_opcode(struct insn *insn)
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/* Get first opcode */
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op = get_next(insn_byte_t, insn);
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opcode->bytes[0] = op;
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insn_set_byte(opcode, 0, op);
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opcode->nbytes = 1;
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/* Check if there is VEX prefix or not */
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@ -30,6 +30,12 @@ static inline void insn_field_set(struct insn_field *p, insn_value_t v,
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p->nbytes = n;
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}
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static inline void insn_set_byte(struct insn_field *p, unsigned char n,
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insn_byte_t v)
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{
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p->bytes[n] = v;
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}
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#else
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struct insn_field {
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@ -51,6 +57,12 @@ static inline void insn_field_set(struct insn_field *p, insn_value_t v,
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p->nbytes = n;
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}
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static inline void insn_set_byte(struct insn_field *p, unsigned char n,
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insn_byte_t v)
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{
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p->bytes[n] = v;
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p->value = __le32_to_cpu(p->little);
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}
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#endif
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struct insn {
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@ -161,9 +161,9 @@ void insn_get_prefixes(struct insn *insn)
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b = insn->prefixes.bytes[3];
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for (i = 0; i < nb; i++)
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if (prefixes->bytes[i] == lb)
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prefixes->bytes[i] = b;
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insn_set_byte(prefixes, i, b);
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}
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insn->prefixes.bytes[3] = lb;
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insn_set_byte(&insn->prefixes, 3, lb);
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}
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/* Decode REX prefix */
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@ -194,13 +194,13 @@ void insn_get_prefixes(struct insn *insn)
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if (X86_MODRM_MOD(b2) != 3)
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goto vex_end;
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}
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insn->vex_prefix.bytes[0] = b;
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insn->vex_prefix.bytes[1] = b2;
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insn_set_byte(&insn->vex_prefix, 0, b);
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insn_set_byte(&insn->vex_prefix, 1, b2);
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if (inat_is_evex_prefix(attr)) {
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b2 = peek_nbyte_next(insn_byte_t, insn, 2);
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insn->vex_prefix.bytes[2] = b2;
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insn_set_byte(&insn->vex_prefix, 2, b2);
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b2 = peek_nbyte_next(insn_byte_t, insn, 3);
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insn->vex_prefix.bytes[3] = b2;
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insn_set_byte(&insn->vex_prefix, 3, b2);
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insn->vex_prefix.nbytes = 4;
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insn->next_byte += 4;
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if (insn->x86_64 && X86_VEX_W(b2))
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@ -208,7 +208,7 @@ void insn_get_prefixes(struct insn *insn)
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insn->opnd_bytes = 8;
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} else if (inat_is_vex3_prefix(attr)) {
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b2 = peek_nbyte_next(insn_byte_t, insn, 2);
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insn->vex_prefix.bytes[2] = b2;
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insn_set_byte(&insn->vex_prefix, 2, b2);
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insn->vex_prefix.nbytes = 3;
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insn->next_byte += 3;
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if (insn->x86_64 && X86_VEX_W(b2))
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@ -220,7 +220,7 @@ void insn_get_prefixes(struct insn *insn)
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* Makes it easier to decode vex.W, vex.vvvv,
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* vex.L and vex.pp. Masking with 0x7f sets vex.W == 0.
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*/
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insn->vex_prefix.bytes[2] = b2 & 0x7f;
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insn_set_byte(&insn->vex_prefix, 2, b2 & 0x7f);
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insn->vex_prefix.nbytes = 2;
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insn->next_byte += 2;
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}
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@ -256,7 +256,7 @@ void insn_get_opcode(struct insn *insn)
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/* Get first opcode */
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op = get_next(insn_byte_t, insn);
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opcode->bytes[0] = op;
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insn_set_byte(opcode, 0, op);
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opcode->nbytes = 1;
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/* Check if there is VEX prefix or not */
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