arm64: dts: imx8mq-evk: Add second PCIe port support
Enable the second PCIe port support on i.MX8MQ EVK board. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -27,6 +27,17 @@
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clock-frequency = <100000000>;
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};
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reg_pcie1: regulator-pcie {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie1_reg>;
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regulator-name = "MPCIE_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-vsd-3v3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2>;
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@ -328,6 +339,20 @@
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status = "okay";
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};
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&pcie1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pcie1>;
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reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
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clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
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<&clk IMX8MQ_CLK_PCIE2_AUX>,
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<&clk IMX8MQ_CLK_PCIE2_PHY>,
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<&pcie0_refclk>;
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clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
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vpcie-supply = <®_pcie1>;
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vph-supply = <&vgen5_reg>;
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status = "okay";
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};
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&pgc_gpu {
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power-supply = <&sw1a_reg>;
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};
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@ -483,6 +508,19 @@
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>;
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};
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pinctrl_pcie1: pcie1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
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MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
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>;
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};
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pinctrl_pcie1_reg: pcie1reggrp {
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fsl,pins = <
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MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
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