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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
drm/amdgpu: update Fiji's tiling mode table
Change-Id: I925c15015390113f7e27746ec5751eaa6a92c2a7 Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
c305fd5fff
commit
5f2e816b29
1 changed files with 291 additions and 1 deletions
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@ -995,7 +995,7 @@ static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
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adev->gfx.config.max_cu_per_sh = 16;
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adev->gfx.config.max_sh_per_se = 1;
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adev->gfx.config.max_backends_per_se = 4;
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adev->gfx.config.max_texture_channel_caches = 8;
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adev->gfx.config.max_texture_channel_caches = 16;
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adev->gfx.config.max_gprs = 256;
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adev->gfx.config.max_gs_threads = 32;
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adev->gfx.config.max_hw_contexts = 8;
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@ -1608,6 +1608,296 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
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WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
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}
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case CHIP_FIJI:
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
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switch (reg_offset) {
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case 0:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 1:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 2:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 3:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 4:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 5:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 6:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 7:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 8:
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gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
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break;
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case 9:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
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break;
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case 10:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
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break;
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case 11:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
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break;
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case 12:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
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break;
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case 13:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
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break;
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case 14:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
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break;
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case 15:
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gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
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break;
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case 16:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
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break;
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case 17:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
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break;
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case 18:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 19:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 20:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 21:
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gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 22:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 23:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 24:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 25:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 26:
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gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
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break;
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case 27:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
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break;
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case 28:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
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break;
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case 29:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
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break;
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case 30:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
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SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
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break;
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default:
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gb_tile_moden = 0;
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break;
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}
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adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
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WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
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}
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for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
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switch (reg_offset) {
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case 0:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 1:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 2:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 3:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 4:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 5:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 6:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 8:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 9:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 10:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 11:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 12:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 13:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
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NUM_BANKS(ADDR_SURF_8_BANK));
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break;
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case 14:
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gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
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BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
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MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
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NUM_BANKS(ADDR_SURF_4_BANK));
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break;
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case 7:
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/* unused idx */
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continue;
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default:
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gb_tile_moden = 0;
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break;
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}
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adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
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WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
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}
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break;
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case CHIP_TONGA:
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for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
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switch (reg_offset) {
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