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xhci: move usb3 speficic bits to own function in get_port_status call

Browse source 
refactoring, no functional changes

Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mathias Nyman 2018-12-07 16:19:32 +02:00 committed by Greg Kroah-Hartman
parent 1c2d81cc28
commit 5f78a54f8d
1 changed files with 40 additions and 28 deletions
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68
drivers/usb/host/xhci-hub.c
View file

@ -818,6 +818,41 @@ static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
return ext_stat;
}
static void xhci_get_usb3_port_status(struct xhci_port *port, u32 *status,
u32 portsc)
{
struct xhci_hcd *xhci;
u32 link_state;
u32 portnum;
xhci = hcd_to_xhci(port->rhub->hcd);
link_state = portsc & PORT_PLS_MASK;
portnum = port->hcd_portnum;
/* USB3 specific wPortChange bits
*
* Port link change with port in resume state should not be
* reported to usbcore, as this is an internal state to be
* handled by xhci driver. Reporting PLC to usbcore may
* cause usbcore clearing PLC first and port change event
* irq won't be generated.
*/
if (portsc & PORT_PLC && (link_state != XDEV_RESUME))
*status |= USB_PORT_STAT_C_LINK_STATE << 16;
if (portsc & PORT_WRC)
*status |= USB_PORT_STAT_C_BH_RESET << 16;
if (portsc & PORT_CEC)
*status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
/* USB3 specific wPortStatus bits */
if (portsc & PORT_POWER)
*status |= USB_SS_PORT_STAT_POWER;
xhci_hub_report_usb3_link_state(xhci, status, portsc);
xhci_del_comp_mod_timer(xhci, portsc, portnum);
}
/*
* Converts a raw xHCI port status into the format that external USB 2.0 or USB
* 3.0 hubs use.
@ -854,22 +889,8 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
if ((raw_port_status & PORT_RC))
status |= USB_PORT_STAT_C_RESET << 16;
/* USB3.0 only */
if (hcd->speed >= HCD_USB3) {
/* Port link change with port in resume state should not be
* reported to usbcore, as this is an internal state to be
* handled by xhci driver. Reporting PLC to usbcore may
* cause usbcore clearing PLC first and port change event
* irq won't be generated.
*/
if ((raw_port_status & PORT_PLC) &&
(raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
status |= USB_PORT_STAT_C_LINK_STATE << 16;
if ((raw_port_status & PORT_WRC))
status |= USB_PORT_STAT_C_BH_RESET << 16;
if ((raw_port_status & PORT_CEC))
status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
}
if (hcd->speed >= HCD_USB3)
xhci_get_usb3_port_status(port, &status, raw_port_status);
if (hcd->speed < HCD_USB3) {
if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
&& (raw_port_status & PORT_POWER))
@ -989,22 +1010,13 @@ static u32 xhci_get_port_status(struct usb_hcd *hcd,
if (raw_port_status & PORT_RESET)
status |= USB_PORT_STAT_RESET;
if (raw_port_status & PORT_POWER) {
if (hcd->speed >= HCD_USB3)
status |= USB_SS_PORT_STAT_POWER;
else
if (hcd->speed < HCD_USB3)
status |= USB_PORT_STAT_POWER;
}
/* Update Port Link State */
if (hcd->speed >= HCD_USB3) {
xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
/*
* Verify if all USB3 Ports Have entered U0 already.
* Delete Compliance Mode Timer if so.
*/
xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
} else {
if (hcd->speed < HCD_USB3)
xhci_hub_report_usb2_link_state(&status, raw_port_status);
}
if (bus_state->port_c_suspend & (1 << wIndex))
status |= USB_PORT_STAT_C_SUSPEND << 16;