mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 10:49:33 +00:00
Merge branch 'drm-fixes-staging' of ssh://people.freedesktop.org/~/linux into drm-fixes
Pull the staging fixes tree I had into rc3 to make real -fixes again.
This commit is contained in:
commit
5f7f8f6edb
36 changed files with 250 additions and 120 deletions
|
@ -519,7 +519,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
|
|||
r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
|
||||
&duplicates);
|
||||
if (unlikely(r != 0)) {
|
||||
DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
|
||||
if (r != -ERESTARTSYS)
|
||||
DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
|
||||
goto error_free_pages;
|
||||
}
|
||||
|
||||
|
|
|
@ -1959,6 +1959,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
|
|||
/* evict remaining vram memory */
|
||||
amdgpu_bo_evict_vram(adev);
|
||||
|
||||
amdgpu_atombios_scratch_regs_save(adev);
|
||||
pci_save_state(dev->pdev);
|
||||
if (suspend) {
|
||||
/* Shut down the device */
|
||||
|
@ -2010,6 +2011,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
|
|||
return r;
|
||||
}
|
||||
}
|
||||
amdgpu_atombios_scratch_regs_restore(adev);
|
||||
|
||||
/* post card */
|
||||
if (!amdgpu_card_posted(adev) || !resume) {
|
||||
|
@ -2268,8 +2270,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
|
|||
}
|
||||
|
||||
if (need_full_reset) {
|
||||
/* save scratch */
|
||||
amdgpu_atombios_scratch_regs_save(adev);
|
||||
r = amdgpu_suspend(adev);
|
||||
|
||||
retry:
|
||||
|
@ -2279,8 +2279,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
|
|||
amdgpu_display_stop_mc_access(adev, &save);
|
||||
amdgpu_wait_for_idle(adev, AMD_IP_BLOCK_TYPE_GMC);
|
||||
}
|
||||
|
||||
amdgpu_atombios_scratch_regs_save(adev);
|
||||
r = amdgpu_asic_reset(adev);
|
||||
amdgpu_atombios_scratch_regs_restore(adev);
|
||||
/* post card */
|
||||
amdgpu_atom_asic_init(adev->mode_info.atom_context);
|
||||
|
||||
|
@ -2288,8 +2289,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
|
|||
dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
|
||||
r = amdgpu_resume(adev);
|
||||
}
|
||||
/* restore scratch */
|
||||
amdgpu_atombios_scratch_regs_restore(adev);
|
||||
}
|
||||
if (!r) {
|
||||
amdgpu_irq_gpu_reset_resume_helper(adev);
|
||||
|
|
|
@ -68,6 +68,7 @@ int amdgpu_fence_slab_init(void)
|
|||
|
||||
void amdgpu_fence_slab_fini(void)
|
||||
{
|
||||
rcu_barrier();
|
||||
kmem_cache_destroy(amdgpu_fence_slab);
|
||||
}
|
||||
/*
|
||||
|
|
|
@ -239,6 +239,7 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
|
|||
if (r) {
|
||||
adev->irq.installed = false;
|
||||
flush_work(&adev->hotplug_work);
|
||||
cancel_work_sync(&adev->reset_work);
|
||||
return r;
|
||||
}
|
||||
|
||||
|
@ -264,6 +265,7 @@ void amdgpu_irq_fini(struct amdgpu_device *adev)
|
|||
if (adev->irq.msi_enabled)
|
||||
pci_disable_msi(adev->pdev);
|
||||
flush_work(&adev->hotplug_work);
|
||||
cancel_work_sync(&adev->reset_work);
|
||||
}
|
||||
|
||||
for (i = 0; i < AMDGPU_MAX_IRQ_SRC_ID; ++i) {
|
||||
|
|
|
@ -459,10 +459,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
|
|||
/* return all clocks in KHz */
|
||||
dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
|
||||
if (adev->pm.dpm_enabled) {
|
||||
dev_info.max_engine_clock =
|
||||
adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
|
||||
dev_info.max_memory_clock =
|
||||
adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10;
|
||||
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
|
||||
dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
|
||||
} else {
|
||||
dev_info.max_engine_clock = adev->pm.default_sclk * 10;
|
||||
dev_info.max_memory_clock = adev->pm.default_mclk * 10;
|
||||
|
|
|
@ -1758,5 +1758,6 @@ void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
|
|||
fence_put(adev->vm_manager.ids[i].first);
|
||||
amdgpu_sync_free(&adev->vm_manager.ids[i].active);
|
||||
fence_put(id->flushed_updates);
|
||||
fence_put(id->last_flush);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -4075,7 +4075,7 @@ static int ci_enable_uvd_dpm(struct amdgpu_device *adev, bool enable)
|
|||
pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
|
||||
}
|
||||
} else {
|
||||
if (pi->last_mclk_dpm_enable_mask & 0x1) {
|
||||
if (pi->uvd_enabled) {
|
||||
pi->uvd_enabled = false;
|
||||
pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
|
||||
amdgpu_ci_send_msg_to_smc_with_parameter(adev,
|
||||
|
@ -6236,6 +6236,8 @@ static int ci_dpm_sw_fini(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
flush_work(&adev->pm.dpm.thermal.work);
|
||||
|
||||
mutex_lock(&adev->pm.mutex);
|
||||
amdgpu_pm_sysfs_fini(adev);
|
||||
ci_dpm_fini(adev);
|
||||
|
|
|
@ -3151,10 +3151,6 @@ static int dce_v10_0_hw_fini(void *handle)
|
|||
|
||||
static int dce_v10_0_suspend(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
amdgpu_atombios_scratch_regs_save(adev);
|
||||
|
||||
return dce_v10_0_hw_fini(handle);
|
||||
}
|
||||
|
||||
|
@ -3165,8 +3161,6 @@ static int dce_v10_0_resume(void *handle)
|
|||
|
||||
ret = dce_v10_0_hw_init(handle);
|
||||
|
||||
amdgpu_atombios_scratch_regs_restore(adev);
|
||||
|
||||
/* turn on the BL */
|
||||
if (adev->mode_info.bl_encoder) {
|
||||
u8 bl_level = amdgpu_display_backlight_get_level(adev,
|
||||
|
|
|
@ -3215,10 +3215,6 @@ static int dce_v11_0_hw_fini(void *handle)
|
|||
|
||||
static int dce_v11_0_suspend(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
amdgpu_atombios_scratch_regs_save(adev);
|
||||
|
||||
return dce_v11_0_hw_fini(handle);
|
||||
}
|
||||
|
||||
|
@ -3229,8 +3225,6 @@ static int dce_v11_0_resume(void *handle)
|
|||
|
||||
ret = dce_v11_0_hw_init(handle);
|
||||
|
||||
amdgpu_atombios_scratch_regs_restore(adev);
|
||||
|
||||
/* turn on the BL */
|
||||
if (adev->mode_info.bl_encoder) {
|
||||
u8 bl_level = amdgpu_display_backlight_get_level(adev,
|
||||
|
|
|
@ -2482,10 +2482,6 @@ static int dce_v6_0_hw_fini(void *handle)
|
|||
|
||||
static int dce_v6_0_suspend(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
amdgpu_atombios_scratch_regs_save(adev);
|
||||
|
||||
return dce_v6_0_hw_fini(handle);
|
||||
}
|
||||
|
||||
|
@ -2496,8 +2492,6 @@ static int dce_v6_0_resume(void *handle)
|
|||
|
||||
ret = dce_v6_0_hw_init(handle);
|
||||
|
||||
amdgpu_atombios_scratch_regs_restore(adev);
|
||||
|
||||
/* turn on the BL */
|
||||
if (adev->mode_info.bl_encoder) {
|
||||
u8 bl_level = amdgpu_display_backlight_get_level(adev,
|
||||
|
|
|
@ -3033,10 +3033,6 @@ static int dce_v8_0_hw_fini(void *handle)
|
|||
|
||||
static int dce_v8_0_suspend(void *handle)
|
||||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
amdgpu_atombios_scratch_regs_save(adev);
|
||||
|
||||
return dce_v8_0_hw_fini(handle);
|
||||
}
|
||||
|
||||
|
@ -3047,8 +3043,6 @@ static int dce_v8_0_resume(void *handle)
|
|||
|
||||
ret = dce_v8_0_hw_init(handle);
|
||||
|
||||
amdgpu_atombios_scratch_regs_restore(adev);
|
||||
|
||||
/* turn on the BL */
|
||||
if (adev->mode_info.bl_encoder) {
|
||||
u8 bl_level = amdgpu_display_backlight_get_level(adev,
|
||||
|
|
|
@ -640,7 +640,6 @@ static const u32 stoney_mgcg_cgcg_init[] =
|
|||
mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
|
||||
mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
|
||||
mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
|
||||
mmATC_MISC_CG, 0xffffffff, 0x000c0200,
|
||||
};
|
||||
|
||||
static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
|
||||
|
|
|
@ -100,6 +100,7 @@ static const u32 cz_mgcg_cgcg_init[] =
|
|||
|
||||
static const u32 stoney_mgcg_cgcg_init[] =
|
||||
{
|
||||
mmATC_MISC_CG, 0xffffffff, 0x000c0200,
|
||||
mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
|
||||
};
|
||||
|
||||
|
|
|
@ -3063,6 +3063,8 @@ static int kv_dpm_sw_fini(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
flush_work(&adev->pm.dpm.thermal.work);
|
||||
|
||||
mutex_lock(&adev->pm.mutex);
|
||||
amdgpu_pm_sysfs_fini(adev);
|
||||
kv_dpm_fini(adev);
|
||||
|
|
|
@ -3477,6 +3477,49 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
|
|||
int i;
|
||||
struct si_dpm_quirk *p = si_dpm_quirk_list;
|
||||
|
||||
/* limit all SI kickers */
|
||||
if (adev->asic_type == CHIP_PITCAIRN) {
|
||||
if ((adev->pdev->revision == 0x81) ||
|
||||
(adev->pdev->device == 0x6810) ||
|
||||
(adev->pdev->device == 0x6811) ||
|
||||
(adev->pdev->device == 0x6816) ||
|
||||
(adev->pdev->device == 0x6817) ||
|
||||
(adev->pdev->device == 0x6806))
|
||||
max_mclk = 120000;
|
||||
} else if (adev->asic_type == CHIP_VERDE) {
|
||||
if ((adev->pdev->revision == 0x81) ||
|
||||
(adev->pdev->revision == 0x83) ||
|
||||
(adev->pdev->revision == 0x87) ||
|
||||
(adev->pdev->device == 0x6820) ||
|
||||
(adev->pdev->device == 0x6821) ||
|
||||
(adev->pdev->device == 0x6822) ||
|
||||
(adev->pdev->device == 0x6823) ||
|
||||
(adev->pdev->device == 0x682A) ||
|
||||
(adev->pdev->device == 0x682B)) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
} else if (adev->asic_type == CHIP_OLAND) {
|
||||
if ((adev->pdev->revision == 0xC7) ||
|
||||
(adev->pdev->revision == 0x80) ||
|
||||
(adev->pdev->revision == 0x81) ||
|
||||
(adev->pdev->revision == 0x83) ||
|
||||
(adev->pdev->device == 0x6604) ||
|
||||
(adev->pdev->device == 0x6605)) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
} else if (adev->asic_type == CHIP_HAINAN) {
|
||||
if ((adev->pdev->revision == 0x81) ||
|
||||
(adev->pdev->revision == 0x83) ||
|
||||
(adev->pdev->revision == 0xC3) ||
|
||||
(adev->pdev->device == 0x6664) ||
|
||||
(adev->pdev->device == 0x6665) ||
|
||||
(adev->pdev->device == 0x6667)) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
}
|
||||
/* Apply dpm quirks */
|
||||
while (p && p->chip_device != 0) {
|
||||
if (adev->pdev->vendor == p->chip_vendor &&
|
||||
|
@ -3489,22 +3532,6 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
|
|||
}
|
||||
++p;
|
||||
}
|
||||
/* limit mclk on all R7 370 parts for stability */
|
||||
if (adev->pdev->device == 0x6811 &&
|
||||
adev->pdev->revision == 0x81)
|
||||
max_mclk = 120000;
|
||||
/* limit sclk/mclk on Jet parts for stability */
|
||||
if (adev->pdev->device == 0x6665 &&
|
||||
adev->pdev->revision == 0xc3) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
/* Limit clocks for some HD8600 parts */
|
||||
if (adev->pdev->device == 0x6660 &&
|
||||
adev->pdev->revision == 0x83) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
|
||||
if (rps->vce_active) {
|
||||
rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
|
||||
|
@ -7777,6 +7804,8 @@ static int si_dpm_sw_fini(void *handle)
|
|||
{
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
|
||||
flush_work(&adev->pm.dpm.thermal.work);
|
||||
|
||||
mutex_lock(&adev->pm.mutex);
|
||||
amdgpu_pm_sysfs_fini(adev);
|
||||
si_dpm_fini(adev);
|
||||
|
|
|
@ -52,6 +52,8 @@
|
|||
#define VCE_V3_0_STACK_SIZE (64 * 1024)
|
||||
#define VCE_V3_0_DATA_SIZE ((16 * 1024 * AMDGPU_MAX_VCE_HANDLES) + (52 * 1024))
|
||||
|
||||
#define FW_52_8_3 ((52 << 24) | (8 << 16) | (3 << 8))
|
||||
|
||||
static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx);
|
||||
static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev);
|
||||
static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev);
|
||||
|
@ -382,6 +384,10 @@ static int vce_v3_0_sw_init(void *handle)
|
|||
if (r)
|
||||
return r;
|
||||
|
||||
/* 52.8.3 required for 3 ring support */
|
||||
if (adev->vce.fw_version < FW_52_8_3)
|
||||
adev->vce.num_rings = 2;
|
||||
|
||||
r = amdgpu_vce_resume(adev);
|
||||
if (r)
|
||||
return r;
|
||||
|
|
|
@ -1651,7 +1651,7 @@ static int vi_common_early_init(void *handle)
|
|||
AMD_CG_SUPPORT_SDMA_MGCG |
|
||||
AMD_CG_SUPPORT_SDMA_LS |
|
||||
AMD_CG_SUPPORT_VCE_MGCG;
|
||||
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
|
||||
adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
|
||||
AMD_PG_SUPPORT_GFX_SMG |
|
||||
AMD_PG_SUPPORT_GFX_PIPELINE |
|
||||
AMD_PG_SUPPORT_UVD |
|
||||
|
|
|
@ -716,7 +716,7 @@ int phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
|
|||
*voltage = 1150;
|
||||
} else {
|
||||
ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
|
||||
*voltage = (uint16_t)vol/100;
|
||||
*voltage = (uint16_t)(vol/100);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -1320,7 +1320,8 @@ int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_
|
|||
if (0 != result)
|
||||
return result;
|
||||
|
||||
*voltage = le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)(&get_voltage_info_param_space))->ulVoltageLevel);
|
||||
*voltage = le32_to_cpu(((GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 *)
|
||||
(&get_voltage_info_param_space))->ulVoltageLevel);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
|
|
@ -1201,12 +1201,15 @@ static uint32_t make_classification_flags(struct pp_hwmgr *hwmgr,
|
|||
static int ppt_get_num_of_vce_state_table_entries_v1_0(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
const ATOM_Tonga_POWERPLAYTABLE *pp_table = get_powerplay_table(hwmgr);
|
||||
const ATOM_Tonga_VCE_State_Table *vce_state_table =
|
||||
(ATOM_Tonga_VCE_State_Table *)(((unsigned long)pp_table) + le16_to_cpu(pp_table->usVCEStateTableOffset));
|
||||
const ATOM_Tonga_VCE_State_Table *vce_state_table;
|
||||
|
||||
if (vce_state_table == NULL)
|
||||
|
||||
if (pp_table == NULL)
|
||||
return 0;
|
||||
|
||||
vce_state_table = (void *)pp_table +
|
||||
le16_to_cpu(pp_table->usVCEStateTableOffset);
|
||||
|
||||
return vce_state_table->ucNumEntries;
|
||||
}
|
||||
|
||||
|
|
|
@ -1168,8 +1168,8 @@ int smu7_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
|
|||
|
||||
tmp_result = (!smum_is_dpm_running(hwmgr)) ? 0 : -1;
|
||||
PP_ASSERT_WITH_CODE(tmp_result == 0,
|
||||
"DPM is already running right now, no need to enable DPM!",
|
||||
return 0);
|
||||
"DPM is already running",
|
||||
);
|
||||
|
||||
if (smu7_voltage_control(hwmgr)) {
|
||||
tmp_result = smu7_enable_voltage_control(hwmgr);
|
||||
|
@ -2127,15 +2127,18 @@ static int smu7_patch_acp_vddc(struct pp_hwmgr *hwmgr,
|
|||
}
|
||||
|
||||
static int smu7_patch_limits_vddc(struct pp_hwmgr *hwmgr,
|
||||
struct phm_clock_and_voltage_limits *tab)
|
||||
struct phm_clock_and_voltage_limits *tab)
|
||||
{
|
||||
uint32_t vddc, vddci;
|
||||
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
|
||||
|
||||
if (tab) {
|
||||
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, (uint32_t *)&tab->vddc,
|
||||
&data->vddc_leakage);
|
||||
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, (uint32_t *)&tab->vddci,
|
||||
&data->vddci_leakage);
|
||||
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddc,
|
||||
&data->vddc_leakage);
|
||||
tab->vddc = vddc;
|
||||
smu7_patch_ppt_v0_with_vdd_leakage(hwmgr, &vddci,
|
||||
&data->vddci_leakage);
|
||||
tab->vddci = vddci;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -645,6 +645,7 @@ void amd_sched_fini(struct amd_gpu_scheduler *sched)
|
|||
{
|
||||
if (sched->thread)
|
||||
kthread_stop(sched->thread);
|
||||
rcu_barrier();
|
||||
if (atomic_dec_and_test(&sched_fence_slab_ref))
|
||||
kmem_cache_destroy(sched_fence_slab);
|
||||
}
|
||||
|
|
|
@ -103,7 +103,7 @@ static void amd_sched_fence_free(struct rcu_head *rcu)
|
|||
}
|
||||
|
||||
/**
|
||||
* amd_sched_fence_release - callback that fence can be freed
|
||||
* amd_sched_fence_release_scheduled - callback that fence can be freed
|
||||
*
|
||||
* @fence: fence
|
||||
*
|
||||
|
@ -118,7 +118,7 @@ static void amd_sched_fence_release_scheduled(struct fence *f)
|
|||
}
|
||||
|
||||
/**
|
||||
* amd_sched_fence_release_scheduled - drop extra reference
|
||||
* amd_sched_fence_release_finished - drop extra reference
|
||||
*
|
||||
* @f: fence
|
||||
*
|
||||
|
|
|
@ -420,18 +420,21 @@ drm_atomic_replace_property_blob_from_id(struct drm_crtc *crtc,
|
|||
ssize_t expected_size,
|
||||
bool *replaced)
|
||||
{
|
||||
struct drm_device *dev = crtc->dev;
|
||||
struct drm_property_blob *new_blob = NULL;
|
||||
|
||||
if (blob_id != 0) {
|
||||
new_blob = drm_property_lookup_blob(dev, blob_id);
|
||||
new_blob = drm_property_lookup_blob(crtc->dev, blob_id);
|
||||
if (new_blob == NULL)
|
||||
return -EINVAL;
|
||||
if (expected_size > 0 && expected_size != new_blob->length)
|
||||
|
||||
if (expected_size > 0 && expected_size != new_blob->length) {
|
||||
drm_property_unreference_blob(new_blob);
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
drm_atomic_replace_property_blob(blob, new_blob, replaced);
|
||||
drm_property_unreference_blob(new_blob);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -594,10 +594,6 @@ drm_atomic_helper_check_planes(struct drm_device *dev,
|
|||
struct drm_plane_state *plane_state;
|
||||
int i, ret = 0;
|
||||
|
||||
ret = drm_atomic_normalize_zpos(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for_each_plane_in_state(state, plane, plane_state, i) {
|
||||
const struct drm_plane_helper_funcs *funcs;
|
||||
|
||||
|
|
|
@ -914,6 +914,7 @@ static void drm_dp_destroy_port(struct kref *kref)
|
|||
/* no need to clean up vcpi
|
||||
* as if we have no connector we never setup a vcpi */
|
||||
drm_dp_port_teardown_pdt(port, port->pdt);
|
||||
port->pdt = DP_PEER_DEVICE_NONE;
|
||||
}
|
||||
kfree(port);
|
||||
}
|
||||
|
@ -1159,7 +1160,9 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb,
|
|||
drm_dp_put_port(port);
|
||||
goto out;
|
||||
}
|
||||
if (port->port_num >= DP_MST_LOGICAL_PORT_0) {
|
||||
if ((port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV ||
|
||||
port->pdt == DP_PEER_DEVICE_SST_SINK) &&
|
||||
port->port_num >= DP_MST_LOGICAL_PORT_0) {
|
||||
port->cached_edid = drm_get_edid(port->connector, &port->aux.ddc);
|
||||
drm_mode_connector_set_tile_property(port->connector);
|
||||
}
|
||||
|
@ -2919,6 +2922,7 @@ static void drm_dp_destroy_connector_work(struct work_struct *work)
|
|||
mgr->cbs->destroy_connector(mgr, port->connector);
|
||||
|
||||
drm_dp_port_teardown_pdt(port, port->pdt);
|
||||
port->pdt = DP_PEER_DEVICE_NONE;
|
||||
|
||||
if (!port->input && port->vcpi.vcpi > 0) {
|
||||
drm_dp_mst_reset_vcpi_slots(mgr, port);
|
||||
|
|
|
@ -131,7 +131,12 @@ int drm_fb_helper_single_add_all_connectors(struct drm_fb_helper *fb_helper)
|
|||
return 0;
|
||||
fail:
|
||||
for (i = 0; i < fb_helper->connector_count; i++) {
|
||||
kfree(fb_helper->connector_info[i]);
|
||||
struct drm_fb_helper_connector *fb_helper_connector =
|
||||
fb_helper->connector_info[i];
|
||||
|
||||
drm_connector_unreference(fb_helper_connector->connector);
|
||||
|
||||
kfree(fb_helper_connector);
|
||||
fb_helper->connector_info[i] = NULL;
|
||||
}
|
||||
fb_helper->connector_count = 0;
|
||||
|
@ -603,6 +608,24 @@ int drm_fb_helper_blank(int blank, struct fb_info *info)
|
|||
}
|
||||
EXPORT_SYMBOL(drm_fb_helper_blank);
|
||||
|
||||
static void drm_fb_helper_modeset_release(struct drm_fb_helper *helper,
|
||||
struct drm_mode_set *modeset)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < modeset->num_connectors; i++) {
|
||||
drm_connector_unreference(modeset->connectors[i]);
|
||||
modeset->connectors[i] = NULL;
|
||||
}
|
||||
modeset->num_connectors = 0;
|
||||
|
||||
drm_mode_destroy(helper->dev, modeset->mode);
|
||||
modeset->mode = NULL;
|
||||
|
||||
/* FIXME should hold a ref? */
|
||||
modeset->fb = NULL;
|
||||
}
|
||||
|
||||
static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper)
|
||||
{
|
||||
int i;
|
||||
|
@ -612,10 +635,12 @@ static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper)
|
|||
kfree(helper->connector_info[i]);
|
||||
}
|
||||
kfree(helper->connector_info);
|
||||
|
||||
for (i = 0; i < helper->crtc_count; i++) {
|
||||
kfree(helper->crtc_info[i].mode_set.connectors);
|
||||
if (helper->crtc_info[i].mode_set.mode)
|
||||
drm_mode_destroy(helper->dev, helper->crtc_info[i].mode_set.mode);
|
||||
struct drm_mode_set *modeset = &helper->crtc_info[i].mode_set;
|
||||
|
||||
drm_fb_helper_modeset_release(helper, modeset);
|
||||
kfree(modeset->connectors);
|
||||
}
|
||||
kfree(helper->crtc_info);
|
||||
}
|
||||
|
@ -644,7 +669,9 @@ static void drm_fb_helper_dirty_work(struct work_struct *work)
|
|||
clip->x2 = clip->y2 = 0;
|
||||
spin_unlock_irqrestore(&helper->dirty_lock, flags);
|
||||
|
||||
helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, &clip_copy, 1);
|
||||
/* call dirty callback only when it has been really touched */
|
||||
if (clip_copy.x1 < clip_copy.x2 && clip_copy.y1 < clip_copy.y2)
|
||||
helper->fb->funcs->dirty(helper->fb, NULL, 0, 0, &clip_copy, 1);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -2088,7 +2115,6 @@ static void drm_setup_crtcs(struct drm_fb_helper *fb_helper)
|
|||
struct drm_fb_helper_crtc **crtcs;
|
||||
struct drm_display_mode **modes;
|
||||
struct drm_fb_offset *offsets;
|
||||
struct drm_mode_set *modeset;
|
||||
bool *enabled;
|
||||
int width, height;
|
||||
int i;
|
||||
|
@ -2136,45 +2162,35 @@ static void drm_setup_crtcs(struct drm_fb_helper *fb_helper)
|
|||
|
||||
/* need to set the modesets up here for use later */
|
||||
/* fill out the connector<->crtc mappings into the modesets */
|
||||
for (i = 0; i < fb_helper->crtc_count; i++) {
|
||||
modeset = &fb_helper->crtc_info[i].mode_set;
|
||||
modeset->num_connectors = 0;
|
||||
modeset->fb = NULL;
|
||||
}
|
||||
for (i = 0; i < fb_helper->crtc_count; i++)
|
||||
drm_fb_helper_modeset_release(fb_helper,
|
||||
&fb_helper->crtc_info[i].mode_set);
|
||||
|
||||
for (i = 0; i < fb_helper->connector_count; i++) {
|
||||
struct drm_display_mode *mode = modes[i];
|
||||
struct drm_fb_helper_crtc *fb_crtc = crtcs[i];
|
||||
struct drm_fb_offset *offset = &offsets[i];
|
||||
modeset = &fb_crtc->mode_set;
|
||||
struct drm_mode_set *modeset = &fb_crtc->mode_set;
|
||||
|
||||
if (mode && fb_crtc) {
|
||||
struct drm_connector *connector =
|
||||
fb_helper->connector_info[i]->connector;
|
||||
|
||||
DRM_DEBUG_KMS("desired mode %s set on crtc %d (%d,%d)\n",
|
||||
mode->name, fb_crtc->mode_set.crtc->base.id, offset->x, offset->y);
|
||||
|
||||
fb_crtc->desired_mode = mode;
|
||||
fb_crtc->x = offset->x;
|
||||
fb_crtc->y = offset->y;
|
||||
if (modeset->mode)
|
||||
drm_mode_destroy(dev, modeset->mode);
|
||||
modeset->mode = drm_mode_duplicate(dev,
|
||||
fb_crtc->desired_mode);
|
||||
modeset->connectors[modeset->num_connectors++] = fb_helper->connector_info[i]->connector;
|
||||
drm_connector_reference(connector);
|
||||
modeset->connectors[modeset->num_connectors++] = connector;
|
||||
modeset->fb = fb_helper->fb;
|
||||
modeset->x = offset->x;
|
||||
modeset->y = offset->y;
|
||||
}
|
||||
}
|
||||
|
||||
/* Clear out any old modes if there are no more connected outputs. */
|
||||
for (i = 0; i < fb_helper->crtc_count; i++) {
|
||||
modeset = &fb_helper->crtc_info[i].mode_set;
|
||||
if (modeset->num_connectors == 0) {
|
||||
BUG_ON(modeset->fb);
|
||||
if (modeset->mode)
|
||||
drm_mode_destroy(dev, modeset->mode);
|
||||
modeset->mode = NULL;
|
||||
}
|
||||
}
|
||||
out:
|
||||
kfree(crtcs);
|
||||
kfree(modes);
|
||||
|
|
|
@ -262,6 +262,26 @@ int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state,
|
|||
return 0;
|
||||
}
|
||||
|
||||
int exynos_atomic_check(struct drm_device *dev,
|
||||
struct drm_atomic_state *state)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = drm_atomic_helper_check_modeset(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = drm_atomic_normalize_zpos(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = drm_atomic_helper_check_planes(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int exynos_drm_open(struct drm_device *dev, struct drm_file *file)
|
||||
{
|
||||
struct drm_exynos_file_private *file_priv;
|
||||
|
|
|
@ -301,6 +301,7 @@ static inline int exynos_dpi_bind(struct drm_device *dev,
|
|||
|
||||
int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state,
|
||||
bool nonblock);
|
||||
int exynos_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
|
||||
|
||||
|
||||
extern struct platform_driver fimd_driver;
|
||||
|
|
|
@ -190,7 +190,7 @@ dma_addr_t exynos_drm_fb_dma_addr(struct drm_framebuffer *fb, int index)
|
|||
static const struct drm_mode_config_funcs exynos_drm_mode_config_funcs = {
|
||||
.fb_create = exynos_user_fb_create,
|
||||
.output_poll_changed = exynos_drm_output_poll_changed,
|
||||
.atomic_check = drm_atomic_helper_check,
|
||||
.atomic_check = exynos_atomic_check,
|
||||
.atomic_commit = exynos_atomic_commit,
|
||||
};
|
||||
|
||||
|
|
|
@ -1396,9 +1396,7 @@ static void cayman_pcie_gart_fini(struct radeon_device *rdev)
|
|||
void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
|
||||
int ring, u32 cp_int_cntl)
|
||||
{
|
||||
u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
|
||||
|
||||
WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
|
||||
WREG32(SRBM_GFX_CNTL, RINGID(ring));
|
||||
WREG32(CP_INT_CNTL, cp_int_cntl);
|
||||
}
|
||||
|
||||
|
|
|
@ -105,7 +105,7 @@ radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg
|
|||
|
||||
tmp &= AUX_HPD_SEL(0x7);
|
||||
tmp |= AUX_HPD_SEL(chan->rec.hpd);
|
||||
tmp |= AUX_EN | AUX_LS_READ_EN | AUX_HPD_DISCON(0x1);
|
||||
tmp |= AUX_EN | AUX_LS_READ_EN;
|
||||
|
||||
WREG32(AUX_CONTROL + aux_offset[instance], tmp);
|
||||
|
||||
|
|
|
@ -2999,6 +2999,49 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
|
|||
int i;
|
||||
struct si_dpm_quirk *p = si_dpm_quirk_list;
|
||||
|
||||
/* limit all SI kickers */
|
||||
if (rdev->family == CHIP_PITCAIRN) {
|
||||
if ((rdev->pdev->revision == 0x81) ||
|
||||
(rdev->pdev->device == 0x6810) ||
|
||||
(rdev->pdev->device == 0x6811) ||
|
||||
(rdev->pdev->device == 0x6816) ||
|
||||
(rdev->pdev->device == 0x6817) ||
|
||||
(rdev->pdev->device == 0x6806))
|
||||
max_mclk = 120000;
|
||||
} else if (rdev->family == CHIP_VERDE) {
|
||||
if ((rdev->pdev->revision == 0x81) ||
|
||||
(rdev->pdev->revision == 0x83) ||
|
||||
(rdev->pdev->revision == 0x87) ||
|
||||
(rdev->pdev->device == 0x6820) ||
|
||||
(rdev->pdev->device == 0x6821) ||
|
||||
(rdev->pdev->device == 0x6822) ||
|
||||
(rdev->pdev->device == 0x6823) ||
|
||||
(rdev->pdev->device == 0x682A) ||
|
||||
(rdev->pdev->device == 0x682B)) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
} else if (rdev->family == CHIP_OLAND) {
|
||||
if ((rdev->pdev->revision == 0xC7) ||
|
||||
(rdev->pdev->revision == 0x80) ||
|
||||
(rdev->pdev->revision == 0x81) ||
|
||||
(rdev->pdev->revision == 0x83) ||
|
||||
(rdev->pdev->device == 0x6604) ||
|
||||
(rdev->pdev->device == 0x6605)) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
} else if (rdev->family == CHIP_HAINAN) {
|
||||
if ((rdev->pdev->revision == 0x81) ||
|
||||
(rdev->pdev->revision == 0x83) ||
|
||||
(rdev->pdev->revision == 0xC3) ||
|
||||
(rdev->pdev->device == 0x6664) ||
|
||||
(rdev->pdev->device == 0x6665) ||
|
||||
(rdev->pdev->device == 0x6667)) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
}
|
||||
/* Apply dpm quirks */
|
||||
while (p && p->chip_device != 0) {
|
||||
if (rdev->pdev->vendor == p->chip_vendor &&
|
||||
|
@ -3011,16 +3054,6 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
|
|||
}
|
||||
++p;
|
||||
}
|
||||
/* limit mclk on all R7 370 parts for stability */
|
||||
if (rdev->pdev->device == 0x6811 &&
|
||||
rdev->pdev->revision == 0x81)
|
||||
max_mclk = 120000;
|
||||
/* limit sclk/mclk on Jet parts for stability */
|
||||
if (rdev->pdev->device == 0x6665 &&
|
||||
rdev->pdev->revision == 0xc3) {
|
||||
max_sclk = 75000;
|
||||
max_mclk = 80000;
|
||||
}
|
||||
|
||||
if (rps->vce_active) {
|
||||
rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
|
||||
|
|
|
@ -231,8 +231,16 @@ static int rcar_du_atomic_check(struct drm_device *dev,
|
|||
struct rcar_du_device *rcdu = dev->dev_private;
|
||||
int ret;
|
||||
|
||||
ret = drm_atomic_helper_check(dev, state);
|
||||
if (ret < 0)
|
||||
ret = drm_atomic_helper_check_modeset(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = drm_atomic_normalize_zpos(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = drm_atomic_helper_check_planes(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
|
||||
|
|
|
@ -195,6 +195,26 @@ static void sti_atomic_work(struct work_struct *work)
|
|||
sti_atomic_complete(private, private->commit.state);
|
||||
}
|
||||
|
||||
static int sti_atomic_check(struct drm_device *dev,
|
||||
struct drm_atomic_state *state)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = drm_atomic_helper_check_modeset(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = drm_atomic_normalize_zpos(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = drm_atomic_helper_check_planes(dev, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int sti_atomic_commit(struct drm_device *drm,
|
||||
struct drm_atomic_state *state, bool nonblock)
|
||||
{
|
||||
|
@ -248,7 +268,7 @@ static void sti_output_poll_changed(struct drm_device *ddev)
|
|||
static const struct drm_mode_config_funcs sti_mode_config_funcs = {
|
||||
.fb_create = drm_fb_cma_create,
|
||||
.output_poll_changed = sti_output_poll_changed,
|
||||
.atomic_check = drm_atomic_helper_check,
|
||||
.atomic_check = sti_atomic_check,
|
||||
.atomic_commit = sti_atomic_commit,
|
||||
};
|
||||
|
||||
|
|
|
@ -47,8 +47,14 @@ struct drm_crtc;
|
|||
* @src_h: height of visible portion of plane (in 16.16)
|
||||
* @rotation: rotation of the plane
|
||||
* @zpos: priority of the given plane on crtc (optional)
|
||||
* Note that multiple active planes on the same crtc can have an identical
|
||||
* zpos value. The rule to solving the conflict is to compare the plane
|
||||
* object IDs; the plane with a higher ID must be stacked on top of a
|
||||
* plane with a lower ID.
|
||||
* @normalized_zpos: normalized value of zpos: unique, range from 0 to N-1
|
||||
* where N is the number of active planes for given crtc
|
||||
* where N is the number of active planes for given crtc. Note that
|
||||
* the driver must call drm_atomic_normalize_zpos() to update this before
|
||||
* it can be trusted.
|
||||
* @src: clipped source coordinates of the plane (in 16.16)
|
||||
* @dst: clipped destination coordinates of the plane
|
||||
* @visible: visibility of the plane
|
||||
|
|
Loading…
Reference in a new issue