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drm/i915: rewrite hsw/bdw audio codec enable/disable sequences
There's some serious confusion regarding ELD valid bit that gets set and cleared back and forth etc. Rewrite it all based on the documented audio codec enable/disable sequences. v3: replace vblank wait with a comment v4: expand the comment on what should be done with the vblank wait Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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parent
c46f111f51
commit
5fad84a753
1 changed files with 57 additions and 70 deletions
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@ -132,14 +132,26 @@ static void g4x_audio_codec_enable(struct drm_connector *connector,
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static void hsw_audio_codec_disable(struct intel_encoder *encoder)
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{
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struct drm_device *dev = encoder->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = encoder->base.crtc;
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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enum pipe pipe = intel_crtc->pipe;
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uint32_t tmp;
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DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
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/* Disable timestamps */
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tmp = I915_READ(HSW_AUD_CFG(pipe));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp |= AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_UPPER_N_MASK;
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tmp &= ~AUD_CONFIG_LOWER_N_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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I915_WRITE(HSW_AUD_CFG(pipe), tmp);
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/* Invalidate ELD */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
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tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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}
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@ -149,77 +161,52 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
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{
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struct drm_i915_private *dev_priv = connector->dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
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uint8_t *eld = connector->eld;
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uint32_t eldv;
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enum pipe pipe = intel_crtc->pipe;
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const uint8_t *eld = connector->eld;
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uint32_t tmp;
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int len, i;
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enum pipe pipe = intel_crtc->pipe;
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enum port port;
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int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
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int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
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int aud_config = HSW_AUD_CFG(pipe);
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int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
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/* Audio output enable */
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DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
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tmp = I915_READ(aud_cntrl_st2);
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tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
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I915_WRITE(aud_cntrl_st2, tmp);
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POSTING_READ(aud_cntrl_st2);
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DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
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pipe_name(pipe), eld[2]);
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/* Set ELD valid state */
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tmp = I915_READ(aud_cntrl_st2);
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DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
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tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
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I915_WRITE(aud_cntrl_st2, tmp);
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tmp = I915_READ(aud_cntrl_st2);
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DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
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/* Enable HDMI mode */
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tmp = I915_READ(aud_config);
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DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
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/* clear N_programing_enable and N_value_index */
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tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
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I915_WRITE(aud_config, tmp);
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DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
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eldv = AUDIO_ELD_VALID_A << (pipe * 4);
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
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else
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I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
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if (intel_eld_uptodate(connector,
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aud_cntrl_st2, eldv,
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aud_cntl_st, IBX_ELD_ADDRESS_MASK,
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hdmiw_hdmiedid))
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return;
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tmp = I915_READ(aud_cntrl_st2);
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tmp &= ~eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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tmp = I915_READ(aud_cntl_st);
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tmp &= ~IBX_ELD_ADDRESS_MASK;
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I915_WRITE(aud_cntl_st, tmp);
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port = (tmp >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
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DRM_DEBUG_DRIVER("port num:%d\n", port);
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len = min_t(int, eld[2], 21); /* 84 bytes of hw ELD buffer */
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DRM_DEBUG_DRIVER("ELD size %d\n", len);
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for (i = 0; i < len; i++)
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I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
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tmp = I915_READ(aud_cntrl_st2);
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tmp |= eldv;
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I915_WRITE(aud_cntrl_st2, tmp);
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/* XXX: Transitional */
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/* Enable audio presence detect, invalidate ELD */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4));
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tmp |= AUDIO_OUTPUT_ENABLE_A << (pipe * 4);
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tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4));
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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/*
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* FIXME: We're supposed to wait for vblank here, but we have vblanks
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* disabled during the mode set. The proper fix would be to push the
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* rest of the setup into a vblank work item, queued here, but the
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* infrastructure is not there yet.
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*/
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/* Reset ELD write address */
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tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
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tmp &= ~IBX_ELD_ADDRESS_MASK;
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I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
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/* Up to 84 bytes of hw ELD buffer */
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len = min_t(int, eld[2], 21);
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for (i = 0; i < len; i++)
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I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
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/* ELD valid */
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tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
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tmp |= AUDIO_ELD_VALID_A << (pipe * 4);
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I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
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/* Enable timestamps */
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tmp = I915_READ(HSW_AUD_CFG(pipe));
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tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
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tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
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tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
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if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT))
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tmp |= AUD_CONFIG_N_VALUE_INDEX;
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else
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tmp |= audio_config_hdmi_pixel_clock(mode);
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I915_WRITE(HSW_AUD_CFG(pipe), tmp);
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}
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static void ilk_audio_codec_enable(struct drm_connector *connector,
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