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media: staging: atomisp: Remove dead code for MID (#1)
Remove dead code. If someone needs it the P-Unit semaphore is handled by I2C DesignWare driver (drivers/i2c/busses/i2c-designware-baytrail.c). Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
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2 changed files with 0 additions and 103 deletions
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@ -33,5 +33,3 @@ void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data);
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u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext);
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void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data);
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u32 intel_mid_soc_stepping(void);
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int intel_mid_dw_i2c_acquire_ownership(void);
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int intel_mid_dw_i2c_release_ownership(void);
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@ -14,13 +14,6 @@
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#define INTEL_ATOM_BYT 0x37
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#define INTEL_ATOM_MOORFLD 0x5a
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#define INTEL_ATOM_CHT 0x4c
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/* synchronization for sharing the I2C controller */
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#define PUNIT_PORT 0x04
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#define PUNIT_DOORBELL_OPCODE (0xE0)
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#define PUNIT_DOORBELL_REG (0x0)
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#ifndef CSTATE_EXIT_LATENCY
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#define CSTATE_EXIT_LATENCY_C1 1
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#endif
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static inline int platform_is(u8 model)
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{
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return (boot_cpu_data.x86_model == model);
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@ -201,97 +194,3 @@ static void pci_d3_delay_fixup(struct pci_dev *dev)
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3_delay_fixup);
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#define PUNIT_SEMAPHORE (platform_is(INTEL_ATOM_BYT) ? 0x7 : 0x10E)
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#define GET_SEM() (intel_mid_msgbus_read32(PUNIT_PORT, PUNIT_SEMAPHORE) & 0x1)
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static void reset_semaphore(void)
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{
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u32 data;
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data = intel_mid_msgbus_read32(PUNIT_PORT, PUNIT_SEMAPHORE);
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smp_mb();
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data = data & 0xfffffffc;
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intel_mid_msgbus_write32(PUNIT_PORT, PUNIT_SEMAPHORE, data);
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smp_mb();
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}
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int intel_mid_dw_i2c_acquire_ownership(void)
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{
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u32 ret = 0;
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u32 data = 0; /* data sent to PUNIT */
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u32 cmd;
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u32 cmdext;
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int timeout = 1000;
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if (DW_I2C_NEED_QOS)
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pm_qos_update_request(&pm_qos, CSTATE_EXIT_LATENCY_C1 - 1);
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/*
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* We need disable irq. Otherwise, the main thread
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* might be preempted and the other thread jumps to
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* disable irq for a long time. Another case is
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* some irq handlers might trigger power voltage change
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*/
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BUG_ON(irqs_disabled());
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local_irq_disable();
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/* host driver writes 0x2 to side band register 0x7 */
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intel_mid_msgbus_write32(PUNIT_PORT, PUNIT_SEMAPHORE, 0x2);
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smp_mb();
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/* host driver sends 0xE0 opcode to PUNIT and writes 0 register */
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cmd = (PUNIT_DOORBELL_OPCODE << 24) | (PUNIT_PORT << 16) |
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((PUNIT_DOORBELL_REG & 0xFF) << 8) | PCI_ROOT_MSGBUS_DWORD_ENABLE;
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cmdext = PUNIT_DOORBELL_REG & 0xffffff00;
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if (cmdext)
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intel_mid_msgbus_write32_raw_ext(cmd, cmdext, data);
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else
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intel_mid_msgbus_write32_raw(cmd, data);
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/* host driver waits for bit 0 to be set in side band 0x7 */
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while (GET_SEM() != 0x1) {
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udelay(100);
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timeout--;
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if (timeout <= 0) {
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pr_err("Timeout: semaphore timed out, reset sem\n");
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ret = -ETIMEDOUT;
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reset_semaphore();
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/*Delay 1ms in case race with punit*/
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udelay(1000);
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if (GET_SEM() != 0) {
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/*Reset again as kernel might race with punit*/
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reset_semaphore();
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}
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pr_err("PUNIT SEM: %d\n",
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intel_mid_msgbus_read32(PUNIT_PORT,
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PUNIT_SEMAPHORE));
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local_irq_enable();
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if (DW_I2C_NEED_QOS) {
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pm_qos_update_request(&pm_qos,
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PM_QOS_DEFAULT_VALUE);
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}
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return ret;
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}
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}
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smp_mb();
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return ret;
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}
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EXPORT_SYMBOL(intel_mid_dw_i2c_acquire_ownership);
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int intel_mid_dw_i2c_release_ownership(void)
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{
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reset_semaphore();
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local_irq_enable();
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if (DW_I2C_NEED_QOS)
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pm_qos_update_request(&pm_qos, PM_QOS_DEFAULT_VALUE);
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return 0;
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}
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EXPORT_SYMBOL(intel_mid_dw_i2c_release_ownership);
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