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drm/i915/mtl: add initial definitions for GSC CS
Starting on MTL, the GSC is no longer managed with direct MMIO access, but we instead have a dedicated command streamer for it. As a first step for adding support for this CS, add the required definitions. Note that, although it is now a CS, the GSC retains its old class:instance value (OTHER_CLASS instance 6) Bspec: 65308, 45605 Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221102171047.2787951-2-daniele.ceraolospurio@intel.com
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4 changed files with 11 additions and 0 deletions
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@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
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{ .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
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}
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},
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[GSC0] = {
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.class = OTHER_CLASS,
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.instance = OTHER_GSC_INSTANCE,
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.mmio_bases = {
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{ .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
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}
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},
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};
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/**
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@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
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case VIDEO_DECODE_CLASS:
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case VIDEO_ENHANCEMENT_CLASS:
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case COPY_ENGINE_CLASS:
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case OTHER_CLASS:
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if (GRAPHICS_VER(gt->i915) < 8)
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return 0;
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return GEN8_LR_CONTEXT_OTHER_SIZE;
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@ -136,6 +136,7 @@ enum intel_engine_id {
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CCS2,
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CCS3,
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#define _CCS(n) (CCS0 + (n))
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GSC0,
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I915_NUM_ENGINES
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#define INVALID_ENGINE ((enum intel_engine_id)-1)
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};
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@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
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[COPY_ENGINE_CLASS] = "bcs",
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[VIDEO_DECODE_CLASS] = "vcs",
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[VIDEO_ENHANCEMENT_CLASS] = "vecs",
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[OTHER_CLASS] = "other",
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[COMPUTE_CLASS] = "ccs",
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};
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@ -970,6 +970,7 @@
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#define GEN11_VEBOX2_RING_BASE 0x1d8000
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#define XEHP_VEBOX3_RING_BASE 0x1e8000
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#define XEHP_VEBOX4_RING_BASE 0x1f8000
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#define MTL_GSC_RING_BASE 0x11a000
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#define GEN12_COMPUTE0_RING_BASE 0x1a000
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#define GEN12_COMPUTE1_RING_BASE 0x1c000
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#define GEN12_COMPUTE2_RING_BASE 0x1e000
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