mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-30 16:07:39 +00:00
amd, mediatek, exynos and hdlcd fixes.
-----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJYN7+wAAoJEAx081l5xIa++uYQAKPoS2yg+EQytgBmAVJxQ0Vi Z8O+z6rPOubHvXHqdAswNbZaxYxiL1RGyn1nYYNpLMTNOF2md8KrYvxc7irikcnC qxTCtZCkWRsUjzprxea+koaq3m6wBT4ToK+jl+mxVsSo/vCtYVWu/zgPnW9Drqiy Z9XfrwESDwMYK/tVCorucBNmzHvleJ+AngpsAyE6KZHy2eOyDiunIDMnAyPi9S2C KdC6jaHTv3p7Z/xyEw7gGvyqPFrX50kmphLY8O3+KBJfosifMuXLJV/p41iX0aI8 8P3lwQpb3h9Fv9urCXjXU+i8F3L7A6y4RuKCvZtKNGpas6jRrOGojkQJhD17EdvT N7D5ijIskCeoMFwaJ2kUMupY06rzt1CaNJAXpGbryR1bLUvyJysMWNDKHgPC5jUS MZIhqArUqht1DzFup25fx54CAAbb+4zOBiX9Jgq5zqqiq8i2XAWRoMT+fvJ6H5BL T819KKneKpS/uK61m8xPhopdOB1wU0rNvsOVYjXMxT4xTrbXODllO+Mm1eAuAPwh qfyCdhwspoDlaXwDFtkG9EyJpSeq6+A8DZS8DYz9wdcAhbHuy4kuMIYCeXCEfhsf xclxRVrzG3cWsu6QeEXdVjfVyN9fuhyzOJxkVzFVyfesiY0OHYoOY1AAouuO36q+ X2avUsWc8qtG6ap/rgWJ =N8S/ -----END PGP SIGNATURE----- Merge tag 'drm-fixes-for-v4.9-rc7' of git://people.freedesktop.org/~airlied/linux Pull drm fixes from Dave Airlie: "Seems to be quietening down nicely, a few mediatek, one exynos and one hdlcd fix, along with two amd fixes" * tag 'drm-fixes-for-v4.9-rc7' of git://people.freedesktop.org/~airlied/linux: gpu/drm/exynos/exynos_hdmi - Unmap region obtained by of_iomap drm/mediatek: fix null pointer dereference drm/mediatek: fixed the calc method of data rate per lane drm/mediatek: fix a typo of DISP_OD_CFG to OD_RELAYMODE drm/radeon: fix power state when port pm is unavailable (v2) drm/amdgpu: fix power state when port pm is unavailable drm/arm: hdlcd: fix plane base address update drm/amd/powerplay: avoid out of bounds access on array ps.
This commit is contained in:
commit
6006d6e719
8 changed files with 87 additions and 37 deletions
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@ -34,6 +34,7 @@ struct amdgpu_atpx {
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static struct amdgpu_atpx_priv {
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static struct amdgpu_atpx_priv {
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bool atpx_detected;
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bool atpx_detected;
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bool bridge_pm_usable;
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/* handle for device - and atpx */
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/* handle for device - and atpx */
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acpi_handle dhandle;
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acpi_handle dhandle;
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acpi_handle other_handle;
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acpi_handle other_handle;
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@ -205,7 +206,11 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx)
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atpx->is_hybrid = false;
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atpx->is_hybrid = false;
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if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
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if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
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printk("ATPX Hybrid Graphics\n");
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printk("ATPX Hybrid Graphics\n");
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atpx->functions.power_cntl = false;
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/*
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* Disable legacy PM methods only when pcie port PM is usable,
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* otherwise the device might fail to power off or power on.
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*/
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atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable;
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atpx->is_hybrid = true;
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atpx->is_hybrid = true;
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}
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}
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@ -480,6 +485,7 @@ static int amdgpu_atpx_power_state(enum vga_switcheroo_client_id id,
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*/
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*/
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static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
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static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
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{
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{
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struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
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acpi_handle dhandle, atpx_handle;
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acpi_handle dhandle, atpx_handle;
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acpi_status status;
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acpi_status status;
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@ -494,6 +500,7 @@ static bool amdgpu_atpx_pci_probe_handle(struct pci_dev *pdev)
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}
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}
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amdgpu_atpx_priv.dhandle = dhandle;
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amdgpu_atpx_priv.dhandle = dhandle;
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amdgpu_atpx_priv.atpx.handle = atpx_handle;
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amdgpu_atpx_priv.atpx.handle = atpx_handle;
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amdgpu_atpx_priv.bridge_pm_usable = parent_pdev && parent_pdev->bridge_d3;
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return true;
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return true;
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}
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}
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@ -2984,19 +2984,19 @@ static int smu7_get_pp_table_entry_callback_func_v0(struct pp_hwmgr *hwmgr,
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if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
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if (!(data->mc_micro_code_feature & DISABLE_MC_LOADMICROCODE) && memory_clock > data->highest_mclk)
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data->highest_mclk = memory_clock;
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data->highest_mclk = memory_clock;
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performance_level = &(ps->performance_levels
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[ps->performance_level_count++]);
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PP_ASSERT_WITH_CODE(
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PP_ASSERT_WITH_CODE(
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(ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
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(ps->performance_level_count < smum_get_mac_definition(hwmgr->smumgr, SMU_MAX_LEVELS_GRAPHICS)),
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"Performance levels exceeds SMC limit!",
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"Performance levels exceeds SMC limit!",
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return -EINVAL);
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return -EINVAL);
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PP_ASSERT_WITH_CODE(
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PP_ASSERT_WITH_CODE(
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(ps->performance_level_count <=
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(ps->performance_level_count <
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hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
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hwmgr->platform_descriptor.hardwareActivityPerformanceLevels),
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"Performance levels exceeds Driver limit!",
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"Performance levels exceeds Driver limit, Skip!",
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return -EINVAL);
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return 0);
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performance_level = &(ps->performance_levels
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[ps->performance_level_count++]);
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/* Performance levels are arranged from low to high. */
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/* Performance levels are arranged from low to high. */
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performance_level->memory_clock = memory_clock;
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performance_level->memory_clock = memory_clock;
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@ -150,15 +150,14 @@ static void hdlcd_crtc_enable(struct drm_crtc *crtc)
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clk_prepare_enable(hdlcd->clk);
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clk_prepare_enable(hdlcd->clk);
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hdlcd_crtc_mode_set_nofb(crtc);
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hdlcd_crtc_mode_set_nofb(crtc);
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
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drm_crtc_vblank_on(crtc);
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}
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}
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static void hdlcd_crtc_disable(struct drm_crtc *crtc)
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static void hdlcd_crtc_disable(struct drm_crtc *crtc)
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{
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{
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
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if (!crtc->state->active)
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drm_crtc_vblank_off(crtc);
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return;
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
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hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
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clk_disable_unprepare(hdlcd->clk);
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clk_disable_unprepare(hdlcd->clk);
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}
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}
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@ -1907,6 +1907,8 @@ static int hdmi_probe(struct platform_device *pdev)
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err_hdmiphy:
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err_hdmiphy:
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if (hdata->hdmiphy_port)
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if (hdata->hdmiphy_port)
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put_device(&hdata->hdmiphy_port->dev);
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put_device(&hdata->hdmiphy_port->dev);
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if (hdata->regs_hdmiphy)
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iounmap(hdata->regs_hdmiphy);
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err_ddc:
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err_ddc:
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put_device(&hdata->ddc_adpt->dev);
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put_device(&hdata->ddc_adpt->dev);
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@ -1929,6 +1931,9 @@ static int hdmi_remove(struct platform_device *pdev)
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if (hdata->hdmiphy_port)
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if (hdata->hdmiphy_port)
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put_device(&hdata->hdmiphy_port->dev);
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put_device(&hdata->hdmiphy_port->dev);
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if (hdata->regs_hdmiphy)
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iounmap(hdata->regs_hdmiphy);
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put_device(&hdata->ddc_adpt->dev);
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put_device(&hdata->ddc_adpt->dev);
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return 0;
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return 0;
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@ -251,13 +251,6 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
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if (irq < 0)
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if (irq < 0)
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return irq;
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return irq;
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ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
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IRQF_TRIGGER_NONE, dev_name(dev), priv);
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if (ret < 0) {
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dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
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return ret;
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}
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comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL);
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comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL);
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if (comp_id < 0) {
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if (comp_id < 0) {
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dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
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dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
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@ -273,6 +266,13 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, priv);
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platform_set_drvdata(pdev, priv);
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ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
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IRQF_TRIGGER_NONE, dev_name(dev), priv);
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if (ret < 0) {
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dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
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return ret;
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}
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ret = component_add(dev, &mtk_disp_ovl_component_ops);
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ret = component_add(dev, &mtk_disp_ovl_component_ops);
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if (ret)
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if (ret)
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dev_err(dev, "Failed to add component: %d\n", ret);
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dev_err(dev, "Failed to add component: %d\n", ret);
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@ -123,7 +123,7 @@ static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
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unsigned int bpc)
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unsigned int bpc)
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{
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{
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writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
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writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
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writel(OD_RELAYMODE, comp->regs + OD_RELAYMODE);
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writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
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mtk_dither_set(comp, bpc, DISP_OD_CFG);
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mtk_dither_set(comp, bpc, DISP_OD_CFG);
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}
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}
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@ -86,7 +86,7 @@
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#define DSI_PHY_TIMECON0 0x110
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#define DSI_PHY_TIMECON0 0x110
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#define LPX (0xff << 0)
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#define LPX (0xff << 0)
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#define HS_PRPR (0xff << 8)
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#define HS_PREP (0xff << 8)
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#define HS_ZERO (0xff << 16)
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#define HS_ZERO (0xff << 16)
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#define HS_TRAIL (0xff << 24)
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#define HS_TRAIL (0xff << 24)
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@ -102,10 +102,16 @@
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#define CLK_TRAIL (0xff << 24)
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#define CLK_TRAIL (0xff << 24)
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#define DSI_PHY_TIMECON3 0x11c
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#define DSI_PHY_TIMECON3 0x11c
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#define CLK_HS_PRPR (0xff << 0)
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#define CLK_HS_PREP (0xff << 0)
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#define CLK_HS_POST (0xff << 8)
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#define CLK_HS_POST (0xff << 8)
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#define CLK_HS_EXIT (0xff << 16)
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#define CLK_HS_EXIT (0xff << 16)
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#define T_LPX 5
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#define T_HS_PREP 6
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#define T_HS_TRAIL 8
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#define T_HS_EXIT 7
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#define T_HS_ZERO 10
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#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
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#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
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struct phy;
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struct phy;
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@ -161,20 +167,18 @@ static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
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static void dsi_phy_timconfig(struct mtk_dsi *dsi)
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static void dsi_phy_timconfig(struct mtk_dsi *dsi)
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{
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{
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u32 timcon0, timcon1, timcon2, timcon3;
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u32 timcon0, timcon1, timcon2, timcon3;
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unsigned int ui, cycle_time;
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u32 ui, cycle_time;
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unsigned int lpx;
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ui = 1000 / dsi->data_rate + 0x01;
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ui = 1000 / dsi->data_rate + 0x01;
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cycle_time = 8000 / dsi->data_rate + 0x01;
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cycle_time = 8000 / dsi->data_rate + 0x01;
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lpx = 5;
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timcon0 = (8 << 24) | (0xa << 16) | (0x6 << 8) | lpx;
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timcon0 = T_LPX | T_HS_PREP << 8 | T_HS_ZERO << 16 | T_HS_TRAIL << 24;
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timcon1 = (7 << 24) | (5 * lpx << 16) | ((3 * lpx) / 2) << 8 |
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timcon1 = 4 * T_LPX | (3 * T_LPX / 2) << 8 | 5 * T_LPX << 16 |
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(4 * lpx);
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T_HS_EXIT << 24;
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timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
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timcon2 = ((NS_TO_CYCLE(0x64, cycle_time) + 0xa) << 24) |
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(NS_TO_CYCLE(0x150, cycle_time) << 16);
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(NS_TO_CYCLE(0x150, cycle_time) << 16);
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timcon3 = (2 * lpx) << 16 | NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8 |
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timcon3 = NS_TO_CYCLE(0x40, cycle_time) | (2 * T_LPX) << 16 |
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NS_TO_CYCLE(0x40, cycle_time);
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NS_TO_CYCLE(80 + 52 * ui, cycle_time) << 8;
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|
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writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
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writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
|
||||||
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
|
writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
|
||||||
|
@ -202,19 +206,47 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
|
||||||
{
|
{
|
||||||
struct device *dev = dsi->dev;
|
struct device *dev = dsi->dev;
|
||||||
int ret;
|
int ret;
|
||||||
|
u64 pixel_clock, total_bits;
|
||||||
|
u32 htotal, htotal_bits, bit_per_pixel, overhead_cycles, overhead_bits;
|
||||||
|
|
||||||
if (++dsi->refcount != 1)
|
if (++dsi->refcount != 1)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
/**
|
switch (dsi->format) {
|
||||||
* data_rate = (pixel_clock / 1000) * pixel_dipth * mipi_ratio;
|
case MIPI_DSI_FMT_RGB565:
|
||||||
* pixel_clock unit is Khz, data_rata unit is MHz, so need divide 1000.
|
bit_per_pixel = 16;
|
||||||
* mipi_ratio is mipi clk coefficient for balance the pixel clk in mipi.
|
break;
|
||||||
* we set mipi_ratio is 1.05.
|
case MIPI_DSI_FMT_RGB666_PACKED:
|
||||||
*/
|
bit_per_pixel = 18;
|
||||||
dsi->data_rate = dsi->vm.pixelclock * 3 * 21 / (1 * 1000 * 10);
|
break;
|
||||||
|
case MIPI_DSI_FMT_RGB666:
|
||||||
|
case MIPI_DSI_FMT_RGB888:
|
||||||
|
default:
|
||||||
|
bit_per_pixel = 24;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate * 1000000);
|
/**
|
||||||
|
* vm.pixelclock is in kHz, pixel_clock unit is Hz, so multiply by 1000
|
||||||
|
* htotal_time = htotal * byte_per_pixel / num_lanes
|
||||||
|
* overhead_time = lpx + hs_prepare + hs_zero + hs_trail + hs_exit
|
||||||
|
* mipi_ratio = (htotal_time + overhead_time) / htotal_time
|
||||||
|
* data_rate = pixel_clock * bit_per_pixel * mipi_ratio / num_lanes;
|
||||||
|
*/
|
||||||
|
pixel_clock = dsi->vm.pixelclock * 1000;
|
||||||
|
htotal = dsi->vm.hactive + dsi->vm.hback_porch + dsi->vm.hfront_porch +
|
||||||
|
dsi->vm.hsync_len;
|
||||||
|
htotal_bits = htotal * bit_per_pixel;
|
||||||
|
|
||||||
|
overhead_cycles = T_LPX + T_HS_PREP + T_HS_ZERO + T_HS_TRAIL +
|
||||||
|
T_HS_EXIT;
|
||||||
|
overhead_bits = overhead_cycles * dsi->lanes * 8;
|
||||||
|
total_bits = htotal_bits + overhead_bits;
|
||||||
|
|
||||||
|
dsi->data_rate = DIV_ROUND_UP_ULL(pixel_clock * total_bits,
|
||||||
|
htotal * dsi->lanes);
|
||||||
|
|
||||||
|
ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
dev_err(dev, "Failed to set data rate: %d\n", ret);
|
dev_err(dev, "Failed to set data rate: %d\n", ret);
|
||||||
goto err_refcount;
|
goto err_refcount;
|
||||||
|
|
|
@ -34,6 +34,7 @@ struct radeon_atpx {
|
||||||
|
|
||||||
static struct radeon_atpx_priv {
|
static struct radeon_atpx_priv {
|
||||||
bool atpx_detected;
|
bool atpx_detected;
|
||||||
|
bool bridge_pm_usable;
|
||||||
/* handle for device - and atpx */
|
/* handle for device - and atpx */
|
||||||
acpi_handle dhandle;
|
acpi_handle dhandle;
|
||||||
struct radeon_atpx atpx;
|
struct radeon_atpx atpx;
|
||||||
|
@ -203,7 +204,11 @@ static int radeon_atpx_validate(struct radeon_atpx *atpx)
|
||||||
atpx->is_hybrid = false;
|
atpx->is_hybrid = false;
|
||||||
if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
|
if (valid_bits & ATPX_MS_HYBRID_GFX_SUPPORTED) {
|
||||||
printk("ATPX Hybrid Graphics\n");
|
printk("ATPX Hybrid Graphics\n");
|
||||||
atpx->functions.power_cntl = false;
|
/*
|
||||||
|
* Disable legacy PM methods only when pcie port PM is usable,
|
||||||
|
* otherwise the device might fail to power off or power on.
|
||||||
|
*/
|
||||||
|
atpx->functions.power_cntl = !radeon_atpx_priv.bridge_pm_usable;
|
||||||
atpx->is_hybrid = true;
|
atpx->is_hybrid = true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -474,6 +479,7 @@ static int radeon_atpx_power_state(enum vga_switcheroo_client_id id,
|
||||||
*/
|
*/
|
||||||
static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
|
static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
|
||||||
{
|
{
|
||||||
|
struct pci_dev *parent_pdev = pci_upstream_bridge(pdev);
|
||||||
acpi_handle dhandle, atpx_handle;
|
acpi_handle dhandle, atpx_handle;
|
||||||
acpi_status status;
|
acpi_status status;
|
||||||
|
|
||||||
|
@ -487,6 +493,7 @@ static bool radeon_atpx_pci_probe_handle(struct pci_dev *pdev)
|
||||||
|
|
||||||
radeon_atpx_priv.dhandle = dhandle;
|
radeon_atpx_priv.dhandle = dhandle;
|
||||||
radeon_atpx_priv.atpx.handle = atpx_handle;
|
radeon_atpx_priv.atpx.handle = atpx_handle;
|
||||||
|
radeon_atpx_priv.bridge_pm_usable = parent_pdev && parent_pdev->bridge_d3;
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue