KVM: x86: Add helpers to query individual CR0/CR4 bits
Add helpers to check if a specific CR0/CR4 bit is set to avoid a plethora of implicit casts from the "unsigned long" return of kvm_read_cr*_bits(), and to make each caller's intent more obvious. Defer converting helpers that do truly ugly casts from "unsigned long" to "int", e.g. is_pse(), to a future commit so that their conversion is more isolated. Opportunistically drop the superfluous pcid_enabled from kvm_set_cr3(); the local variable is used only once, immediately after its declaration. Suggested-by: Sean Christopherson <seanjc@google.com> Signed-off-by: Binbin Wu <binbin.wu@linux.intel.com> Link: https://lore.kernel.org/r/20230322045824.22970-2-binbin.wu@linux.intel.com [sean: move "obvious" conversions to this commit, massage changelog] Signed-off-by: Sean Christopherson <seanjc@google.com>
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@ -266,7 +266,7 @@ static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_e
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/* Update OSXSAVE bit */
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if (boot_cpu_has(X86_FEATURE_XSAVE))
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cpuid_entry_change(best, X86_FEATURE_OSXSAVE,
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kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE));
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kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE));
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cpuid_entry_change(best, X86_FEATURE_APIC,
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vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE);
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@ -275,7 +275,7 @@ static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_e
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best = cpuid_entry2_find(entries, nent, 7, 0);
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if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7)
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cpuid_entry_change(best, X86_FEATURE_OSPKE,
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kvm_read_cr4_bits(vcpu, X86_CR4_PKE));
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kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE));
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best = cpuid_entry2_find(entries, nent, 0xD, 0);
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if (best)
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@ -157,6 +157,14 @@ static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask)
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return vcpu->arch.cr0 & mask;
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}
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static __always_inline bool kvm_is_cr0_bit_set(struct kvm_vcpu *vcpu,
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unsigned long cr0_bit)
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{
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BUILD_BUG_ON(!is_power_of_2(cr0_bit));
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return !!kvm_read_cr0_bits(vcpu, cr0_bit);
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}
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static inline ulong kvm_read_cr0(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, ~0UL);
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@ -171,6 +179,14 @@ static inline ulong kvm_read_cr4_bits(struct kvm_vcpu *vcpu, ulong mask)
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return vcpu->arch.cr4 & mask;
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}
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static __always_inline bool kvm_is_cr4_bit_set(struct kvm_vcpu *vcpu,
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unsigned long cr4_bit)
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{
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BUILD_BUG_ON(!is_power_of_2(cr4_bit));
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return !!kvm_read_cr4_bits(vcpu, cr4_bit);
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}
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static inline ulong kvm_read_cr3(struct kvm_vcpu *vcpu)
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{
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if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3))
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@ -132,7 +132,7 @@ static inline unsigned long kvm_get_pcid(struct kvm_vcpu *vcpu, gpa_t cr3)
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{
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BUILD_BUG_ON((X86_CR3_PCID_MASK & PAGE_MASK) != 0);
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return kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)
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return kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)
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? cr3 & X86_CR3_PCID_MASK
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: 0;
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}
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@ -540,9 +540,9 @@ int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned idx, u64 *data)
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if (!pmc)
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return 1;
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if (!(kvm_read_cr4_bits(vcpu, X86_CR4_PCE)) &&
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if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCE) &&
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(static_call(kvm_x86_get_cpl)(vcpu) != 0) &&
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(kvm_read_cr0_bits(vcpu, X86_CR0_PE)))
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kvm_is_cr0_bit_set(vcpu, X86_CR0_PE))
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return 1;
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*data = pmc_read_counter(pmc) & mask;
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@ -5154,7 +5154,7 @@ static int handle_vmxon(struct kvm_vcpu *vcpu)
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* does force CR0.PE=1, but only to also force VM86 in order to emulate
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* Real Mode, and so there's no need to check CR0.PE manually.
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*/
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if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE)) {
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if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_VMXE)) {
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kvm_queue_exception(vcpu, UD_VECTOR);
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return 1;
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}
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@ -5180,7 +5180,7 @@ bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu)
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if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
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return true;
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return vmx_get_cpl(vcpu) == 3 && kvm_read_cr0_bits(vcpu, X86_CR0_AM) &&
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return vmx_get_cpl(vcpu) == 3 && kvm_is_cr0_bit_set(vcpu, X86_CR0_AM) &&
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(kvm_get_rflags(vcpu) & X86_EFLAGS_AC);
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}
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@ -841,7 +841,7 @@ bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
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bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
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{
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if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
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if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE))
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return true;
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kvm_queue_exception(vcpu, UD_VECTOR);
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@ -983,7 +983,7 @@ int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
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return 1;
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if (!(cr0 & X86_CR0_PG) &&
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(is_64_bit_mode(vcpu) || kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)))
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(is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
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return 1;
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static_call(kvm_x86_set_cr0)(vcpu, cr0);
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@ -1005,7 +1005,7 @@ void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
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if (vcpu->arch.guest_state_protected)
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return;
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if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
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if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
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if (vcpu->arch.xcr0 != host_xcr0)
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xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
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@ -1019,7 +1019,7 @@ void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
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if (static_cpu_has(X86_FEATURE_PKU) &&
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vcpu->arch.pkru != vcpu->arch.host_pkru &&
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((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
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kvm_read_cr4_bits(vcpu, X86_CR4_PKE)))
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kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)))
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write_pkru(vcpu->arch.pkru);
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#endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
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}
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@ -1033,14 +1033,14 @@ void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
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#ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
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if (static_cpu_has(X86_FEATURE_PKU) &&
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((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
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kvm_read_cr4_bits(vcpu, X86_CR4_PKE))) {
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kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
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vcpu->arch.pkru = rdpkru();
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if (vcpu->arch.pkru != vcpu->arch.host_pkru)
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write_pkru(vcpu->arch.host_pkru);
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}
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#endif /* CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS */
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if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)) {
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if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
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if (vcpu->arch.xcr0 != host_xcr0)
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xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
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@ -1245,7 +1245,7 @@ static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
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* PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
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* with PCIDE=0.
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*/
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if (!kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
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if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))
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return;
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for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
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@ -1260,9 +1260,7 @@ int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
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bool skip_tlb_flush = false;
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unsigned long pcid = 0;
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#ifdef CONFIG_X86_64
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bool pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
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if (pcid_enabled) {
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if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
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skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
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cr3 &= ~X86_CR3_PCID_NOFLUSH;
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pcid = cr3 & X86_CR3_PCID_MASK;
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@ -5051,7 +5049,7 @@ static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
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return 0;
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if (mce->status & MCI_STATUS_UC) {
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if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
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!kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
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!kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) {
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kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
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return 0;
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}
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@ -13254,7 +13252,7 @@ int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
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return 1;
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}
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pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
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pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE);
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switch (type) {
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case INVPCID_TYPE_INDIV_ADDR:
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@ -123,7 +123,7 @@ static inline bool kvm_exception_is_soft(unsigned int nr)
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static inline bool is_protmode(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr0_bits(vcpu, X86_CR0_PE);
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return kvm_is_cr0_bit_set(vcpu, X86_CR0_PE);
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}
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static inline int is_long_mode(struct kvm_vcpu *vcpu)
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@ -193,7 +193,7 @@ static inline bool is_pae_paging(struct kvm_vcpu *vcpu)
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static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
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{
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return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
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return kvm_is_cr4_bit_set(vcpu, X86_CR4_LA57) ? 57 : 48;
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}
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static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
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