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Code Issues Releases Wiki Activity

clk: mediatek: Replace 'struct clk' with 'struct clk_hw'

Browse source 
As part of the effort to improve the MediaTek clk drivers, the next step
is to switch from the old 'struct clk' clk prodivder APIs to the new
'struct clk_hw' ones.

Instead of adding new APIs to the MediaTek clk driver library mirroring
the existing ones, moving all drivers to the new APIs, and then removing
the old ones, just migrate everything at the same time. This involves
replacing 'struct clk' with 'struct clk_hw', and 'struct clk_onecell_data'
with 'struct clk_hw_onecell_data', and fixing up all usages.

For now, the clk_register() and co. usage is retained, with __clk_get_hw()
and (struct clk_hw *)->clk used to bridge the difference between the APIs.
These will be replaced in subsequent patches.

Fix up mtk_{alloc,free}_clk_data to use 'struct clk_hw' by hand. Fix up
all other affected call sites with the following coccinelle script.

    // Replace type
    @@
    @@
    - struct clk_onecell_data
    + struct clk_hw_onecell_data

    // Replace of_clk_add_provider() & of_clk_src_simple_get()
    @@
    expression NP, DATA;
    symbol of_clk_src_onecell_get;
    @@
    - of_clk_add_provider(
    + of_clk_add_hw_provider(
	    NP,
    -	of_clk_src_onecell_get,
    +	of_clk_hw_onecell_get,
	    DATA
      )

    // Fix register/unregister
    @@
    identifier CD;
    expression E;
    identifier fn =~ "unregister";
    @@
      fn(...,
    -    CD->clks[E]
    +    CD->hws[E]->clk
	 ,...
	);

    // Fix calls to clk_prepare_enable()
    @@
    identifier CD;
    expression E;
    @@
      clk_prepare_enable(
    - 		     CD->clks[E]
    + 		     CD->hws[E]->clk
      );

    // Fix pointer assignment
    @@
    identifier CD;
    identifier CLK;
    expression E;
    @@
    - CD->clks[E]
    + CD->hws[E]
      =
    (
    - CLK
    + __clk_get_hw(CLK)
    |
      ERR_PTR(...)
    )
      ;

    // Fix pointer usage
    @@
    identifier CD;
    expression E;
    @@
    - CD->clks[E]
    + CD->hws[E]

    // Fix mtk_clk_pll_get_base()
    @@
    symbol clk, hw, data;
    @@
      mtk_clk_pll_get_base(
    - 		       struct clk *clk,
    + 		       struct clk_hw *hw,
			   const struct mtk_pll_data *data
      ) {
    - struct clk_hw *hw = __clk_get_hw(clk);
      ...
      }

    // Fix mtk_clk_pll_get_base() usage
    @@
    identifier CD;
    expression E;
    @@
      mtk_clk_pll_get_base(
    -    CD->clks[E]
    +    CD->hws[E]->clk
	 ,...
      );

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220519071610.423372-4-wenst@chromium.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Chen-Yu Tsai 2022-05-19 15:16:08 +08:00 committed by Stephen Boyd
parent 012715ad7c
commit 609cc5e1a8
94 changed files with 438 additions and 444 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
drivers/clk/mediatek/clk-cpumux.c
View file

@ -105,7 +105,7 @@ static void mtk_clk_unregister_cpumux(struct clk *clk)
int mtk_clk_register_cpumuxes(struct device_node *node,
const struct mtk_composite *clks, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
struct clk *clk;
@ -120,7 +120,7 @@ int mtk_clk_register_cpumuxes(struct device_node *node,
for (i = 0; i < num; i++) {
const struct mtk_composite *mux = &clks[i];
if (!IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, mux->id);
continue;
@ -132,7 +132,7 @@ int mtk_clk_register_cpumuxes(struct device_node *node,
goto err;
}
clk_data->clks[mux->id] = clk;
clk_data->hws[mux->id] = __clk_get_hw(clk);
}
return 0;
@ -141,29 +141,29 @@ int mtk_clk_register_cpumuxes(struct device_node *node,
while (--i >= 0) {
const struct mtk_composite *mux = &clks[i];
if (IS_ERR_OR_NULL(clk_data->clks[mux->id]))
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
continue;
mtk_clk_unregister_cpumux(clk_data->clks[mux->id]);
clk_data->clks[mux->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_cpumux(clk_data->hws[mux->id]->clk);
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(clk);
}
void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
for (i = num; i > 0; i--) {
const struct mtk_composite *mux = &clks[i - 1];
if (IS_ERR_OR_NULL(clk_data->clks[mux->id]))
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
continue;
mtk_clk_unregister_cpumux(clk_data->clks[mux->id]);
clk_data->clks[mux->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_cpumux(clk_data->hws[mux->id]->clk);
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
}
}

6
drivers/clk/mediatek/clk-cpumux.h
View file

@ -7,15 +7,15 @@
#ifndef __DRV_CLK_CPUMUX_H
#define __DRV_CLK_CPUMUX_H
struct clk_onecell_data;
struct clk_hw_onecell_data;
struct device_node;
struct mtk_composite;
int mtk_clk_register_cpumuxes(struct device_node *node,
const struct mtk_composite *clks, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
#endif /* __DRV_CLK_CPUMUX_H */

22
drivers/clk/mediatek/clk-gate.c
View file

@ -205,7 +205,7 @@ static void mtk_clk_unregister_gate(struct clk *clk)
int mtk_clk_register_gates_with_dev(struct device_node *node,
const struct mtk_gate *clks, int num,
struct clk_onecell_data *clk_data,
struct clk_hw_onecell_data *clk_data,
struct device *dev)
{
int i;
@ -224,7 +224,7 @@ int mtk_clk_register_gates_with_dev(struct device_node *node,
for (i = 0; i < num; i++) {
const struct mtk_gate *gate = &clks[i];
if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) {
if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, gate->id);
continue;
@ -243,7 +243,7 @@ int mtk_clk_register_gates_with_dev(struct device_node *node,
goto err;
}
clk_data->clks[gate->id] = clk;
clk_data->hws[gate->id] = __clk_get_hw(clk);
}
return 0;
@ -252,11 +252,11 @@ int mtk_clk_register_gates_with_dev(struct device_node *node,
while (--i >= 0) {
const struct mtk_gate *gate = &clks[i];
if (IS_ERR_OR_NULL(clk_data->clks[gate->id]))
if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
continue;
mtk_clk_unregister_gate(clk_data->clks[gate->id]);
clk_data->clks[gate->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_gate(clk_data->hws[gate->id]->clk);
clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(clk);
@ -264,14 +264,14 @@ int mtk_clk_register_gates_with_dev(struct device_node *node,
int mtk_clk_register_gates(struct device_node *node,
const struct mtk_gate *clks, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
}
EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
@ -281,11 +281,11 @@ void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
for (i = num; i > 0; i--) {
const struct mtk_gate *gate = &clks[i - 1];
if (IS_ERR_OR_NULL(clk_data->clks[gate->id]))
if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
continue;
mtk_clk_unregister_gate(clk_data->clks[gate->id]);
clk_data->clks[gate->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_gate(clk_data->hws[gate->id]->clk);
clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
}
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_gates);

8
drivers/clk/mediatek/clk-gate.h
View file

@ -10,7 +10,7 @@
#include <linux/types.h>
struct clk;
struct clk_onecell_data;
struct clk_hw_onecell_data;
struct clk_ops;
struct device;
struct device_node;
@ -52,14 +52,14 @@ struct mtk_gate {
int mtk_clk_register_gates(struct device_node *node,
const struct mtk_gate *clks, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
int mtk_clk_register_gates_with_dev(struct device_node *node,
const struct mtk_gate *clks, int num,
struct clk_onecell_data *clk_data,
struct clk_hw_onecell_data *clk_data,
struct device *dev);
void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
#endif /* __DRV_CLK_GATE_H */

4
drivers/clk/mediatek/clk-mt2701-aud.c
View file

@ -145,7 +145,7 @@ static const struct of_device_id of_match_clk_mt2701_aud[] = {
static int clk_mt2701_aud_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -154,7 +154,7 @@ static int clk_mt2701_aud_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt2701-bdp.c
View file

@ -101,7 +101,7 @@ static const struct of_device_id of_match_clk_mt2701_bdp[] = {
static int clk_mt2701_bdp_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -110,7 +110,7 @@ static int clk_mt2701_bdp_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt2701-eth.c
View file

@ -43,7 +43,7 @@ static const struct of_device_id of_match_clk_mt2701_eth[] = {
static int clk_mt2701_eth_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -52,7 +52,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt2701-g3d.c
View file

@ -37,7 +37,7 @@ static const struct mtk_gate g3d_clks[] = {
static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -46,7 +46,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt2701-hif.c
View file

@ -40,7 +40,7 @@ static const struct of_device_id of_match_clk_mt2701_hif[] = {
static int clk_mt2701_hif_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -49,7 +49,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt2701-img.c
View file

@ -43,7 +43,7 @@ static const struct of_device_id of_match_clk_mt2701_img[] = {
static int clk_mt2701_img_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -52,7 +52,7 @@ static int clk_mt2701_img_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt2701-mm.c
View file

@ -83,7 +83,7 @@ static int clk_mt2701_mm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_MM_NR);
@ -91,7 +91,7 @@ static int clk_mt2701_mm_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt2701-vdec.c
View file

@ -54,7 +54,7 @@ static const struct of_device_id of_match_clk_mt2701_vdec[] = {
static int clk_mt2701_vdec_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -63,7 +63,7 @@ static int clk_mt2701_vdec_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

26
drivers/clk/mediatek/clk-mt2701.c
View file

@ -666,7 +666,7 @@ static const struct mtk_gate top_clks[] = {
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@ -692,7 +692,7 @@ static int mtk_topckgen_init(struct platform_device *pdev)
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct mtk_gate_regs infra_cg_regs = {
@ -735,7 +735,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
};
static struct clk_onecell_data *infra_clk_data;
static struct clk_hw_onecell_data *infra_clk_data;
static void __init mtk_infrasys_init_early(struct device_node *node)
{
@ -745,7 +745,7 @@ static void __init mtk_infrasys_init_early(struct device_node *node)
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
}
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
@ -754,7 +754,8 @@ static void __init mtk_infrasys_init_early(struct device_node *node)
mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
infra_clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -771,8 +772,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
} else {
for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
}
}
@ -781,7 +782,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
if (r)
return r;
@ -886,7 +888,7 @@ static const struct mtk_composite peri_muxs[] = {
static int mtk_pericfg_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
struct device_node *node = pdev->dev.of_node;
@ -904,7 +906,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
&mt2701_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
return r;
@ -969,7 +971,7 @@ static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
@ -981,7 +983,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt2701[] = {

4
drivers/clk/mediatek/clk-mt2712-bdp.c
View file

@ -60,7 +60,7 @@ static const struct mtk_gate bdp_clks[] = {
static int clk_mt2712_bdp_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -69,7 +69,7 @@ static int clk_mt2712_bdp_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt2712-img.c
View file

@ -38,7 +38,7 @@ static const struct mtk_gate img_clks[] = {
static int clk_mt2712_img_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -47,7 +47,7 @@ static int clk_mt2712_img_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt2712-jpgdec.c
View file

@ -34,7 +34,7 @@ static const struct mtk_gate jpgdec_clks[] = {
static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -43,7 +43,7 @@ static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt2712-mfg.c
View file

@ -33,7 +33,7 @@ static const struct mtk_gate mfg_clks[] = {
static int clk_mt2712_mfg_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -42,7 +42,7 @@ static int clk_mt2712_mfg_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt2712-mm.c
View file

@ -130,7 +130,7 @@ static int clk_mt2712_mm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
@ -138,7 +138,7 @@ static int clk_mt2712_mm_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt2712-vdec.c
View file

@ -52,7 +52,7 @@ static const struct mtk_gate vdec_clks[] = {
static int clk_mt2712_vdec_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -61,7 +61,7 @@ static int clk_mt2712_vdec_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt2712-venc.c
View file

@ -35,7 +35,7 @@ static const struct mtk_gate venc_clks[] = {
static int clk_mt2712_venc_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -44,7 +44,7 @@ static int clk_mt2712_venc_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",

28
drivers/clk/mediatek/clk-mt2712.c
View file

@ -1260,7 +1260,7 @@ static const struct mtk_pll_data plls[] = {
static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -1268,7 +1268,7 @@ static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",
@ -1277,7 +1277,7 @@ static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
return r;
}
static struct clk_onecell_data *top_clk_data;
static struct clk_hw_onecell_data *top_clk_data;
static void clk_mt2712_top_init_early(struct device_node *node)
{
@ -1287,13 +1287,13 @@ static void clk_mt2712_top_init_early(struct device_node *node)
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
for (i = 0; i < CLK_TOP_NR_CLK; i++)
top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
}
mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
top_clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -1318,8 +1318,8 @@ static int clk_mt2712_top_probe(struct platform_device *pdev)
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
} else {
for (i = 0; i < CLK_TOP_NR_CLK; i++) {
if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
top_clk_data->clks[i] = ERR_PTR(-ENOENT);
if (top_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
top_clk_data->hws[i] = ERR_PTR(-ENOENT);
}
}
@ -1335,7 +1335,7 @@ static int clk_mt2712_top_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
top_clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",
@ -1346,7 +1346,7 @@ static int clk_mt2712_top_probe(struct platform_device *pdev)
static int clk_mt2712_infra_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -1355,7 +1355,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",
@ -1368,7 +1368,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
static int clk_mt2712_peri_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -1377,7 +1377,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",
@ -1390,7 +1390,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
static int clk_mt2712_mcu_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
@ -1406,7 +1406,7 @@ static int clk_mt2712_mcu_probe(struct platform_device *pdev)
mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
&mt2712_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r != 0)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt6765-audio.c
View file

@ -66,7 +66,7 @@ static const struct mtk_gate audio_clks[] = {
static int clk_mt6765_audio_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -75,7 +75,7 @@ static int clk_mt6765_audio_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, audio_clks,
ARRAY_SIZE(audio_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt6765-cam.c
View file

@ -41,7 +41,7 @@ static const struct mtk_gate cam_clks[] = {
static int clk_mt6765_cam_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -49,7 +49,7 @@ static int clk_mt6765_cam_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt6765-img.c
View file

@ -37,7 +37,7 @@ static const struct mtk_gate img_clks[] = {
static int clk_mt6765_img_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -45,7 +45,7 @@ static int clk_mt6765_img_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt6765-mipi0a.c
View file

@ -34,7 +34,7 @@ static const struct mtk_gate mipi0a_clks[] = {
static int clk_mt6765_mipi0a_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -43,7 +43,7 @@ static int clk_mt6765_mipi0a_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, mipi0a_clks,
ARRAY_SIZE(mipi0a_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt6765-mm.c
View file

@ -63,7 +63,7 @@ static const struct mtk_gate mm_clks[] = {
static int clk_mt6765_mm_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -71,7 +71,7 @@ static int clk_mt6765_mm_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt6765-vcodec.c
View file

@ -36,7 +36,7 @@ static const struct mtk_gate venc_clks[] = {
static int clk_mt6765_vcodec_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -45,7 +45,7 @@ static int clk_mt6765_vcodec_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, venc_clks,
ARRAY_SIZE(venc_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

12
drivers/clk/mediatek/clk-mt6765.c
View file

@ -773,7 +773,7 @@ static const struct mtk_pll_data plls[] = {
static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
@ -791,7 +791,7 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
@ -811,7 +811,7 @@ static int clk_mt6765_top_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
@ -831,7 +831,7 @@ static int clk_mt6765_top_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
@ -848,7 +848,7 @@ static int clk_mt6765_top_probe(struct platform_device *pdev)
static int clk_mt6765_ifr_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
@ -864,7 +864,7 @@ static int clk_mt6765_ifr_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt6779-aud.c
View file

@ -96,7 +96,7 @@ static const struct of_device_id of_match_clk_mt6779_aud[] = {
static int clk_mt6779_aud_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
@ -104,7 +104,7 @@ static int clk_mt6779_aud_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt6779_aud_drv = {

4
drivers/clk/mediatek/clk-mt6779-cam.c
View file

@ -45,7 +45,7 @@ static const struct of_device_id of_match_clk_mt6779_cam[] = {
static int clk_mt6779_cam_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
@ -53,7 +53,7 @@ static int clk_mt6779_cam_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt6779_cam_drv = {

4
drivers/clk/mediatek/clk-mt6779-img.c
View file

@ -37,7 +37,7 @@ static const struct of_device_id of_match_clk_mt6779_img[] = {
static int clk_mt6779_img_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
@ -45,7 +45,7 @@ static int clk_mt6779_img_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt6779_img_drv = {

4
drivers/clk/mediatek/clk-mt6779-ipe.c
View file

@ -39,7 +39,7 @@ static const struct of_device_id of_match_clk_mt6779_ipe[] = {
static int clk_mt6779_ipe_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
@ -47,7 +47,7 @@ static int clk_mt6779_ipe_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt6779_ipe_drv = {

4
drivers/clk/mediatek/clk-mt6779-mfg.c
View file

@ -29,7 +29,7 @@ static const struct mtk_gate mfg_clks[] = {
static int clk_mt6779_mfg_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
@ -37,7 +37,7 @@ static int clk_mt6779_mfg_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt6779_mfg[] = {

4
drivers/clk/mediatek/clk-mt6779-mm.c
View file

@ -89,14 +89,14 @@ static int clk_mt6779_mm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt6779_mm_drv = {

4
drivers/clk/mediatek/clk-mt6779-vdec.c
View file

@ -46,7 +46,7 @@ static const struct of_device_id of_match_clk_mt6779_vdec[] = {
static int clk_mt6779_vdec_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_VDEC_GCON_NR_CLK);
@ -54,7 +54,7 @@ static int clk_mt6779_vdec_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt6779_vdec_drv = {

4
drivers/clk/mediatek/clk-mt6779-venc.c
View file

@ -37,7 +37,7 @@ static const struct of_device_id of_match_clk_mt6779_venc[] = {
static int clk_mt6779_venc_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_VENC_GCON_NR_CLK);
@ -45,7 +45,7 @@ static int clk_mt6779_venc_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt6779_venc_drv = {

12
drivers/clk/mediatek/clk-mt6779.c
View file

@ -1214,7 +1214,7 @@ static const struct mtk_pll_data plls[] = {
static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
@ -1224,13 +1224,13 @@ static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int clk_mt6779_top_probe(struct platform_device *pdev)
{
void __iomem *base;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
base = devm_platform_ioremap_resource(pdev, 0);
@ -1253,12 +1253,12 @@ static int clk_mt6779_top_probe(struct platform_device *pdev)
mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
base, &mt6779_clk_lock, clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int clk_mt6779_infra_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
@ -1266,7 +1266,7 @@ static int clk_mt6779_infra_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt6779[] = {

4
drivers/clk/mediatek/clk-mt6797-img.c
View file

@ -39,7 +39,7 @@ static const struct of_device_id of_match_clk_mt6797_img[] = {
static int clk_mt6797_img_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -48,7 +48,7 @@ static int clk_mt6797_img_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt6797-mm.c
View file

@ -96,7 +96,7 @@ static int clk_mt6797_mm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_MM_NR);
@ -104,7 +104,7 @@ static int clk_mt6797_mm_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt6797-vdec.c
View file

@ -56,7 +56,7 @@ static const struct of_device_id of_match_clk_mt6797_vdec[] = {
static int clk_mt6797_vdec_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -65,7 +65,7 @@ static int clk_mt6797_vdec_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

4
drivers/clk/mediatek/clk-mt6797-venc.c
View file

@ -41,7 +41,7 @@ static const struct of_device_id of_match_clk_mt6797_venc[] = {
static int clk_mt6797_venc_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -50,7 +50,7 @@ static int clk_mt6797_venc_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

22
drivers/clk/mediatek/clk-mt6797.c
View file

@ -383,7 +383,7 @@ static const struct mtk_composite top_muxes[] = {
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
@ -399,7 +399,7 @@ static int mtk_topckgen_init(struct platform_device *pdev)
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
&mt6797_clk_lock, clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct mtk_gate_regs infra0_cg_regs = {
@ -556,7 +556,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
};
static struct clk_onecell_data *infra_clk_data;
static struct clk_hw_onecell_data *infra_clk_data;
static void mtk_infrasys_init_early(struct device_node *node)
{
@ -566,13 +566,14 @@ static void mtk_infrasys_init_early(struct device_node *node)
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
}
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -590,8 +591,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
} else {
for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
}
}
@ -600,7 +601,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
infra_clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
infra_clk_data);
}
#define MT6797_PLL_FMAX (3000UL * MHZ)
@ -659,7 +661,7 @@ static const struct mtk_pll_data plls[] = {
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
@ -668,7 +670,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt6797[] = {

4
drivers/clk/mediatek/clk-mt7622-aud.c
View file

@ -132,7 +132,7 @@ static const struct mtk_gate audio_clks[] = {
static int clk_mt7622_audiosys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -141,7 +141,7 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

8
drivers/clk/mediatek/clk-mt7622-eth.c
View file

@ -67,7 +67,7 @@ static const struct mtk_gate sgmii_clks[] = {
static int clk_mt7622_ethsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -76,7 +76,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
@ -89,7 +89,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -98,7 +98,7 @@ static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

8
drivers/clk/mediatek/clk-mt7622-hif.c
View file

@ -78,7 +78,7 @@ static const struct mtk_gate pcie_clks[] = {
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -87,7 +87,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
@ -100,7 +100,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
static int clk_mt7622_pciesys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -109,7 +109,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

30
drivers/clk/mediatek/clk-mt7622.c
View file

@ -612,7 +612,7 @@ static struct mtk_composite peri_muxes[] = {
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
@ -637,17 +637,17 @@ static int mtk_topckgen_init(struct platform_device *pdev)
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
clk_data);
clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int mtk_infrasys_init(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
@ -658,8 +658,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get,
clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
clk_data);
if (r)
return r;
@ -670,7 +670,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
@ -683,15 +683,15 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int mtk_pericfg_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
struct device_node *node = pdev->dev.of_node;
@ -708,11 +708,11 @@ static int mtk_pericfg_init(struct platform_device *pdev)
mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
&mt7622_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
return r;
clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
mtk_register_reset_controller(node, 2, 0x0);

8
drivers/clk/mediatek/clk-mt7629-eth.c
View file

@ -78,7 +78,7 @@ static const struct mtk_gate sgmii_clks[2][4] = {
static int clk_mt7629_ethsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -86,7 +86,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
@ -99,7 +99,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
static int id;
int r;
@ -109,7 +109,7 @@ static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

8
drivers/clk/mediatek/clk-mt7629-hif.c
View file

@ -73,7 +73,7 @@ static const struct mtk_gate pcie_clks[] = {
static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -82,7 +82,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",
@ -95,7 +95,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
static int clk_mt7629_pciesys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -104,7 +104,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n",

30
drivers/clk/mediatek/clk-mt7629.c
View file

@ -572,7 +572,7 @@ static struct mtk_composite peri_muxes[] = {
static int mtk_topckgen_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct device_node *node = pdev->dev.of_node;
@ -591,17 +591,17 @@ static int mtk_topckgen_init(struct platform_device *pdev)
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
base, &mt7629_clk_lock, clk_data);
clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int mtk_infrasys_init(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
@ -611,13 +611,13 @@ static int mtk_infrasys_init(struct platform_device *pdev)
mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get,
clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
clk_data);
}
static int mtk_pericfg_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
struct device_node *node = pdev->dev.of_node;
@ -634,18 +634,18 @@ static int mtk_pericfg_init(struct platform_device *pdev)
mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
&mt7629_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
return r;
clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
return 0;
}
static int mtk_apmixedsys_init(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
@ -658,10 +658,10 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
mtk_clk_register_gates(node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}

6
drivers/clk/mediatek/clk-mt7986-apmixed.c
View file

@ -67,7 +67,7 @@ static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -77,9 +77,9 @@ static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

12
drivers/clk/mediatek/clk-mt7986-eth.c
View file

@ -79,7 +79,7 @@ static const struct mtk_gate eth_clks[] __initconst = {
static void __init mtk_sgmiisys_0_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
@ -87,7 +87,7 @@ static void __init mtk_sgmiisys_0_init(struct device_node *node)
mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -97,7 +97,7 @@ CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
static void __init mtk_sgmiisys_1_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
@ -105,7 +105,7 @@ static void __init mtk_sgmiisys_1_init(struct device_node *node)
mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
@ -116,14 +116,14 @@ CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
static void __init mtk_ethsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt7986-infracfg.c
View file

@ -171,7 +171,7 @@ static const struct mtk_gate infra_clks[] = {
static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
void __iomem *base;
@ -195,7 +195,7 @@ static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

16
drivers/clk/mediatek/clk-mt7986-topckgen.c
View file

@ -283,7 +283,7 @@ static const struct mtk_mux top_muxes[] = {
static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
void __iomem *base;
@ -306,14 +306,14 @@ static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
&mt7986_clk_lock, clk_data);
clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
pr_err("%s(): could not register clock provider: %d\n",

18
drivers/clk/mediatek/clk-mt8135.c
View file

@ -516,7 +516,7 @@ static const struct mtk_composite peri_clks[] __initconst = {
static void __init mtk_topckgen_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
@ -533,9 +533,9 @@ static void __init mtk_topckgen_init(struct device_node *node)
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
&mt8135_clk_lock, clk_data);
clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -544,7 +544,7 @@ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
static void __init mtk_infrasys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
@ -552,9 +552,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -565,7 +565,7 @@ CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
static void __init mtk_pericfg_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
void __iomem *base;
@ -582,7 +582,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
&mt8135_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -626,7 +626,7 @@ static const struct mtk_pll_data plls[] = {
static void __init mtk_apmixedsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)

4
drivers/clk/mediatek/clk-mt8167-aud.c
View file

@ -50,14 +50,14 @@ static const struct mtk_gate aud_clks[] __initconst = {
static void __init mtk_audsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

4
drivers/clk/mediatek/clk-mt8167-img.c
View file

@ -43,14 +43,14 @@ static const struct mtk_gate img_clks[] __initconst = {
static void __init mtk_imgsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt8167-mfgcfg.c
View file

@ -41,14 +41,14 @@ static const struct mtk_gate mfg_clks[] __initconst = {
static void __init mtk_mfgcfg_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

4
drivers/clk/mediatek/clk-mt8167-mm.c
View file

@ -101,7 +101,7 @@ static int clk_mt8167_mm_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
const struct clk_mt8167_mm_driver_data *data;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int ret;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
@ -115,7 +115,7 @@ static int clk_mt8167_mm_probe(struct platform_device *pdev)
if (ret)
return ret;
ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
return ret;

4
drivers/clk/mediatek/clk-mt8167-vdec.c
View file

@ -56,14 +56,14 @@ static const struct mtk_gate vdec_clks[] __initconst = {
static void __init mtk_vdecsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",

12
drivers/clk/mediatek/clk-mt8167.c
View file

@ -923,7 +923,7 @@ static const struct mtk_gate top_clks[] __initconst = {
static void __init mtk_topckgen_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
void __iomem *base;
@ -945,7 +945,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt8167_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -954,7 +954,7 @@ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init);
static void __init mtk_infracfg_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
void __iomem *base;
@ -969,7 +969,7 @@ static void __init mtk_infracfg_init(struct device_node *node)
mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
&mt8167_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -1037,7 +1037,7 @@ static const struct mtk_pll_data plls[] = {
static void __init mtk_apmixedsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
@ -1053,7 +1053,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs),
base, &mt8167_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

4
drivers/clk/mediatek/clk-mt8173-mm.c
View file

@ -115,7 +115,7 @@ static int clk_mt8173_mm_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
const struct clk_mt8173_mm_driver_data *data;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int ret;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
@ -129,7 +129,7 @@ static int clk_mt8173_mm_probe(struct platform_device *pdev)
if (ret)
return ret;
ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (ret)
return ret;

52
drivers/clk/mediatek/clk-mt8173.c
View file

@ -819,25 +819,25 @@ static const struct mtk_gate venclt_clks[] __initconst = {
GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
};
static struct clk_onecell_data *mt8173_top_clk_data __initdata;
static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata;
static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata;
static void __init mtk_clk_enable_critical(void)
{
if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
return;
clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA15PLL]->clk);
clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA7PLL]->clk);
clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_MEM_SEL]->clk);
clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_CCI400_SEL]->clk);
clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk);
}
static void __init mtk_topckgen_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
@ -854,7 +854,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
&mt8173_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -865,7 +865,7 @@ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
static void __init mtk_infrasys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
@ -877,7 +877,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -888,7 +888,7 @@ CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
static void __init mtk_pericfg_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
void __iomem *base;
@ -905,7 +905,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
&mt8173_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -991,7 +991,7 @@ static const struct mtk_pll_data plls[] = {
static void __init mtk_apmixedsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
struct clk *clk;
int r, i;
@ -1022,15 +1022,15 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
continue;
}
clk_data->clks[cku->id] = clk;
clk_data->hws[cku->id] = __clk_get_hw(clk);
}
clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
NULL);
clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
clk_data->hws[CLK_APMIXED_HDMI_REF] = __clk_get_hw(clk);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -1042,7 +1042,7 @@ CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
static void __init mtk_imgsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
@ -1050,7 +1050,7 @@ static void __init mtk_imgsys_init(struct device_node *node)
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
@ -1060,7 +1060,7 @@ CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
static void __init mtk_vdecsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
@ -1068,7 +1068,7 @@ static void __init mtk_vdecsys_init(struct device_node *node)
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -1077,7 +1077,7 @@ CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
static void __init mtk_vencsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
@ -1085,7 +1085,7 @@ static void __init mtk_vencsys_init(struct device_node *node)
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -1094,7 +1094,7 @@ CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
static void __init mtk_vencltsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
@ -1102,7 +1102,7 @@ static void __init mtk_vencltsys_init(struct device_node *node)
mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

4
drivers/clk/mediatek/clk-mt8183-audio.c
View file

@ -69,7 +69,7 @@ static const struct mtk_gate audio_clks[] = {
static int clk_mt8183_audio_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
struct device_node *node = pdev->dev.of_node;
@ -78,7 +78,7 @@ static int clk_mt8183_audio_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
return r;

4
drivers/clk/mediatek/clk-mt8183-cam.c
View file

@ -36,7 +36,7 @@ static const struct mtk_gate cam_clks[] = {
static int clk_mt8183_cam_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
@ -44,7 +44,7 @@ static int clk_mt8183_cam_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_cam[] = {

4
drivers/clk/mediatek/clk-mt8183-img.c
View file

@ -36,7 +36,7 @@ static const struct mtk_gate img_clks[] = {
static int clk_mt8183_img_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
@ -44,7 +44,7 @@ static int clk_mt8183_img_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_img[] = {

4
drivers/clk/mediatek/clk-mt8183-ipu0.c
View file

@ -29,7 +29,7 @@ static const struct mtk_gate ipu_core0_clks[] = {
static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
@ -37,7 +37,7 @@ static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {

4
drivers/clk/mediatek/clk-mt8183-ipu1.c
View file

@ -29,7 +29,7 @@ static const struct mtk_gate ipu_core1_clks[] = {
static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_IPU_CORE1_NR_CLK);
@ -37,7 +37,7 @@ static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, ipu_core1_clks, ARRAY_SIZE(ipu_core1_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = {

4
drivers/clk/mediatek/clk-mt8183-ipu_adl.c
View file

@ -27,7 +27,7 @@ static const struct mtk_gate ipu_adl_clks[] = {
static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
@ -35,7 +35,7 @@ static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {

4
drivers/clk/mediatek/clk-mt8183-ipu_conn.c
View file

@ -96,7 +96,7 @@ static const struct mtk_gate ipu_conn_clks[] = {
static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
@ -104,7 +104,7 @@ static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {

4
drivers/clk/mediatek/clk-mt8183-mfgcfg.c
View file

@ -28,7 +28,7 @@ static const struct mtk_gate mfg_clks[] = {
static int clk_mt8183_mfg_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
pm_runtime_enable(&pdev->dev);
@ -38,7 +38,7 @@ static int clk_mt8183_mfg_probe(struct platform_device *pdev)
mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks),
clk_data, &pdev->dev);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_mfg[] = {

4
drivers/clk/mediatek/clk-mt8183-mm.c
View file

@ -86,14 +86,14 @@ static int clk_mt8183_mm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt8183_mm_drv = {

4
drivers/clk/mediatek/clk-mt8183-vdec.c
View file

@ -40,7 +40,7 @@ static const struct mtk_gate vdec_clks[] = {
static int clk_mt8183_vdec_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
@ -48,7 +48,7 @@ static int clk_mt8183_vdec_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_vdec[] = {

4
drivers/clk/mediatek/clk-mt8183-venc.c
View file

@ -32,7 +32,7 @@ static const struct mtk_gate venc_clks[] = {
static int clk_mt8183_venc_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
@ -40,7 +40,7 @@ static int clk_mt8183_venc_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183_venc[] = {

25
drivers/clk/mediatek/clk-mt8183.c
View file

@ -1155,7 +1155,7 @@ static const struct mtk_pll_data plls[] = {
static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
@ -1165,10 +1165,10 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct clk_onecell_data *top_clk_data;
static struct clk_hw_onecell_data *top_clk_data;
static void clk_mt8183_top_init_early(struct device_node *node)
{
@ -1177,12 +1177,12 @@ static void clk_mt8183_top_init_early(struct device_node *node)
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
for (i = 0; i < CLK_TOP_NR_CLK; i++)
top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
top_clk_data);
of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
}
CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
@ -1217,12 +1217,13 @@ static int clk_mt8183_top_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
top_clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
top_clk_data);
}
static int clk_mt8183_infra_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -1231,7 +1232,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {
dev_err(&pdev->dev,
"%s(): could not register clock provider: %d\n",
@ -1246,7 +1247,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
static int clk_mt8183_peri_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
@ -1254,12 +1255,12 @@ static int clk_mt8183_peri_probe(struct platform_device *pdev)
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static int clk_mt8183_mcu_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
void __iomem *base;
@ -1272,7 +1273,7 @@ static int clk_mt8183_mcu_probe(struct platform_device *pdev)
mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
&mt8183_clk_lock, clk_data);
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static const struct of_device_id of_match_clk_mt8183[] = {

6
drivers/clk/mediatek/clk-mt8186-apmixedsys.c
View file

@ -83,7 +83,7 @@ static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -95,7 +95,7 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
if (r)
goto free_apmixed_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
@ -113,7 +113,7 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
static int clk_mt8186_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);

6
drivers/clk/mediatek/clk-mt8186-mcu.c
View file

@ -50,7 +50,7 @@ static const struct of_device_id of_match_clk_mt8186_mcu[] = {
static int clk_mt8186_mcu_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
void __iomem *base;
@ -70,7 +70,7 @@ static int clk_mt8186_mcu_probe(struct platform_device *pdev)
if (r)
goto free_mcu_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_composite_muxes;
@ -87,7 +87,7 @@ static int clk_mt8186_mcu_probe(struct platform_device *pdev)
static int clk_mt8186_mcu_remove(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);

6
drivers/clk/mediatek/clk-mt8186-mm.c
View file

@ -62,7 +62,7 @@ static int clk_mt8186_mm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
@ -73,7 +73,7 @@ static int clk_mt8186_mm_probe(struct platform_device *pdev)
if (r)
goto free_mm_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_gates;
@ -92,7 +92,7 @@ static int clk_mt8186_mm_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data);

6
drivers/clk/mediatek/clk-mt8186-topckgen.c
View file

@ -691,7 +691,7 @@ static const struct of_device_id of_match_clk_mt8186_topck[] = {
static int clk_mt8186_topck_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
void __iomem *base;
@ -730,7 +730,7 @@ static int clk_mt8186_topck_probe(struct platform_device *pdev)
if (r)
goto unregister_composite_muxes;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_composite_divs;
@ -755,7 +755,7 @@ static int clk_mt8186_topck_probe(struct platform_device *pdev)
static int clk_mt8186_topck_remove(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);

4
drivers/clk/mediatek/clk-mt8192-aud.c
View file

@ -79,7 +79,7 @@ static const struct mtk_gate aud_clks[] = {
static int clk_mt8192_aud_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -91,7 +91,7 @@ static int clk_mt8192_aud_probe(struct platform_device *pdev)
if (r)
return r;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
return r;

4
drivers/clk/mediatek/clk-mt8192-mm.c
View file

@ -84,7 +84,7 @@ static int clk_mt8192_mm_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
@ -95,7 +95,7 @@ static int clk_mt8192_mm_probe(struct platform_device *pdev)
if (r)
return r;
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}
static struct platform_driver clk_mt8192_mm_drv = {

21
drivers/clk/mediatek/clk-mt8192.c
View file

@ -1178,7 +1178,7 @@ static const struct mtk_pll_data plls[] = {
0, 0, 32, 0x0330, 24, 0, 0, 0, 0x0334, 0),
};
static struct clk_onecell_data *top_clk_data;
static struct clk_hw_onecell_data *top_clk_data;
static void clk_mt8192_top_init_early(struct device_node *node)
{
@ -1189,11 +1189,11 @@ static void clk_mt8192_top_init_early(struct device_node *node)
return;
for (i = 0; i < CLK_TOP_NR_CLK; i++)
top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
}
CLK_OF_DECLARE_DRIVER(mt8192_topckgen, "mediatek,mt8192-topckgen",
@ -1222,12 +1222,13 @@ static int clk_mt8192_top_probe(struct platform_device *pdev)
if (r)
return r;
return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
top_clk_data);
}
static int clk_mt8192_infra_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -1239,7 +1240,7 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
if (r)
goto free_clk_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto free_clk_data;
@ -1252,7 +1253,7 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
static int clk_mt8192_peri_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -1264,7 +1265,7 @@ static int clk_mt8192_peri_probe(struct platform_device *pdev)
if (r)
goto free_clk_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto free_clk_data;
@ -1277,7 +1278,7 @@ static int clk_mt8192_peri_probe(struct platform_device *pdev)
static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -1290,7 +1291,7 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
if (r)
goto free_clk_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto free_clk_data;

6
drivers/clk/mediatek/clk-mt8195-apmixedsys.c
View file

@ -112,7 +112,7 @@ static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -128,7 +128,7 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
if (r)
goto unregister_plls;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_gates;
@ -148,7 +148,7 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
static int clk_mt8195_apmixed_remove(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);

6
drivers/clk/mediatek/clk-mt8195-apusys_pll.c
View file

@ -58,7 +58,7 @@ static const struct mtk_pll_data apusys_plls[] = {
static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -70,7 +70,7 @@ static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
if (r)
goto free_apusys_pll_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_plls;
@ -87,7 +87,7 @@ static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
static int clk_mt8195_apusys_pll_remove(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);

6
drivers/clk/mediatek/clk-mt8195-topckgen.c
View file

@ -1224,7 +1224,7 @@ static const struct of_device_id of_match_clk_mt8195_topck[] = {
static int clk_mt8195_topck_probe(struct platform_device *pdev)
{
struct clk_onecell_data *top_clk_data;
struct clk_hw_onecell_data *top_clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
void __iomem *base;
@ -1267,7 +1267,7 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev)
if (r)
goto unregister_composite_divs;
r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
if (r)
goto unregister_gates;
@ -1294,7 +1294,7 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev)
static int clk_mt8195_topck_remove(struct platform_device *pdev)
{
struct clk_onecell_data *top_clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *top_clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);

6
drivers/clk/mediatek/clk-mt8195-vdo0.c
View file

@ -92,7 +92,7 @@ static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VDO0_NR_CLK);
@ -103,7 +103,7 @@ static int clk_mt8195_vdo0_probe(struct platform_device *pdev)
if (r)
goto free_vdo0_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_gates;
@ -122,7 +122,7 @@ static int clk_mt8195_vdo0_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_gates(vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data);

6
drivers/clk/mediatek/clk-mt8195-vdo1.c
View file

@ -109,7 +109,7 @@ static int clk_mt8195_vdo1_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_VDO1_NR_CLK);
@ -120,7 +120,7 @@ static int clk_mt8195_vdo1_probe(struct platform_device *pdev)
if (r)
goto free_vdo1_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_gates;
@ -139,7 +139,7 @@ static int clk_mt8195_vdo1_remove(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct device_node *node = dev->parent->of_node;
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
of_clk_del_provider(node);
mtk_clk_unregister_gates(vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data);

4
drivers/clk/mediatek/clk-mt8516-aud.c
View file

@ -49,14 +49,14 @@ static const struct mtk_gate aud_clks[] __initconst = {
static void __init mtk_audsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

12
drivers/clk/mediatek/clk-mt8516.c
View file

@ -677,7 +677,7 @@ static const struct mtk_gate top_clks[] __initconst = {
static void __init mtk_topckgen_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
void __iomem *base;
@ -699,7 +699,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
base, &mt8516_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -708,7 +708,7 @@ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init);
static void __init mtk_infracfg_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
int r;
void __iomem *base;
@ -723,7 +723,7 @@ static void __init mtk_infracfg_init(struct device_node *node)
mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
&mt8516_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);
@ -787,7 +787,7 @@ static const struct mtk_pll_data plls[] = {
static void __init mtk_apmixedsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
void __iomem *base;
int r;
@ -801,7 +801,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
pr_err("%s(): could not register clock provider: %d\n",
__func__, r);

111
drivers/clk/mediatek/clk-mtk.c
View file

@ -18,43 +18,32 @@
#include "clk-mtk.h"
#include "clk-gate.h"
struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
struct clk_hw_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
{
int i;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
clk_data = kzalloc(struct_size(clk_data, hws, clk_num), GFP_KERNEL);
if (!clk_data)
return NULL;
clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
if (!clk_data->clks)
goto err_out;
clk_data->clk_num = clk_num;
clk_data->num = clk_num;
for (i = 0; i < clk_num; i++)
clk_data->clks[i] = ERR_PTR(-ENOENT);
clk_data->hws[i] = ERR_PTR(-ENOENT);
return clk_data;
err_out:
kfree(clk_data);
return NULL;
}
EXPORT_SYMBOL_GPL(mtk_alloc_clk_data);
void mtk_free_clk_data(struct clk_onecell_data *clk_data)
void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data)
{
if (!clk_data)
return;
kfree(clk_data->clks);
kfree(clk_data);
}
EXPORT_SYMBOL_GPL(mtk_free_clk_data);
int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
struct clk *clk;
@ -65,7 +54,7 @@ int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
for (i = 0; i < num; i++) {
const struct mtk_fixed_clk *rc = &clks[i];
if (!IS_ERR_OR_NULL(clk_data->clks[rc->id])) {
if (!IS_ERR_OR_NULL(clk_data->hws[rc->id])) {
pr_warn("Trying to register duplicate clock ID: %d\n", rc->id);
continue;
}
@ -78,7 +67,7 @@ int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
goto err;
}
clk_data->clks[rc->id] = clk;
clk_data->hws[rc->id] = __clk_get_hw(clk);
}
return 0;
@ -87,11 +76,11 @@ int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
while (--i >= 0) {
const struct mtk_fixed_clk *rc = &clks[i];
if (IS_ERR_OR_NULL(clk_data->clks[rc->id]))
if (IS_ERR_OR_NULL(clk_data->hws[rc->id]))
continue;
clk_unregister_fixed_rate(clk_data->clks[rc->id]);
clk_data->clks[rc->id] = ERR_PTR(-ENOENT);
clk_unregister_fixed_rate(clk_data->hws[rc->id]->clk);
clk_data->hws[rc->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(clk);
@ -99,7 +88,7 @@ int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
EXPORT_SYMBOL_GPL(mtk_clk_register_fixed_clks);
void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
@ -109,17 +98,17 @@ void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num,
for (i = num; i > 0; i--) {
const struct mtk_fixed_clk *rc = &clks[i - 1];
if (IS_ERR_OR_NULL(clk_data->clks[rc->id]))
if (IS_ERR_OR_NULL(clk_data->hws[rc->id]))
continue;
clk_unregister_fixed_rate(clk_data->clks[rc->id]);
clk_data->clks[rc->id] = ERR_PTR(-ENOENT);
clk_unregister_fixed_rate(clk_data->hws[rc->id]->clk);
clk_data->hws[rc->id] = ERR_PTR(-ENOENT);
}
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_fixed_clks);
int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
struct clk *clk;
@ -130,7 +119,7 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
for (i = 0; i < num; i++) {
const struct mtk_fixed_factor *ff = &clks[i];
if (!IS_ERR_OR_NULL(clk_data->clks[ff->id])) {
if (!IS_ERR_OR_NULL(clk_data->hws[ff->id])) {
pr_warn("Trying to register duplicate clock ID: %d\n", ff->id);
continue;
}
@ -143,7 +132,7 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
goto err;
}
clk_data->clks[ff->id] = clk;
clk_data->hws[ff->id] = __clk_get_hw(clk);
}
return 0;
@ -152,11 +141,11 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
while (--i >= 0) {
const struct mtk_fixed_factor *ff = &clks[i];
if (IS_ERR_OR_NULL(clk_data->clks[ff->id]))
if (IS_ERR_OR_NULL(clk_data->hws[ff->id]))
continue;
clk_unregister_fixed_factor(clk_data->clks[ff->id]);
clk_data->clks[ff->id] = ERR_PTR(-ENOENT);
clk_unregister_fixed_factor(clk_data->hws[ff->id]->clk);
clk_data->hws[ff->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(clk);
@ -164,7 +153,7 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
EXPORT_SYMBOL_GPL(mtk_clk_register_factors);
void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
@ -174,11 +163,11 @@ void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num,
for (i = num; i > 0; i--) {
const struct mtk_fixed_factor *ff = &clks[i - 1];
if (IS_ERR_OR_NULL(clk_data->clks[ff->id]))
if (IS_ERR_OR_NULL(clk_data->hws[ff->id]))
continue;
clk_unregister_fixed_factor(clk_data->clks[ff->id]);
clk_data->clks[ff->id] = ERR_PTR(-ENOENT);
clk_unregister_fixed_factor(clk_data->hws[ff->id]->clk);
clk_data->hws[ff->id] = ERR_PTR(-ENOENT);
}
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors);
@ -298,7 +287,7 @@ static void mtk_clk_unregister_composite(struct clk *clk)
int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
struct clk *clk;
int i;
@ -309,7 +298,7 @@ int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
for (i = 0; i < num; i++) {
const struct mtk_composite *mc = &mcs[i];
if (!IS_ERR_OR_NULL(clk_data->clks[mc->id])) {
if (!IS_ERR_OR_NULL(clk_data->hws[mc->id])) {
pr_warn("Trying to register duplicate clock ID: %d\n",
mc->id);
continue;
@ -322,7 +311,7 @@ int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
goto err;
}
clk_data->clks[mc->id] = clk;
clk_data->hws[mc->id] = __clk_get_hw(clk);
}
return 0;
@ -331,11 +320,11 @@ int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
while (--i >= 0) {
const struct mtk_composite *mc = &mcs[i];
if (IS_ERR_OR_NULL(clk_data->clks[mcs->id]))
if (IS_ERR_OR_NULL(clk_data->hws[mcs->id]))
continue;
mtk_clk_unregister_composite(clk_data->clks[mc->id]);
clk_data->clks[mc->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_composite(clk_data->hws[mc->id]->clk);
clk_data->hws[mc->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(clk);
@ -343,7 +332,7 @@ int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
EXPORT_SYMBOL_GPL(mtk_clk_register_composites);
void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
@ -353,18 +342,18 @@ void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
for (i = num; i > 0; i--) {
const struct mtk_composite *mc = &mcs[i - 1];
if (IS_ERR_OR_NULL(clk_data->clks[mc->id]))
if (IS_ERR_OR_NULL(clk_data->hws[mc->id]))
continue;
mtk_clk_unregister_composite(clk_data->clks[mc->id]);
clk_data->clks[mc->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_composite(clk_data->hws[mc->id]->clk);
clk_data->hws[mc->id] = ERR_PTR(-ENOENT);
}
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_composites);
int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num,
void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
struct clk *clk;
int i;
@ -375,7 +364,7 @@ int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num,
for (i = 0; i < num; i++) {
const struct mtk_clk_divider *mcd = &mcds[i];
if (!IS_ERR_OR_NULL(clk_data->clks[mcd->id])) {
if (!IS_ERR_OR_NULL(clk_data->hws[mcd->id])) {
pr_warn("Trying to register duplicate clock ID: %d\n",
mcd->id);
continue;
@ -390,7 +379,7 @@ int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num,
goto err;
}
clk_data->clks[mcd->id] = clk;
clk_data->hws[mcd->id] = __clk_get_hw(clk);
}
return 0;
@ -399,18 +388,18 @@ int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num,
while (--i >= 0) {
const struct mtk_clk_divider *mcd = &mcds[i];
if (IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
if (IS_ERR_OR_NULL(clk_data->hws[mcd->id]))
continue;
mtk_clk_unregister_composite(clk_data->clks[mcd->id]);
clk_data->clks[mcd->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_composite(clk_data->hws[mcd->id]->clk);
clk_data->hws[mcd->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(clk);
}
void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
@ -420,18 +409,18 @@ void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num,
for (i = num; i > 0; i--) {
const struct mtk_clk_divider *mcd = &mcds[i - 1];
if (IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
if (IS_ERR_OR_NULL(clk_data->hws[mcd->id]))
continue;
clk_unregister_divider(clk_data->clks[mcd->id]);
clk_data->clks[mcd->id] = ERR_PTR(-ENOENT);
clk_unregister_divider(clk_data->hws[mcd->id]->clk);
clk_data->hws[mcd->id] = ERR_PTR(-ENOENT);
}
}
int mtk_clk_simple_probe(struct platform_device *pdev)
{
const struct mtk_clk_desc *mcd;
struct clk_onecell_data *clk_data;
struct clk_hw_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
int r;
@ -447,7 +436,7 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
if (r)
goto free_data;
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_clks;
@ -465,7 +454,7 @@ int mtk_clk_simple_probe(struct platform_device *pdev)
int mtk_clk_simple_remove(struct platform_device *pdev)
{
const struct mtk_clk_desc *mcd = of_device_get_match_data(&pdev->dev);
struct clk_onecell_data *clk_data = platform_get_drvdata(pdev);
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
struct device_node *node = pdev->dev.of_node;
of_clk_del_provider(node);

20
drivers/clk/mediatek/clk-mtk.h
View file

@ -35,9 +35,9 @@ struct mtk_fixed_clk {
}
int mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_fixed_clks(const struct mtk_fixed_clk *clks, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
struct mtk_fixed_factor {
int id;
@ -56,9 +56,9 @@ struct mtk_fixed_factor {
}
int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
struct mtk_composite {
int id;
@ -149,9 +149,9 @@ struct mtk_composite {
int mtk_clk_register_composites(const struct mtk_composite *mcs, int num,
void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
struct mtk_clk_divider {
int id;
@ -177,12 +177,12 @@ struct mtk_clk_divider {
int mtk_clk_register_dividers(const struct mtk_clk_divider *mcds, int num,
void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
void mtk_free_clk_data(struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
void mtk_free_clk_data(struct clk_hw_onecell_data *clk_data);
struct clk *mtk_clk_register_ref2usb_tx(const char *name,
const char *parent_name, void __iomem *reg);

20
drivers/clk/mediatek/clk-mux.c
View file

@ -193,7 +193,7 @@ static void mtk_clk_unregister_mux(struct clk *clk)
int mtk_clk_register_muxes(const struct mtk_mux *muxes,
int num, struct device_node *node,
spinlock_t *lock,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
struct regmap *regmap;
struct clk *clk;
@ -208,7 +208,7 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes,
for (i = 0; i < num; i++) {
const struct mtk_mux *mux = &muxes[i];
if (!IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, mux->id);
continue;
@ -221,7 +221,7 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes,
goto err;
}
clk_data->clks[mux->id] = clk;
clk_data->hws[mux->id] = __clk_get_hw(clk);
}
return 0;
@ -230,11 +230,11 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes,
while (--i >= 0) {
const struct mtk_mux *mux = &muxes[i];
if (IS_ERR_OR_NULL(clk_data->clks[mux->id]))
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
continue;
mtk_clk_unregister_mux(clk_data->clks[mux->id]);
clk_data->clks[mux->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_mux(clk_data->hws[mux->id]->clk);
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
}
return PTR_ERR(clk);
@ -242,7 +242,7 @@ int mtk_clk_register_muxes(const struct mtk_mux *muxes,
EXPORT_SYMBOL_GPL(mtk_clk_register_muxes);
void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
int i;
@ -252,11 +252,11 @@ void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num,
for (i = num; i > 0; i--) {
const struct mtk_mux *mux = &muxes[i - 1];
if (IS_ERR_OR_NULL(clk_data->clks[mux->id]))
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
continue;
mtk_clk_unregister_mux(clk_data->clks[mux->id]);
clk_data->clks[mux->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_mux(clk_data->hws[mux->id]->clk);
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
}
}
EXPORT_SYMBOL_GPL(mtk_clk_unregister_muxes);

6
drivers/clk/mediatek/clk-mux.h
View file

@ -11,7 +11,7 @@
#include <linux/types.h>
struct clk;
struct clk_onecell_data;
struct clk_hw_onecell_data;
struct clk_ops;
struct device_node;
@ -84,9 +84,9 @@ extern const struct clk_ops mtk_mux_gate_clr_set_upd_ops;
int mtk_clk_register_muxes(const struct mtk_mux *muxes,
int num, struct device_node *node,
spinlock_t *lock,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_muxes(const struct mtk_mux *muxes, int num,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
#endif /* __DRV_CLK_MTK_MUX_H */

23
drivers/clk/mediatek/clk-pll.c
View file

@ -375,7 +375,7 @@ static void mtk_clk_unregister_pll(struct clk *clk)
int mtk_clk_register_plls(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
void __iomem *base;
int i;
@ -390,7 +390,7 @@ int mtk_clk_register_plls(struct device_node *node,
for (i = 0; i < num_plls; i++) {
const struct mtk_pll_data *pll = &plls[i];
if (!IS_ERR_OR_NULL(clk_data->clks[pll->id])) {
if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, pll->id);
continue;
@ -403,7 +403,7 @@ int mtk_clk_register_plls(struct device_node *node,
goto err;
}
clk_data->clks[pll->id] = clk;
clk_data->hws[pll->id] = __clk_get_hw(clk);
}
return 0;
@ -412,8 +412,8 @@ int mtk_clk_register_plls(struct device_node *node,
while (--i >= 0) {
const struct mtk_pll_data *pll = &plls[i];
mtk_clk_unregister_pll(clk_data->clks[pll->id]);
clk_data->clks[pll->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_pll(clk_data->hws[pll->id]->clk);
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
}
iounmap(base);
@ -422,17 +422,16 @@ int mtk_clk_register_plls(struct device_node *node,
}
EXPORT_SYMBOL_GPL(mtk_clk_register_plls);
static __iomem void *mtk_clk_pll_get_base(struct clk *clk,
static __iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
const struct mtk_pll_data *data)
{
struct clk_hw *hw = __clk_get_hw(clk);
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
return pll->base_addr - data->reg;
}
void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
struct clk_onecell_data *clk_data)
struct clk_hw_onecell_data *clk_data)
{
__iomem void *base = NULL;
int i;
@ -443,7 +442,7 @@ void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
for (i = num_plls; i > 0; i--) {
const struct mtk_pll_data *pll = &plls[i - 1];
if (IS_ERR_OR_NULL(clk_data->clks[pll->id]))
if (IS_ERR_OR_NULL(clk_data->hws[pll->id]))
continue;
/*
@ -452,10 +451,10 @@ void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
* pointer to the I/O region base address. We have to fetch
* it from one of the registered clks.
*/
base = mtk_clk_pll_get_base(clk_data->clks[pll->id], pll);
base = mtk_clk_pll_get_base(clk_data->hws[pll->id], pll);
mtk_clk_unregister_pll(clk_data->clks[pll->id]);
clk_data->clks[pll->id] = ERR_PTR(-ENOENT);
mtk_clk_unregister_pll(clk_data->hws[pll->id]->clk);
clk_data->hws[pll->id] = ERR_PTR(-ENOENT);
}
iounmap(base);

6
drivers/clk/mediatek/clk-pll.h
View file

@ -10,7 +10,7 @@
#include <linux/types.h>
struct clk_ops;
struct clk_onecell_data;
struct clk_hw_onecell_data;
struct device_node;
struct mtk_pll_div_table {
@ -50,8 +50,8 @@ struct mtk_pll_data {
int mtk_clk_register_plls(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
struct clk_onecell_data *clk_data);
struct clk_hw_onecell_data *clk_data);
#endif /* __DRV_CLK_MTK_PLL_H */