arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SoM
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam. General features: - NXP i.MX8M Mini - Up to 2GB LDDR4 - 8/16GB eMMC - Gigabit Ethernet - USB 2.0 Host/OTG - PCIe Gen2 interface - I2S - MIPI DSI to LVDS - rest of i.MX8M Mini features i.Core MX8M Mini needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Matteo Lisi <matteo.lisi@engicam.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Jagan Teki
Shawn Guo
parent
4e43cd636b
commit
60ac35268f
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 NXP
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* Copyright (c) 2019 Engicam srl
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* Copyright (c) 2020 Amarula Solutons(India)
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*/
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/ {
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compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
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};
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&A53_0 {
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cpu-supply = <®_buck4>;
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};
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&A53_1 {
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cpu-supply = <®_buck4>;
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};
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&A53_2 {
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cpu-supply = <®_buck4>;
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};
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&A53_3 {
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cpu-supply = <®_buck4>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@8 {
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compatible = "nxp,pf8121a";
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reg = <0x08>;
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regulators {
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reg_ldo1: ldo1 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_ldo2: ldo2 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_ldo3: ldo3 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_ldo4: ldo4 {
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_buck1: buck1 {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_buck2: buck2 {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_buck3: buck3 {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_buck4: buck4 {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_buck5: buck5 {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_buck6: buck6 {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_buck7: buck7 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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reg_vsnvs: vsnvs {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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};
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
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MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
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MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
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>;
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};
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pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
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>;
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};
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pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
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fsl,pins = <
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MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
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MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
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MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
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MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
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MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
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MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
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MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
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MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
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MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
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MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
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MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
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>;
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};
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};
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/* eMMC */
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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