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drm/i915/display/fdi: use intel_de_rmw if possible
The helper makes the code more compact and readable. Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20221215125610.1161729-1-andrzej.hajda@intel.com
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2b6f7e39cc
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60bb4478f7
1 changed files with 44 additions and 104 deletions
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@ -439,19 +439,11 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc,
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drm_err(&dev_priv->drm, "FDI train 1 fail!\n");
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/* Train 2 */
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reg = FDI_TX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_2;
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intel_de_write(dev_priv, reg, temp);
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reg = FDI_RX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_2;
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intel_de_write(dev_priv, reg, temp);
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intel_de_posting_read(dev_priv, reg);
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intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
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FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
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intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
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FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_2);
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intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
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udelay(150);
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reg = FDI_RX_IIR(pipe);
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@ -538,13 +530,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
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udelay(150);
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for (i = 0; i < 4; i++) {
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reg = FDI_TX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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temp |= snb_b_fdi_train_param[i];
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intel_de_write(dev_priv, reg, temp);
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intel_de_posting_read(dev_priv, reg);
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intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
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FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
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intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
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udelay(500);
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for (retry = 0; retry < 5; retry++) {
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@ -593,13 +581,9 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc,
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udelay(150);
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for (i = 0; i < 4; i++) {
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reg = FDI_TX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
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temp |= snb_b_fdi_train_param[i];
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intel_de_write(dev_priv, reg, temp);
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intel_de_posting_read(dev_priv, reg);
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intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
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FDI_LINK_TRAIN_VOL_EMP_MASK, snb_b_fdi_train_param[i]);
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intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
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udelay(500);
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for (retry = 0; retry < 5; retry++) {
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@ -719,19 +703,13 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
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}
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/* Train 2 */
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reg = FDI_TX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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temp &= ~FDI_LINK_TRAIN_NONE_IVB;
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temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
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intel_de_write(dev_priv, reg, temp);
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reg = FDI_RX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
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intel_de_write(dev_priv, reg, temp);
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intel_de_posting_read(dev_priv, reg);
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intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
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FDI_LINK_TRAIN_NONE_IVB,
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FDI_LINK_TRAIN_PATTERN_2_IVB);
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intel_de_rmw(dev_priv, FDI_RX_CTL(pipe),
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FDI_LINK_TRAIN_PATTERN_MASK_CPT,
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FDI_LINK_TRAIN_PATTERN_2_CPT);
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intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
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udelay(2); /* should be 1.5us */
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for (i = 0; i < 4; i++) {
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@ -837,9 +815,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
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udelay(30);
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/* Unset FDI_RX_MISC pwrdn lanes */
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temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
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temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
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intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
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FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK, 0);
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intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
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/* Wait for FDI auto training time */
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@ -865,25 +842,21 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
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intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
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intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
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temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
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temp &= ~DDI_BUF_CTL_ENABLE;
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intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
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intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
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intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
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/* Disable DP_TP_CTL and FDI_RX_CTL and retry */
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temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
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temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
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temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
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intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
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intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E),
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DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK,
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DP_TP_CTL_LINK_TRAIN_PAT1);
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intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
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intel_wait_ddi_buf_idle(dev_priv, PORT_E);
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/* Reset FDI_RX_MISC pwrdn lanes */
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temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
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temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
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intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
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intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
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FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
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FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
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intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
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}
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@ -898,7 +871,6 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
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void hsw_fdi_disable(struct intel_encoder *encoder)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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u32 val;
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/*
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* Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
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@ -906,30 +878,15 @@ void hsw_fdi_disable(struct intel_encoder *encoder)
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* step 13 is the correct place for it. Step 18 is where it was
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* originally before the BUN.
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*/
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val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
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val &= ~FDI_RX_ENABLE;
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intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
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val = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
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val &= ~DDI_BUF_CTL_ENABLE;
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intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), val);
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intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_ENABLE, 0);
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intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0);
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intel_wait_ddi_buf_idle(dev_priv, PORT_E);
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intel_ddi_disable_clock(encoder);
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val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
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val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
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val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
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intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
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val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
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val &= ~FDI_PCDCLK;
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intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
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val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
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val &= ~FDI_RX_PLL_ENABLE;
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intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
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intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A),
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FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK,
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FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2));
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intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_PCDCLK, 0);
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intel_de_rmw(dev_priv, FDI_RX_CTL(PIPE_A), FDI_RX_PLL_ENABLE, 0);
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}
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void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
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@ -952,9 +909,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
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udelay(200);
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/* Switch from Rawclk to PCDclk */
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temp = intel_de_read(dev_priv, reg);
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intel_de_write(dev_priv, reg, temp | FDI_PCDCLK);
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intel_de_rmw(dev_priv, reg, 0, FDI_PCDCLK);
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intel_de_posting_read(dev_priv, reg);
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udelay(200);
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@ -974,28 +929,18 @@ void ilk_fdi_pll_disable(struct intel_crtc *crtc)
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struct drm_device *dev = crtc->base.dev;
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struct drm_i915_private *dev_priv = to_i915(dev);
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enum pipe pipe = crtc->pipe;
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i915_reg_t reg;
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u32 temp;
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/* Switch from PCDclk to Rawclk */
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reg = FDI_RX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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intel_de_write(dev_priv, reg, temp & ~FDI_PCDCLK);
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intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_PCDCLK, 0);
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/* Disable CPU FDI TX PLL */
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reg = FDI_TX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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intel_de_write(dev_priv, reg, temp & ~FDI_TX_PLL_ENABLE);
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intel_de_posting_read(dev_priv, reg);
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intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_PLL_ENABLE, 0);
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intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
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udelay(100);
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reg = FDI_RX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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intel_de_write(dev_priv, reg, temp & ~FDI_RX_PLL_ENABLE);
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/* Wait for the clocks to turn off. */
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intel_de_posting_read(dev_priv, reg);
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intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), FDI_RX_PLL_ENABLE, 0);
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intel_de_posting_read(dev_priv, FDI_RX_CTL(pipe));
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udelay(100);
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}
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@ -1007,10 +952,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
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u32 temp;
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/* disable CPU FDI tx and PCH FDI rx */
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reg = FDI_TX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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intel_de_write(dev_priv, reg, temp & ~FDI_TX_ENABLE);
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intel_de_posting_read(dev_priv, reg);
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intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), FDI_TX_ENABLE, 0);
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intel_de_posting_read(dev_priv, FDI_TX_CTL(pipe));
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reg = FDI_RX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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@ -1027,11 +970,8 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
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FDI_RX_PHASE_SYNC_POINTER_OVR);
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/* still set train pattern 1 */
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reg = FDI_TX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_PATTERN_1;
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intel_de_write(dev_priv, reg, temp);
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intel_de_rmw(dev_priv, FDI_TX_CTL(pipe),
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FDI_LINK_TRAIN_NONE, FDI_LINK_TRAIN_PATTERN_1);
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reg = FDI_RX_CTL(pipe);
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temp = intel_de_read(dev_priv, reg);
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