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Hexagon: add support for new v4+ registers
Add support for a couple new v4+ registers, along with newer save/restore pt_regs. Signed-off-by: Richard Kuo <rkuo@codeaurora.org>
This commit is contained in:
parent
444dd742d3
commit
60c4ba99e0
8 changed files with 206 additions and 48 deletions
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@ -57,10 +57,17 @@ struct pt_regs {
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};
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union {
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struct {
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unsigned long gp;
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unsigned long ugp;
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unsigned long gp;
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};
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long long int ugpgp;
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long long int gpugp;
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};
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union {
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struct {
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unsigned long cs0;
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unsigned long cs1;
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};
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long long int cs1cs0;
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};
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/*
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* Be extremely careful with rearranging these, if at all. Some code
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@ -55,9 +55,15 @@ struct user_regs_struct {
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unsigned long pc;
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unsigned long cause;
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unsigned long badva;
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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unsigned long pad1; /* pad out to 48 words total */
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unsigned long pad2; /* pad out to 48 words total */
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unsigned long pad3; /* pad out to 48 words total */
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#else
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unsigned long cs0;
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unsigned long cs1;
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unsigned long pad1; /* pad out to 48 words total */
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#endif
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};
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#endif
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@ -44,7 +44,8 @@ int main(void)
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COMMENT("Hexagon pt_regs definitions");
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OFFSET(_PT_SYSCALL_NR, pt_regs, syscall_nr);
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OFFSET(_PT_UGPGP, pt_regs, ugpgp);
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OFFSET(_PT_GPUGP, pt_regs, gpugp);
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OFFSET(_PT_CS1CS0, pt_regs, cs1cs0);
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OFFSET(_PT_R3130, pt_regs, r3130);
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OFFSET(_PT_R2928, pt_regs, r2928);
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OFFSET(_PT_R2726, pt_regs, r2726);
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@ -70,6 +70,8 @@ struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
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{ "lc1", GDB_SIZEOF_REG, offsetof(struct pt_regs, lc1)},
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{ " gp", GDB_SIZEOF_REG, offsetof(struct pt_regs, gp)},
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{ "ugp", GDB_SIZEOF_REG, offsetof(struct pt_regs, ugp)},
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{ "cs0", GDB_SIZEOF_REG, offsetof(struct pt_regs, cs0)},
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{ "cs1", GDB_SIZEOF_REG, offsetof(struct pt_regs, cs1)},
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{ "psp", GDB_SIZEOF_REG, offsetof(struct pt_regs, hvmer.vmpsp)},
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{ "elr", GDB_SIZEOF_REG, offsetof(struct pt_regs, hvmer.vmel)},
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{ "est", GDB_SIZEOF_REG, offsetof(struct pt_regs, hvmer.vmest)},
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@ -76,6 +76,10 @@ static int genregs_get(struct task_struct *target,
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dummy = pt_cause(regs);
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ONEXT(&dummy, cause);
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ONEXT(&pt_badva(regs), badva);
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#if CONFIG_HEXAGON_ARCH_VERSION >=4
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ONEXT(®s->cs0, cs0);
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ONEXT(®s->cs1, cs1);
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#endif
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/* Pad the rest with zeros, if needed */
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if (!ret)
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@ -123,6 +127,11 @@ static int genregs_set(struct task_struct *target,
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INEXT(&bucket, cause);
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INEXT(&bucket, badva);
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#if CONFIG_HEXAGON_ARCH_VERSION >=4
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INEXT(®s->cs0, cs0);
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INEXT(®s->cs1, cs1);
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#endif
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/* Ignore the rest, if needed */
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if (!ret)
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ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
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@ -66,7 +66,10 @@ static int setup_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
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err |= __put_user(regs->preds, &sc->sc_regs.p3_0);
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err |= __put_user(regs->gp, &sc->sc_regs.gp);
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err |= __put_user(regs->ugp, &sc->sc_regs.ugp);
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#if CONFIG_HEXAGON_ARCH_VERSION >= 4
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err |= __put_user(regs->cs0, &sc->sc_regs.cs0);
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err |= __put_user(regs->cs1, &sc->sc_regs.cs1);
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#endif
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tmp = pt_elr(regs); err |= __put_user(tmp, &sc->sc_regs.pc);
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tmp = pt_cause(regs); err |= __put_user(tmp, &sc->sc_regs.cause);
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tmp = pt_badva(regs); err |= __put_user(tmp, &sc->sc_regs.badva);
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@ -93,7 +96,10 @@ static int restore_sigcontext(struct pt_regs *regs,
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err |= __get_user(regs->preds, &sc->sc_regs.p3_0);
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err |= __get_user(regs->gp, &sc->sc_regs.gp);
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err |= __get_user(regs->ugp, &sc->sc_regs.ugp);
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#if CONFIG_HEXAGON_ARCH_VERSION >= 4
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err |= __get_user(regs->cs0, &sc->sc_regs.cs0);
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err |= __get_user(regs->cs1, &sc->sc_regs.cs1);
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#endif
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err |= __get_user(tmp, &sc->sc_regs.pc); pt_set_elr(regs, tmp);
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return err;
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@ -45,48 +45,88 @@
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* number in the case where we decode a system call (trap0(#1)).
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*/
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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#define save_pt_regs()\
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memd(R0 + #_PT_R3130) = R31:30; \
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memd(R0 + #_PT_R3130) = R31:30; \
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{ memw(R0 + #_PT_R2928) = R28; \
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R31 = memw(R0 + #_PT_ER_VMPSP); }\
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{ memw(R0 + #(_PT_R2928 + 4)) = R31; \
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R31 = ugp; } \
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{ memd(R0 + #_PT_R2726) = R27:26; \
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R30 = gp ; } \
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memd(R0 + #_PT_R2524) = R25:24; \
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memd(R0 + #_PT_R2322) = R23:22; \
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memd(R0 + #_PT_R2120) = R21:20; \
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memd(R0 + #_PT_R1918) = R19:18; \
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memd(R0 + #_PT_R1716) = R17:16; \
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memd(R0 + #_PT_R1514) = R15:14; \
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memd(R0 + #_PT_R1312) = R13:12; \
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{ memd(R0 + #_PT_R1110) = R11:10; \
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R15 = lc0; } \
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{ memd(R0 + #_PT_R0908) = R9:8; \
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R14 = sa0; } \
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{ memd(R0 + #_PT_R0706) = R7:6; \
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R13 = lc1; } \
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{ memd(R0 + #_PT_R0504) = R5:4; \
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R12 = sa1; } \
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{ memd(R0 + #_PT_GPUGP) = R31:30; \
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R11 = m1; \
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R2.H = #HI(_THREAD_SIZE); } \
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{ memd(R0 + #_PT_LC0SA0) = R15:14; \
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R10 = m0; \
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R2.L = #LO(_THREAD_SIZE); } \
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{ memd(R0 + #_PT_LC1SA1) = R13:12; \
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R15 = p3:0; \
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R2 = neg(R2); } \
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{ memd(R0 + #_PT_M1M0) = R11:10; \
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R14 = usr; \
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R2 = and(R0,R2); } \
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{ memd(R0 + #_PT_PREDSUSR) = R15:14; \
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THREADINFO_REG = R2; } \
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{ r24 = memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS); \
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memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
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R2 = #-1; } \
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{ memw(R0 + #_PT_SYSCALL_NR) = R2; \
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R30 = #0; }
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#else
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/* V4+ */
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/* the # ## # syntax inserts a literal ## */
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#define save_pt_regs()\
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{ memd(R0 + #_PT_R3130) = R31:30; \
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R30 = memw(R0 + #_PT_ER_VMPSP); }\
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{ memw(R0 + #_PT_R2928) = R28; \
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R31 = memw(R0 + #_PT_ER_VMPSP); }\
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{ memw(R0 + #(_PT_R2928 + 4)) = R31; \
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R31 = ugp; } \
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{ memd(R0 + #_PT_R2726) = R27:26; \
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R30 = gp ; } \
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memd(R0 + #_PT_R2524) = R25:24; \
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memd(R0 + #_PT_R2322) = R23:22; \
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memd(R0 + #_PT_R2120) = R21:20; \
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memd(R0 + #_PT_R1918) = R19:18; \
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memd(R0 + #_PT_R1716) = R17:16; \
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memd(R0 + #_PT_R1514) = R15:14; \
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memd(R0 + #_PT_R1312) = R13:12; \
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memw(R0 + #(_PT_R2928 + 4)) = R30; }\
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{ R31:30 = C11:10; \
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memd(R0 + #_PT_R2726) = R27:26; \
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memd(R0 + #_PT_R2524) = R25:24; }\
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{ memd(R0 + #_PT_R2322) = R23:22; \
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memd(R0 + #_PT_R2120) = R21:20; }\
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{ memd(R0 + #_PT_R1918) = R19:18; \
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memd(R0 + #_PT_R1716) = R17:16; }\
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{ memd(R0 + #_PT_R1514) = R15:14; \
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memd(R0 + #_PT_R1312) = R13:12; \
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R17:16 = C13:12; }\
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{ memd(R0 + #_PT_R1110) = R11:10; \
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R15 = lc0; } \
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{ memd(R0 + #_PT_R0908) = R9:8; \
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R14 = sa0; } \
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memd(R0 + #_PT_R0908) = R9:8; \
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R15:14 = C1:0; } \
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{ memd(R0 + #_PT_R0706) = R7:6; \
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R13 = lc1; } \
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{ memd(R0 + #_PT_R0504) = R5:4; \
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R12 = sa1; } \
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{ memd(R0 + #_PT_UGPGP) = R31:30; \
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R11 = m1; \
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R2.H = #HI(_THREAD_SIZE); } \
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{ memd(R0 + #_PT_LC0SA0) = R15:14; \
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R10 = m0; \
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R2.L = #LO(_THREAD_SIZE); } \
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{ memd(R0 + #_PT_LC1SA1) = R13:12; \
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R15 = p3:0; \
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R2 = neg(R2); } \
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memd(R0 + #_PT_R0504) = R5:4; \
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R13:12 = C3:2; } \
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{ memd(R0 + #_PT_GPUGP) = R31:30; \
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memd(R0 + #_PT_LC0SA0) = R15:14; \
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R11:10 = C7:6; }\
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{ THREADINFO_REG = and(R0, # ## #-_THREAD_SIZE); \
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memd(R0 + #_PT_LC1SA1) = R13:12; \
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R15 = p3:0; }\
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{ memd(R0 + #_PT_M1M0) = R11:10; \
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R14 = usr; \
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R2 = and(R0,R2); } \
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{ memd(R0 + #_PT_PREDSUSR) = R15:14; \
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THREADINFO_REG = R2; } \
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memw(R0 + #_PT_PREDSUSR + 4) = R15; }\
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{ r24 = memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS); \
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memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R0; \
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R2 = #-1; } \
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{ memw(R0 + #_PT_SYSCALL_NR) = R2; \
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memd(R0 + #_PT_CS1CS0) = R17:16; \
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R30 = #0; }
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#endif
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/*
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* Restore registers and thread_info.regs state. THREADINFO_REG
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@ -94,6 +134,7 @@
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* preserved. Don't restore R29 (SP) until later.
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*/
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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#define restore_pt_regs() \
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{ memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R24; \
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R15:14 = memd(R0 + #_PT_PREDSUSR); } \
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R23:22 = memd(R0 + #_PT_R2322); } \
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{ R25:24 = memd(R0 + #_PT_R2524); \
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R27:26 = memd(R0 + #_PT_R2726); } \
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R31:30 = memd(R0 + #_PT_UGPGP); \
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R31:30 = memd(R0 + #_PT_GPUGP); \
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{ R28 = memw(R0 + #_PT_R2928); \
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ugp = R31; } \
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{ R31:30 = memd(R0 + #_PT_R3130); \
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gp = R30; }
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#else
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/* V4+ */
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#define restore_pt_regs() \
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{ memw(THREADINFO_REG + #_THREAD_INFO_PT_REGS) = R24; \
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R15:14 = memd(R0 + #_PT_PREDSUSR); } \
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{ R11:10 = memd(R0 + #_PT_M1M0); \
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R13:12 = memd(R0 + #_PT_LC1SA1); \
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p3:0 = R15; } \
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{ R15:14 = memd(R0 + #_PT_LC0SA0); \
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R3:2 = memd(R0 + #_PT_R0302); \
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usr = R14; } \
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{ R5:4 = memd(R0 + #_PT_R0504); \
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R7:6 = memd(R0 + #_PT_R0706); \
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C7:6 = R11:10; }\
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{ R9:8 = memd(R0 + #_PT_R0908); \
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R11:10 = memd(R0 + #_PT_R1110); \
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C3:2 = R13:12; }\
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{ R13:12 = memd(R0 + #_PT_R1312); \
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R15:14 = memd(R0 + #_PT_R1514); \
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C1:0 = R15:14; }\
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{ R17:16 = memd(R0 + #_PT_R1716); \
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R19:18 = memd(R0 + #_PT_R1918); } \
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{ R21:20 = memd(R0 + #_PT_R2120); \
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R23:22 = memd(R0 + #_PT_R2322); } \
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{ R25:24 = memd(R0 + #_PT_R2524); \
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R27:26 = memd(R0 + #_PT_R2726); } \
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R31:30 = memd(R0 + #_PT_CS1CS0); \
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{ C13:12 = R31:30; \
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R31:30 = memd(R0 + #_PT_GPUGP) ; \
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R28 = memw(R0 + #_PT_R2928); }\
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{ C11:10 = R31:30; \
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R31:30 = memd(R0 + #_PT_R3130); }
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#endif
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/*
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* Clears off enough space for the rest of pt_regs; evrec is a part
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* Need to save off R0, R1, R2, R3 immediately.
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*/
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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#define vm_event_entry(CHandler) \
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{ \
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R29 = add(R29, #-(_PT_REGS_SIZE)); \
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R1.H = #HI(CHandler); \
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jump event_dispatch; \
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}
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#else
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/* V4+ */
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/* turn on I$ prefetch early */
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/* the # ## # syntax inserts a literal ## */
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#define vm_event_entry(CHandler) \
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{ \
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R29 = add(R29, #-(_PT_REGS_SIZE)); \
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memd(R29 + #(_PT_R0100 + -_PT_REGS_SIZE)) = R1:0; \
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memd(R29 + #(_PT_R0302 + -_PT_REGS_SIZE)) = R3:2; \
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R0 = usr; \
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} \
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{ \
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memw(R29 + #_PT_PREDSUSR) = R0; \
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R0 = setbit(R0, #16); \
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} \
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usr = R0; \
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R1:0 = G1:0; \
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{ \
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memd(R29 + #_PT_ER_VMEL) = R1:0; \
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R1 = # ## #(CHandler); \
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R3:2 = G3:2; \
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} \
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{ \
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R0 = R29; \
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memd(R29 + #_PT_ER_VMPSP) = R3:2; \
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jump event_dispatch; \
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}
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#endif
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.text
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/*
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/* "Nested control path" -- if the previous mode was kernel */
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R0 = memw(R29 + #_PT_ER_VMEST);
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P0 = tstbit(R0, #HVM_VMEST_UM_SFT);
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if !P0 jump restore_all;
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{
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P0 = tstbit(R0, #HVM_VMEST_UM_SFT);
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if (!P0.new) jump:nt restore_all;
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}
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/*
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* Returning from system call, normally coming back from user mode
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*/
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* Coming back from the C-world, our thread info pointer
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* should be in the designated register (usually R19)
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*/
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#if CONFIG_HEXAGON_ARCH_VERSION < 4
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R1.L = #LO(_TIF_ALLWORK_MASK)
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{
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R1.H = #HI(_TIF_ALLWORK_MASK);
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R0 = memw(THREADINFO_REG + #_THREAD_INFO_FLAGS);
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}
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#else
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{
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R1 = ##_TIF_ALLWORK_MASK;
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R0 = memw(THREADINFO_REG + #_THREAD_INFO_FLAGS);
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}
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#endif
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/*
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* Compare against the "return to userspace" _TIF_WORK_MASK
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@ -222,10 +334,14 @@ work_pending:
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work_notifysig:
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/* this is the part that's kind of fuzzy. */
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R1 = and(R0, #(_TIF_SIGPENDING | _TIF_NOTIFY_RESUME));
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P0 = cmp.eq(R1, #0);
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if P0 jump restore_all
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R1 = R0; /* unsigned long thread_info_flags */
|
||||
R0 = R29; /* regs should still be at top of stack */
|
||||
{
|
||||
P0 = cmp.eq(R1, #0);
|
||||
if P0.new jump:t restore_all;
|
||||
}
|
||||
{
|
||||
R1 = R0; /* unsigned long thread_info_flags */
|
||||
R0 = R29; /* regs should still be at top of stack */
|
||||
}
|
||||
call do_notify_resume
|
||||
|
||||
restore_all:
|
||||
|
@ -235,14 +351,23 @@ restore_all:
|
|||
|
||||
/* do the setregs here for VM 0.5 */
|
||||
/* R29 here should already be pointing at pt_regs */
|
||||
R1:0 = memd(R29 + #_PT_ER_VMEL);
|
||||
R3:2 = memd(R29 + #_PT_ER_VMPSP);
|
||||
{
|
||||
R1:0 = memd(R29 + #_PT_ER_VMEL);
|
||||
R3:2 = memd(R29 + #_PT_ER_VMPSP);
|
||||
}
|
||||
#if CONFIG_HEXAGON_ARCH_VERSION < 4
|
||||
trap1(#HVM_TRAP1_VMSETREGS);
|
||||
#else
|
||||
G1:0 = R1:0;
|
||||
G3:2 = R3:2;
|
||||
#endif
|
||||
|
||||
R0 = R29
|
||||
restore_pt_regs()
|
||||
R1:0 = memd(R29 + #_PT_R0100);
|
||||
R29 = add(R29, #_PT_REGS_SIZE);
|
||||
{
|
||||
R1:0 = memd(R29 + #_PT_R0100);
|
||||
R29 = add(R29, #_PT_REGS_SIZE);
|
||||
}
|
||||
trap1(#HVM_TRAP1_VMRTE)
|
||||
/* Notreached */
|
||||
|
||||
|
|
|
@ -42,6 +42,8 @@ void show_regs(struct pt_regs *regs)
|
|||
regs->lc1, regs->sa1, regs->m1);
|
||||
printk(KERN_EMERG "gp: \t0x%08lx ugp: 0x%08lx usr: 0x%08lx\n",
|
||||
regs->gp, regs->ugp, regs->usr);
|
||||
printk(KERN_EMERG "cs0: \t0x%08lx cs1: 0x%08lx\n",
|
||||
regs->cs0, regs->cs1);
|
||||
printk(KERN_EMERG "r0: \t0x%08lx %08lx %08lx %08lx\n", regs->r00,
|
||||
regs->r01,
|
||||
regs->r02,
|
||||
|
|
Loading…
Reference in a new issue