mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 19:00:25 +00:00
drm/nouveau: kick vram functions out into an "engine"
NVC0 will be able to share some of nv50's paths this way. This also makes it the card-specific vram code responsible for deciding if a given set of tile_flags is valid, rather than duplicating the allowed types in nv50_vram.c and nouveau_gem.c Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
34cf01bc4b
commit
60d2a88ae8
7 changed files with 74 additions and 51 deletions
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@ -501,6 +501,15 @@ struct nouveau_crypt_engine {
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void (*tlb_flush)(struct drm_device *dev);
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};
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struct nouveau_vram_engine {
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int (*init)(struct drm_device *);
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int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
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u32 type, struct nouveau_vram **);
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void (*put)(struct drm_device *, struct nouveau_vram **);
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bool (*flags_valid)(struct drm_device *, u32 tile_flags);
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};
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struct nouveau_engine {
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struct nouveau_instmem_engine instmem;
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struct nouveau_mc_engine mc;
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@ -512,6 +521,7 @@ struct nouveau_engine {
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struct nouveau_gpio_engine gpio;
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struct nouveau_pm_engine pm;
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struct nouveau_crypt_engine crypt;
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struct nouveau_vram_engine vram;
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};
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struct nouveau_pll_vals {
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@ -821,6 +831,8 @@ extern void nouveau_mem_gart_fini(struct drm_device *);
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extern int nouveau_mem_init_agp(struct drm_device *);
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extern int nouveau_mem_reset_agp(struct drm_device *);
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extern void nouveau_mem_close(struct drm_device *);
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extern int nouveau_mem_detect(struct drm_device *);
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extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
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extern struct nouveau_tile_reg *nv10_mem_set_tiling(
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struct drm_device *dev, uint32_t addr, uint32_t size,
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uint32_t pitch, uint32_t flags);
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@ -103,32 +103,6 @@ nouveau_gem_info(struct drm_gem_object *gem, struct drm_nouveau_gem_info *rep)
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return 0;
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}
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static bool
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nouveau_gem_tile_flags_valid(struct drm_device *dev, uint32_t tile_flags)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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if (dev_priv->card_type >= NV_50) {
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switch (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) {
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case 0x0000:
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case 0x1800:
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case 0x2800:
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case 0x4800:
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case 0x7000:
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case 0x7400:
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case 0x7a00:
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case 0xe000:
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return true;
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}
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} else {
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if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
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return true;
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}
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NV_ERROR(dev, "bad page flags: 0x%08x\n", tile_flags);
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return false;
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}
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int
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nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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@ -150,8 +124,10 @@ nouveau_gem_ioctl_new(struct drm_device *dev, void *data,
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if (!flags || req->info.domain & NOUVEAU_GEM_DOMAIN_CPU)
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flags |= TTM_PL_FLAG_SYSTEM;
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if (!nouveau_gem_tile_flags_valid(dev, req->info.tile_flags))
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if (!dev_priv->engine.vram.flags_valid(dev, req->info.tile_flags)) {
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NV_ERROR(dev, "bad page flags: 0x%08x\n", req->info.tile_flags);
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return -EINVAL;
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}
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if (req->channel_hint) {
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chan = nouveau_channel_get(dev, file_priv, req->channel_hint);
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@ -241,7 +241,7 @@ nouveau_mem_detect_nforce(struct drm_device *dev)
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return 0;
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}
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static int
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int
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nouveau_mem_detect(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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@ -255,26 +255,25 @@ nouveau_mem_detect(struct drm_device *dev)
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if (dev_priv->card_type < NV_50) {
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dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
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dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
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} else
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if (dev_priv->card_type < NV_C0) {
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if (nv50_vram_init(dev))
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return -ENOMEM;
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} else {
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dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
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dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
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}
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NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
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if (dev_priv->vram_sys_base) {
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NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
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dev_priv->vram_sys_base);
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}
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if (dev_priv->vram_size)
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return 0;
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return -ENOMEM;
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}
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bool
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nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
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{
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if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
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return true;
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return false;
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}
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#if __OS_HAS_AGP
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static unsigned long
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get_agp_mode(struct drm_device *dev, unsigned long mode)
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@ -432,11 +431,16 @@ nouveau_mem_vram_init(struct drm_device *dev)
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else
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dev_priv->ramin_rsvd_vram = (512 * 1024);
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/* initialise gpu-specific vram backend */
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ret = nouveau_mem_detect(dev);
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ret = dev_priv->engine.vram.init(dev);
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if (ret)
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return ret;
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NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
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if (dev_priv->vram_sys_base) {
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NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
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dev_priv->vram_sys_base);
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}
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dev_priv->fb_available_size = dev_priv->vram_size;
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dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
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if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
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@ -698,9 +702,10 @@ nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
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struct ttm_mem_reg *mem)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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struct drm_device *dev = dev_priv->dev;
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nv50_vram_del(dev, (struct nouveau_vram **)&mem->mm_node);
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vram->put(dev, (struct nouveau_vram **)&mem->mm_node);
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}
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static int
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@ -710,30 +715,30 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
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struct ttm_mem_reg *mem)
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{
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struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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struct drm_device *dev = dev_priv->dev;
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struct nouveau_bo *nvbo = nouveau_bo(bo);
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struct nouveau_vram *vram;
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struct nouveau_vram *node;
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u32 size_nc = 0;
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int ret;
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if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
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size_nc = 1 << nvbo->vma.node->type;
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ret = nv50_vram_new(dev, mem->num_pages << PAGE_SHIFT,
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mem->page_alignment << PAGE_SHIFT, size_nc,
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(nvbo->tile_flags >> 8) & 0x7f, &vram);
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ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
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mem->page_alignment << PAGE_SHIFT, size_nc,
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(nvbo->tile_flags >> 8) & 0xff, &node);
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if (ret)
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return ret;
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mem->mm_node = vram;
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mem->start = vram->offset >> PAGE_SHIFT;
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mem->mm_node = node;
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mem->start = node->offset >> PAGE_SHIFT;
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return 0;
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}
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void
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nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
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{
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struct ttm_bo_global *glob = man->bdev->glob;
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struct nouveau_mm *mm = man->priv;
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struct nouveau_mm_node *r;
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u64 total = 0, ttotal[3] = {}, tused[3] = {}, tfree[3] = {};
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@ -57,5 +57,6 @@ int nv50_vram_init(struct drm_device *);
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int nv50_vram_new(struct drm_device *, u64 size, u32 align, u32 size_nc,
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u32 memtype, struct nouveau_vram **);
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void nv50_vram_del(struct drm_device *, struct nouveau_vram **);
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bool nv50_vram_flags_valid(struct drm_device *, u32 tile_flags);
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#endif
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@ -100,6 +100,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->pm.clock_set = nv04_pm_clock_set;
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engine->crypt.init = nouveau_stub_init;
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engine->crypt.takedown = nouveau_stub_takedown;
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engine->vram.init = nouveau_mem_detect;
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engine->vram.flags_valid = nouveau_mem_flags_valid;
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break;
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case 0x10:
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engine->instmem.init = nv04_instmem_init;
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@ -157,6 +159,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->pm.clock_set = nv04_pm_clock_set;
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engine->crypt.init = nouveau_stub_init;
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engine->crypt.takedown = nouveau_stub_takedown;
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engine->vram.init = nouveau_mem_detect;
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engine->vram.flags_valid = nouveau_mem_flags_valid;
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break;
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case 0x20:
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engine->instmem.init = nv04_instmem_init;
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@ -214,6 +218,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->pm.clock_set = nv04_pm_clock_set;
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engine->crypt.init = nouveau_stub_init;
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engine->crypt.takedown = nouveau_stub_takedown;
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engine->vram.init = nouveau_mem_detect;
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engine->vram.flags_valid = nouveau_mem_flags_valid;
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break;
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case 0x30:
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engine->instmem.init = nv04_instmem_init;
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@ -273,6 +279,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->pm.voltage_set = nouveau_voltage_gpio_set;
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engine->crypt.init = nouveau_stub_init;
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engine->crypt.takedown = nouveau_stub_takedown;
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engine->vram.init = nouveau_mem_detect;
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engine->vram.flags_valid = nouveau_mem_flags_valid;
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break;
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case 0x40:
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case 0x60:
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@ -334,6 +342,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->pm.temp_get = nv40_temp_get;
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engine->crypt.init = nouveau_stub_init;
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engine->crypt.takedown = nouveau_stub_takedown;
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engine->vram.init = nouveau_mem_detect;
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engine->vram.flags_valid = nouveau_mem_flags_valid;
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break;
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case 0x50:
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case 0x80: /* gotta love NVIDIA's consistency.. */
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@ -444,6 +454,10 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->crypt.takedown = nouveau_stub_takedown;
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break;
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}
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engine->vram.init = nv50_vram_init;
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engine->vram.get = nv50_vram_new;
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engine->vram.put = nv50_vram_del;
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engine->vram.flags_valid = nv50_vram_flags_valid;
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break;
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case 0xC0:
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engine->instmem.init = nvc0_instmem_init;
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@ -495,6 +509,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->gpio.irq_enable = nv50_gpio_irq_enable;
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engine->crypt.init = nouveau_stub_init;
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engine->crypt.takedown = nouveau_stub_takedown;
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engine->vram.init = nouveau_mem_detect;
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engine->vram.flags_valid = nouveau_mem_flags_valid;
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break;
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default:
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NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
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@ -312,6 +312,7 @@ nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
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{
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struct drm_device *dev = gpuobj->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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struct nv50_gpuobj_node *node = NULL;
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int ret;
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@ -323,7 +324,7 @@ nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
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size = (size + 4095) & ~4095;
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align = max(align, (u32)4096);
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ret = nv50_vram_new(dev, size, align, 0, 0, &node->vram);
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ret = vram->get(dev, size, align, 0, 0, &node->vram);
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if (ret) {
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kfree(node);
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return ret;
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@ -336,7 +337,7 @@ nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
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NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
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&node->chan_vma);
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if (ret) {
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nv50_vram_del(dev, &node->vram);
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vram->put(dev, &node->vram);
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kfree(node);
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return ret;
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}
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@ -354,6 +355,8 @@ void
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nv50_instmem_put(struct nouveau_gpuobj *gpuobj)
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{
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struct drm_device *dev = gpuobj->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
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struct nv50_gpuobj_node *node;
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node = gpuobj->node;
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nouveau_vm_unmap(&node->chan_vma);
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nouveau_vm_put(&node->chan_vma);
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}
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nv50_vram_del(dev, &node->vram);
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vram->put(dev, &node->vram);
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kfree(node);
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}
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@ -37,6 +37,16 @@ static int types[0x80] = {
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1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
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};
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bool
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nv50_vram_flags_valid(struct drm_device *dev, u32 tile_flags)
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{
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int type = (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) >> 8;
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if (likely(type < sizeof(types) && types[type]))
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return true;
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return false;
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}
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void
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nv50_vram_del(struct drm_device *dev, struct nouveau_vram **pvram)
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{
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