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m68knommu: collection of fixes for 5.15

Browse source 
. flexcan platform support (for m5441x)
 . fix CONFIG_ROMKERNEL linking
 . fix compilation when CONFIG_ISA_DMA_API is set
 . fix local ColdFire clk_enable() for NULL clk
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Merge tag 'm68knommu-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Pull m68knommu updates from Greg Ungerer:
 "A collection of fixes:

   -  flexcan platform support (for m5441x)

   -  fix CONFIG_ROMKERNEL linking

   -  fix compilation when CONFIG_ISA_DMA_API is set

   -  fix local ColdFire clk_enable() for NULL clk"

* tag 'm68knommu-for-v5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68knommu: only set CONFIG_ISA_DMA_API for ColdFire sub-arch
  m68k: coldfire: return success for clk_enable(NULL)
  m68k: m5441x: add flexcan support
  m68k: stmark2: update board setup
  m68k/nommu: prevent setting ROMKERNEL when ROM is not set
This commit is contained in:
Linus Torvalds 2021-09-01 18:31:45 -07:00
commit 6104dde096
7 changed files with 74 additions and 8 deletions
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2
arch/m68k/Kconfig.bus
View file

@ -63,7 +63,7 @@ source "drivers/zorro/Kconfig"
endif
if !MMU
if COLDFIRE
config ISA_DMA_API
def_bool !M5272

1
arch/m68k/Kconfig.machine
View file

@ -465,6 +465,7 @@ config RAMKERNEL
config ROMKERNEL
bool "ROM"
depends on ROM
help
The kernel will be resident in FLASH/ROM when running. This is
often referred to as Execute-in-Place (XIP), since the kernel

2
arch/m68k/coldfire/clk.c
View file

@ -78,7 +78,7 @@ int clk_enable(struct clk *clk)
unsigned long flags;
if (!clk)
return -EINVAL;
return 0;
spin_lock_irqsave(&clk_lock, flags);
if ((clk->enabled++ == 0) && clk->clk_ops)

44
arch/m68k/coldfire/device.c
View file

@ -581,6 +581,47 @@ static struct platform_device mcf_esdhc = {
};
#endif /* MCFSDHC_BASE */
#if IS_ENABLED(CONFIG_CAN_FLEXCAN)
#include <linux/can/platform/flexcan.h>
static struct flexcan_platform_data mcf5441x_flexcan_info = {
.clk_src = 1,
.clock_frequency = 120000000,
};
static struct resource mcf5441x_flexcan0_resource[] = {
{
.start = MCFFLEXCAN_BASE0,
.end = MCFFLEXCAN_BASE0 + MCFFLEXCAN_SIZE,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_IFL0,
.end = MCF_IRQ_IFL0,
.flags = IORESOURCE_IRQ,
},
{
.start = MCF_IRQ_BOFF0,
.end = MCF_IRQ_BOFF0,
.flags = IORESOURCE_IRQ,
},
{
.start = MCF_IRQ_ERR0,
.end = MCF_IRQ_ERR0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_flexcan0 = {
.name = "flexcan-mcf5441x",
.id = 0,
.num_resources = ARRAY_SIZE(mcf5441x_flexcan0_resource),
.resource = mcf5441x_flexcan0_resource,
.dev.platform_data = &mcf5441x_flexcan_info,
};
#endif /* IS_ENABLED(CONFIG_CAN_FLEXCAN) */
static struct platform_device *mcf_devices[] __initdata = {
&mcf_uart,
#if IS_ENABLED(CONFIG_FEC)
@ -616,6 +657,9 @@ static struct platform_device *mcf_devices[] __initdata = {
#ifdef MCFSDHC_BASE
&mcf_esdhc,
#endif
#if IS_ENABLED(CONFIG_CAN_FLEXCAN)
&mcf_flexcan0,
#endif
};
/*

8
arch/m68k/coldfire/m5441x.c
View file

@ -19,8 +19,8 @@
#include <asm/mcfclk.h>
DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
DEFINE_CLK(0, "flexcan.0", 8, MCF_CLK);
DEFINE_CLK(0, "flexcan.1", 9, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
DEFINE_CLK(0, "edma", 17, MCF_CLK);
@ -142,6 +142,8 @@ static struct clk_lookup m5411x_clk_lookup[] = {
static struct clk * const enable_clks[] __initconst = {
/* make sure these clocks are enabled */
&__clk_0_8, /* flexcan.0 */
&__clk_0_9, /* flexcan.1 */
&__clk_0_15, /* dspi.1 */
&__clk_0_17, /* eDMA */
&__clk_0_18, /* intc0 */
@ -162,8 +164,6 @@ static struct clk * const enable_clks[] __initconst = {
&__clk_1_37, /* gpio */
};
static struct clk * const disable_clks[] __initconst = {
&__clk_0_8, /* can.0 */
&__clk_0_9, /* can.1 */
&__clk_0_14, /* i2c.1 */
&__clk_0_22, /* i2c.0 */
&__clk_0_23, /* dspi.0 */

6
arch/m68k/coldfire/stmark2.c
View file

@ -111,7 +111,9 @@ static int __init init_stmark2(void)
__raw_writeb(0x00, MCFGPIO_PAR_BE);
__raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
__raw_writeb(0x00, MCFGPIO_PAR_CS);
__raw_writeb(0x00, MCFGPIO_PAR_CANI2C);
/* CAN pads */
__raw_writeb(0x50, MCFGPIO_PAR_CANI2C);
platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices));
@ -121,4 +123,4 @@ static int __init init_stmark2(void)
return 0;
}
late_initcall(init_stmark2);
device_initcall(init_stmark2);

19
arch/m68k/include/asm/m5441xsim.h
View file

@ -73,6 +73,12 @@
#define MCFINT0_FECENTC1 55
/* on interrupt controller 1 */
#define MCFINT1_FLEXCAN0_IFL 0
#define MCFINT1_FLEXCAN0_BOFF 1
#define MCFINT1_FLEXCAN0_ERR 3
#define MCFINT1_FLEXCAN1_IFL 4
#define MCFINT1_FLEXCAN1_BOFF 5
#define MCFINT1_FLEXCAN1_ERR 7
#define MCFINT1_UART4 48
#define MCFINT1_UART5 49
#define MCFINT1_UART6 50
@ -314,4 +320,17 @@
#define MCF_IRQ_SDHC (MCFINT2_VECBASE + MCFINT2_SDHC)
#define MCFSDHC_CLK (MCFSDHC_BASE + 0x2c)
/*
* Flexcan module
*/
#define MCFFLEXCAN_BASE0 0xfc020000
#define MCFFLEXCAN_BASE1 0xfc024000
#define MCFFLEXCAN_SIZE 0x4000
#define MCF_IRQ_IFL0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_IFL)
#define MCF_IRQ_BOFF0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_BOFF)
#define MCF_IRQ_ERR0 (MCFINT1_VECBASE + MCFINT1_FLEXCAN0_ERR)
#define MCF_IRQ_IFL1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_IFL)
#define MCF_IRQ_BOFF1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_BOFF)
#define MCF_IRQ_ERR1 (MCFINT1_VECBASE + MCFINT1_FLEXCAN1_ERR)
#endif /* m5441xsim_h */