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scsi: mpt3sas: Determine smp affinity on per HBA basis
Even though 'smp_affinity_enable' module parameter is enabled, if the number of online CPUs is bigger than the number of msix vectors enabled on that HBA, then smp affinity settings should be disabled only for this HBA. But currently the smp affinity setting is disabled globally and hence smp affinity will be disabled for subsequent HBAs even though number of msix vectors enabled for this HBA matches the number of online CPU. To fix this, define a per HBA variable smp_affinity_enable. Initially this variable is initialized with smp_affinity_enable module parameter value. If this HBA has less number of msix vectors configured when compared to number of online cpus, then only this HBA's variable smp_affinity_enable is set to zero. Signed-off-by: Sreekanth Reddy <sreekanth.reddy@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
This commit is contained in:
parent
48d6f0a6a5
commit
610ef1e955
2 changed files with 7 additions and 4 deletions
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@ -2813,7 +2813,7 @@ _base_free_irq(struct MPT3SAS_ADAPTER *ioc)
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list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
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list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
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list_del(&reply_q->list);
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list_del(&reply_q->list);
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if (smp_affinity_enable)
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if (ioc->smp_affinity_enable)
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irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
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irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
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reply_q->msix_index), NULL);
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reply_q->msix_index), NULL);
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free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
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free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
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@ -2898,7 +2898,7 @@ _base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
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if (!nr_msix)
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if (!nr_msix)
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return;
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return;
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if (smp_affinity_enable) {
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if (ioc->smp_affinity_enable) {
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/*
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/*
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* set irq affinity to local numa node for those irqs
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* set irq affinity to local numa node for those irqs
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@ -3033,7 +3033,7 @@ _base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
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struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
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struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
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struct irq_affinity *descp = &desc;
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struct irq_affinity *descp = &desc;
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if (smp_affinity_enable)
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if (ioc->smp_affinity_enable)
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irq_flags |= PCI_IRQ_AFFINITY;
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irq_flags |= PCI_IRQ_AFFINITY;
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else
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else
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descp = NULL;
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descp = NULL;
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@ -3091,7 +3091,7 @@ _base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
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goto try_ioapic;
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goto try_ioapic;
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if (ioc->msix_vector_count < ioc->cpu_count)
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if (ioc->msix_vector_count < ioc->cpu_count)
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smp_affinity_enable = 0;
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ioc->smp_affinity_enable = 0;
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r = _base_alloc_irq_vectors(ioc);
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r = _base_alloc_irq_vectors(ioc);
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if (r < 0) {
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if (r < 0) {
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@ -6897,6 +6897,8 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
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}
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}
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}
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}
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ioc->smp_affinity_enable = smp_affinity_enable;
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ioc->rdpq_array_enable_assigned = 0;
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ioc->rdpq_array_enable_assigned = 0;
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ioc->dma_mask = 0;
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ioc->dma_mask = 0;
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if (ioc->is_aero_ioc)
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if (ioc->is_aero_ioc)
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@ -1405,6 +1405,7 @@ struct MPT3SAS_ADAPTER {
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u8 combined_reply_queue;
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u8 combined_reply_queue;
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u8 combined_reply_index_count;
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u8 combined_reply_index_count;
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u8 smp_affinity_enable;
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/* reply post register index */
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/* reply post register index */
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resource_size_t **replyPostRegisterIndex;
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resource_size_t **replyPostRegisterIndex;
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