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brcm80211: fmac: replace private SB macros with ssb_regs version
Use SSB macros in order to clean up brcmfmac code Reviewed-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Franky Lin
John W. Linville
parent
e12afb6c5d
commit
61213be4cc
2 changed files with 28 additions and 63 deletions
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@ -18,6 +18,8 @@
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#include <linux/types.h>
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#include <linux/netdevice.h>
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#include <linux/mmc/card.h>
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#include <linux/ssb/ssb_regs.h>
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#include <chipcommon.h>
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#include <brcm_hw_ids.h>
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#include <brcmu_wifi.h>
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@ -38,19 +40,9 @@
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#define BCM4329_CORE_ARM_BASE 0x18002000
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#define BCM4329_RAMSIZE 0x48000
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/* SB regs */
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/* sbidhigh */
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#define SBIDH_RC_MASK 0x000f /* revision code */
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#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
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#define SBIDH_RCE_SHIFT 8
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#define SBCOREREV(sbidh) \
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((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | \
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((sbidh) & SBIDH_RC_MASK))
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#define SBIDH_CC_MASK 0x8ff0 /* core code */
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#define SBIDH_CC_SHIFT 4
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#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
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#define SBIDH_VC_SHIFT 16
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((((sbidh) & SSB_IDHIGH_RCHI) >> SSB_IDHIGH_RCHI_SHIFT) | \
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((sbidh) & SSB_IDHIGH_RCLO))
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#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
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/* SDIO Pad drive strength to select value mappings */
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@ -109,9 +101,9 @@ brcmf_sdio_chip_iscoreup(struct brcmf_sdio_dev *sdiodev,
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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regdata &= (SBTML_RESET | SBTML_REJ_MASK |
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(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
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return ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) == regdata);
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regdata &= (SSB_TMSLOW_RESET | SSB_TMSLOW_REJECT |
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SSB_IMSTATE_REJECT | SSB_TMSLOW_CLOCK);
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return (SSB_TMSLOW_CLOCK == regdata);
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}
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void
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@ -121,12 +113,12 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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if (regdata & SBTML_RESET)
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if (regdata & SSB_TMSLOW_RESET)
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return;
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
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if ((regdata & SSB_TMSLOW_CLOCK) != 0) {
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/*
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* set target reject and spin until busy is clear
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* (preserve core-specific bits)
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@ -134,26 +126,26 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
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4, regdata | SBTML_REJ);
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4, regdata | SSB_TMSLOW_REJECT);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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udelay(1);
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SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatehigh), 4) &
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SBTMH_BUSY), 100000);
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SSB_TMSHIGH_BUSY), 100000);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatehigh), 4);
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if (regdata & SBTMH_BUSY)
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if (regdata & SSB_TMSHIGH_BUSY)
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brcmf_dbg(ERROR, "core state still busy\n");
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbidlow), 4);
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if (regdata & SBIDL_INIT) {
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if (regdata & SSB_IDLOW_INITIATOR) {
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbimstate), 4) |
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SBIM_RJ;
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SSB_IMSTATE_REJECT;
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brcmf_sdcard_reg_write(sdiodev,
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CORE_SB(corebase, sbimstate), 4,
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regdata);
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@ -162,14 +154,14 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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udelay(1);
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SPINWAIT((brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbimstate), 4) &
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SBIM_BY), 100000);
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SSB_IMSTATE_BUSY), 100000);
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}
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/* set reset and reject while enabling the clocks */
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brcmf_sdcard_reg_write(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4,
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(((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
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SBTML_REJ | SBTML_RESET));
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(SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
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SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatelow), 4);
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udelay(10);
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@ -177,10 +169,10 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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/* clear the initiator reject bit */
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbidlow), 4);
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if (regdata & SBIDL_INIT) {
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if (regdata & SSB_IDLOW_INITIATOR) {
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbimstate), 4) &
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~SBIM_RJ;
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~SSB_IMSTATE_REJECT;
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brcmf_sdcard_reg_write(sdiodev,
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CORE_SB(corebase, sbimstate), 4,
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regdata);
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@ -189,7 +181,7 @@ brcmf_sdio_chip_coredisable(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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/* leave reset and reject asserted */
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
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(SBTML_REJ | SBTML_RESET));
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(SSB_TMSLOW_REJECT | SSB_TMSLOW_RESET));
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udelay(1);
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}
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@ -210,31 +202,29 @@ brcmf_sdio_chip_resetcore(struct brcmf_sdio_dev *sdiodev, u32 corebase)
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* forcing them on throughout the core
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*/
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
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((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
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SBTML_RESET);
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SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET);
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udelay(1);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbtmstatehigh), 4);
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if (regdata & SBTMH_SERR)
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if (regdata & SSB_TMSHIGH_SERR)
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brcmf_sdcard_reg_write(sdiodev,
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CORE_SB(corebase, sbtmstatehigh), 4, 0);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(corebase, sbimstate), 4);
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if (regdata & (SBIM_IBE | SBIM_TO))
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if (regdata & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO))
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbimstate), 4,
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regdata & ~(SBIM_IBE | SBIM_TO));
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regdata & ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO));
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/* clear reset and allow it to propagate throughout the core */
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
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(SICF_FGC << SBTML_SICF_SHIFT) |
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(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
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SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK);
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udelay(1);
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/* leave clock enabled */
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow), 4,
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(SICF_CLOCK_EN << SBTML_SICF_SHIFT));
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brcmf_sdcard_reg_write(sdiodev, CORE_SB(corebase, sbtmstatelow),
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4, SSB_TMSLOW_CLOCK);
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udelay(1);
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}
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@ -345,7 +335,7 @@ brcmf_sdio_chip_buscoresetup(struct brcmf_sdio_dev *sdiodev,
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ci->buscorerev = brcmf_sdio_chip_corerev(sdiodev, ci->buscorebase);
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regdata = brcmf_sdcard_reg_read(sdiodev,
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CORE_SB(ci->buscorebase, sbidhigh), 4);
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ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
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ci->buscoretype = (regdata & SSB_IDHIGH_CC) >> SSB_IDHIGH_CC_SHIFT;
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brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
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ci->ccrev, ci->pmurev, ci->buscorerev, ci->buscoretype);
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@ -52,31 +52,6 @@
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#define SBSDIO_CLKAV(regval, alponly) \
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(SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
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/* sbimstate */
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#define SBIM_IBE 0x20000 /* inbanderror */
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#define SBIM_TO 0x40000 /* timeout */
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#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
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#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
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/* sbtmstatelow */
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#define SBTML_RESET 0x0001 /* reset */
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#define SBTML_REJ_MASK 0x0006 /* reject field */
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#define SBTML_REJ 0x0002 /* reject */
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#define SBTML_TMPREJ 0x0004 /* temporary reject(error recovery) */
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/* Shift to locate the SI control flags in sbtml */
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#define SBTML_SICF_SHIFT 16
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/* sbtmstatehigh */
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#define SBTMH_SERR 0x0001 /* serror */
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#define SBTMH_INT 0x0002 /* interrupt */
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#define SBTMH_BUSY 0x0004 /* busy */
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#define SBTMH_TO 0x0020 /* timeout (sonics >= 2.3) */
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/* Shift to locate the SI status flags in sbtmh */
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#define SBTMH_SISF_SHIFT 16
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/* sbidlow */
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#define SBIDL_INIT 0x80 /* initiator */
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struct chip_info {
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u32 chip;
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u32 chiprev;
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