spi: qup: Add DMA capabilities
This patch adds DMA capabilities to the spi-qup driver. If DMA channels are present, the QUP will use DMA instead of block mode for transfers to/from SPI peripherals for transactions larger than the length of a block. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org> Reviewed-by: Ivan T. Ivanov <iivanov@mm-sol.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Andy Gross
Mark Brown
parent
c517d838eb
commit
612762e82a
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@ -33,6 +33,11 @@ Optional properties:
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nodes. If unspecified, a single SPI device without a chip
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select can be used.
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- dmas: Two DMA channel specifiers following the convention outlined
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in bindings/dma/dma.txt
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- dma-names: Names for the dma channels, if present. There must be at
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least one channel named "tx" for transmit and named "rx" for
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receive.
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SPI slave nodes must be children of the SPI master node and can contain
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properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
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@ -51,6 +56,9 @@ Example:
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clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
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clock-names = "core", "iface";
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dmas = <&blsp1_bam 13>, <&blsp1_bam 12>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&spi8_default>;
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@ -22,6 +22,8 @@
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/spi.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#define QUP_CONFIG 0x0000
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#define QUP_STATE 0x0004
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@ -116,6 +118,8 @@
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#define SPI_NUM_CHIPSELECTS 4
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#define SPI_MAX_DMA_XFER (SZ_64K - 64)
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/* high speed mode is when bus rate is greater then 26MHz */
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#define SPI_HS_MIN_RATE 26000000
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#define SPI_MAX_RATE 50000000
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@ -140,9 +144,14 @@ struct spi_qup {
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struct completion done;
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int error;
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int w_size; /* bytes per SPI word */
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int n_words;
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int tx_bytes;
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int rx_bytes;
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int qup_v1;
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int use_dma;
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struct dma_slave_config rx_conf;
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struct dma_slave_config tx_conf;
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};
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@ -198,7 +207,6 @@ static int spi_qup_set_state(struct spi_qup *controller, u32 state)
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return 0;
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}
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static void spi_qup_fifo_read(struct spi_qup *controller,
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struct spi_transfer *xfer)
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{
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@ -266,6 +274,107 @@ static void spi_qup_fifo_write(struct spi_qup *controller,
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}
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}
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static void spi_qup_dma_done(void *data)
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{
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struct spi_qup *qup = data;
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complete(&qup->done);
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}
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static int spi_qup_prep_sg(struct spi_master *master, struct spi_transfer *xfer,
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enum dma_transfer_direction dir,
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dma_async_tx_callback callback)
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{
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struct spi_qup *qup = spi_master_get_devdata(master);
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unsigned long flags = DMA_PREP_INTERRUPT | DMA_PREP_FENCE;
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struct dma_async_tx_descriptor *desc;
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struct scatterlist *sgl;
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struct dma_chan *chan;
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dma_cookie_t cookie;
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unsigned int nents;
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if (dir == DMA_MEM_TO_DEV) {
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chan = master->dma_tx;
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nents = xfer->tx_sg.nents;
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sgl = xfer->tx_sg.sgl;
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} else {
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chan = master->dma_rx;
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nents = xfer->rx_sg.nents;
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sgl = xfer->rx_sg.sgl;
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}
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desc = dmaengine_prep_slave_sg(chan, sgl, nents, dir, flags);
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if (!desc)
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return -EINVAL;
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desc->callback = callback;
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desc->callback_param = qup;
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cookie = dmaengine_submit(desc);
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return dma_submit_error(cookie);
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}
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static void spi_qup_dma_terminate(struct spi_master *master,
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struct spi_transfer *xfer)
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{
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if (xfer->tx_buf)
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dmaengine_terminate_all(master->dma_tx);
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if (xfer->rx_buf)
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dmaengine_terminate_all(master->dma_rx);
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}
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static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer)
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{
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dma_async_tx_callback rx_done = NULL, tx_done = NULL;
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int ret;
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if (xfer->rx_buf)
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rx_done = spi_qup_dma_done;
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else if (xfer->tx_buf)
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tx_done = spi_qup_dma_done;
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if (xfer->rx_buf) {
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ret = spi_qup_prep_sg(master, xfer, DMA_DEV_TO_MEM, rx_done);
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if (ret)
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return ret;
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dma_async_issue_pending(master->dma_rx);
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}
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if (xfer->tx_buf) {
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ret = spi_qup_prep_sg(master, xfer, DMA_MEM_TO_DEV, tx_done);
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if (ret)
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return ret;
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dma_async_issue_pending(master->dma_tx);
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}
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return 0;
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}
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static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer)
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{
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struct spi_qup *qup = spi_master_get_devdata(master);
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int ret;
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ret = spi_qup_set_state(qup, QUP_STATE_RUN);
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if (ret) {
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dev_warn(qup->dev, "cannot set RUN state\n");
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return ret;
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}
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ret = spi_qup_set_state(qup, QUP_STATE_PAUSE);
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if (ret) {
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dev_warn(qup->dev, "cannot set PAUSE state\n");
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return ret;
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}
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spi_qup_fifo_write(qup, xfer);
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return 0;
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}
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static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
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{
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struct spi_qup *controller = dev_id;
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@ -315,11 +424,13 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
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error = -EIO;
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}
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if (opflags & QUP_OP_IN_SERVICE_FLAG)
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spi_qup_fifo_read(controller, xfer);
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if (!controller->use_dma) {
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if (opflags & QUP_OP_IN_SERVICE_FLAG)
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spi_qup_fifo_read(controller, xfer);
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if (opflags & QUP_OP_OUT_SERVICE_FLAG)
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spi_qup_fifo_write(controller, xfer);
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if (opflags & QUP_OP_OUT_SERVICE_FLAG)
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spi_qup_fifo_write(controller, xfer);
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}
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spin_lock_irqsave(&controller->lock, flags);
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controller->error = error;
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@ -332,13 +443,35 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
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return IRQ_HANDLED;
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}
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static u32
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spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer)
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{
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struct spi_qup *qup = spi_master_get_devdata(master);
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u32 mode;
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qup->w_size = 4;
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if (xfer->bits_per_word <= 8)
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qup->w_size = 1;
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else if (xfer->bits_per_word <= 16)
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qup->w_size = 2;
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qup->n_words = xfer->len / qup->w_size;
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if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
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mode = QUP_IO_M_MODE_FIFO;
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else
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mode = QUP_IO_M_MODE_BLOCK;
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return mode;
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}
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/* set clock freq ... bits per word */
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static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
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{
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struct spi_qup *controller = spi_master_get_devdata(spi->master);
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u32 config, iomode, mode, control;
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int ret, n_words, w_size;
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int ret, n_words;
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if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
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dev_err(controller->dev, "too big size for loopback %d > %d\n",
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@ -358,35 +491,54 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
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return -EIO;
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}
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w_size = 4;
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if (xfer->bits_per_word <= 8)
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w_size = 1;
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else if (xfer->bits_per_word <= 16)
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w_size = 2;
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mode = spi_qup_get_mode(spi->master, xfer);
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n_words = controller->n_words;
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n_words = xfer->len / w_size;
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controller->w_size = w_size;
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if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
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mode = QUP_IO_M_MODE_FIFO;
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if (mode == QUP_IO_M_MODE_FIFO) {
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writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
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writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
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/* must be zero for FIFO */
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writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
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writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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} else {
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mode = QUP_IO_M_MODE_BLOCK;
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} else if (!controller->use_dma) {
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writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
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writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
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/* must be zero for BLOCK and BAM */
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writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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} else {
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mode = QUP_IO_M_MODE_BAM;
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writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
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writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
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if (!controller->qup_v1) {
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void __iomem *input_cnt;
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input_cnt = controller->base + QUP_MX_INPUT_CNT;
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/*
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* for DMA transfers, both QUP_MX_INPUT_CNT and
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* QUP_MX_OUTPUT_CNT must be zero to all cases but one.
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* That case is a non-balanced transfer when there is
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* only a rx_buf.
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*/
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if (xfer->tx_buf)
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writel_relaxed(0, input_cnt);
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else
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writel_relaxed(n_words, input_cnt);
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writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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}
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}
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iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
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/* Set input and output transfer mode */
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iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
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iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
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if (!controller->use_dma)
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iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
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else
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iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
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iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
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iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
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@ -428,11 +580,31 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
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config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
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config |= xfer->bits_per_word - 1;
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config |= QUP_CONFIG_SPI_MODE;
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if (controller->use_dma) {
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if (!xfer->tx_buf)
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config |= QUP_CONFIG_NO_OUTPUT;
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if (!xfer->rx_buf)
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config |= QUP_CONFIG_NO_INPUT;
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}
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writel_relaxed(config, controller->base + QUP_CONFIG);
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/* only write to OPERATIONAL_MASK when register is present */
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if (!controller->qup_v1)
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writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
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if (!controller->qup_v1) {
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u32 mask = 0;
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/*
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* mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
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* status change in BAM mode
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*/
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if (mode == QUP_IO_M_MODE_BAM)
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mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
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writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
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}
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return 0;
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}
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@ -461,17 +633,13 @@ static int spi_qup_transfer_one(struct spi_master *master,
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controller->tx_bytes = 0;
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spin_unlock_irqrestore(&controller->lock, flags);
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if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
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dev_warn(controller->dev, "cannot set RUN state\n");
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goto exit;
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}
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if (controller->use_dma)
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ret = spi_qup_do_dma(master, xfer);
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else
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ret = spi_qup_do_pio(master, xfer);
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if (spi_qup_set_state(controller, QUP_STATE_PAUSE)) {
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dev_warn(controller->dev, "cannot set PAUSE state\n");
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if (ret)
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goto exit;
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}
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spi_qup_fifo_write(controller, xfer);
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if (spi_qup_set_state(controller, QUP_STATE_RUN)) {
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dev_warn(controller->dev, "cannot set EXECUTE state\n");
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@ -480,6 +648,7 @@ static int spi_qup_transfer_one(struct spi_master *master,
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if (!wait_for_completion_timeout(&controller->done, timeout))
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ret = -ETIMEDOUT;
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exit:
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spi_qup_set_state(controller, QUP_STATE_RESET);
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spin_lock_irqsave(&controller->lock, flags);
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@ -487,6 +656,97 @@ exit:
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if (!ret)
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ret = controller->error;
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spin_unlock_irqrestore(&controller->lock, flags);
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if (ret && controller->use_dma)
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spi_qup_dma_terminate(master, xfer);
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return ret;
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}
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static bool spi_qup_can_dma(struct spi_master *master, struct spi_device *spi,
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struct spi_transfer *xfer)
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{
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struct spi_qup *qup = spi_master_get_devdata(master);
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size_t dma_align = dma_get_cache_alignment();
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u32 mode;
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qup->use_dma = 0;
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if (xfer->rx_buf && (xfer->len % qup->in_blk_sz ||
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IS_ERR_OR_NULL(master->dma_rx) ||
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!IS_ALIGNED((size_t)xfer->rx_buf, dma_align)))
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return false;
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if (xfer->tx_buf && (xfer->len % qup->out_blk_sz ||
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IS_ERR_OR_NULL(master->dma_tx) ||
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!IS_ALIGNED((size_t)xfer->tx_buf, dma_align)))
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return false;
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mode = spi_qup_get_mode(master, xfer);
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if (mode == QUP_IO_M_MODE_FIFO)
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return false;
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qup->use_dma = 1;
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return true;
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}
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static void spi_qup_release_dma(struct spi_master *master)
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{
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if (!IS_ERR_OR_NULL(master->dma_rx))
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dma_release_channel(master->dma_rx);
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if (!IS_ERR_OR_NULL(master->dma_tx))
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dma_release_channel(master->dma_tx);
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}
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static int spi_qup_init_dma(struct spi_master *master, resource_size_t base)
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{
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struct spi_qup *spi = spi_master_get_devdata(master);
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struct dma_slave_config *rx_conf = &spi->rx_conf,
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*tx_conf = &spi->tx_conf;
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struct device *dev = spi->dev;
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int ret;
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/* allocate dma resources, if available */
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master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
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if (IS_ERR(master->dma_rx))
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return PTR_ERR(master->dma_rx);
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master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
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if (IS_ERR(master->dma_tx)) {
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ret = PTR_ERR(master->dma_tx);
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goto err_tx;
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}
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/* set DMA parameters */
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rx_conf->direction = DMA_DEV_TO_MEM;
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rx_conf->device_fc = 1;
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rx_conf->src_addr = base + QUP_INPUT_FIFO;
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rx_conf->src_maxburst = spi->in_blk_sz;
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tx_conf->direction = DMA_MEM_TO_DEV;
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tx_conf->device_fc = 1;
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tx_conf->dst_addr = base + QUP_OUTPUT_FIFO;
|
||||
tx_conf->dst_maxburst = spi->out_blk_sz;
|
||||
|
||||
ret = dmaengine_slave_config(master->dma_rx, rx_conf);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to configure RX channel\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
ret = dmaengine_slave_config(master->dma_tx, tx_conf);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to configure TX channel\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
dma_release_channel(master->dma_tx);
|
||||
err_tx:
|
||||
dma_release_channel(master->dma_rx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -562,6 +822,8 @@ static int spi_qup_probe(struct platform_device *pdev)
|
|||
master->transfer_one = spi_qup_transfer_one;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->auto_runtime_pm = true;
|
||||
master->dma_alignment = dma_get_cache_alignment();
|
||||
master->max_dma_len = SPI_MAX_DMA_XFER;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
|
|
@ -573,6 +835,12 @@ static int spi_qup_probe(struct platform_device *pdev)
|
|||
controller->cclk = cclk;
|
||||
controller->irq = irq;
|
||||
|
||||
ret = spi_qup_init_dma(master, res->start);
|
||||
if (ret == -EPROBE_DEFER)
|
||||
goto error;
|
||||
else if (!ret)
|
||||
master->can_dma = spi_qup_can_dma;
|
||||
|
||||
/* set v1 flag if device is version 1 */
|
||||
if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
|
||||
controller->qup_v1 = 1;
|
||||
|
|
@ -609,7 +877,7 @@ static int spi_qup_probe(struct platform_device *pdev)
|
|||
ret = spi_qup_set_state(controller, QUP_STATE_RESET);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot set RESET state\n");
|
||||
goto error;
|
||||
goto error_dma;
|
||||
}
|
||||
|
||||
writel_relaxed(0, base + QUP_OPERATIONAL);
|
||||
|
|
@ -633,7 +901,7 @@ static int spi_qup_probe(struct platform_device *pdev)
|
|||
ret = devm_request_irq(dev, irq, spi_qup_qup_irq,
|
||||
IRQF_TRIGGER_HIGH, pdev->name, controller);
|
||||
if (ret)
|
||||
goto error;
|
||||
goto error_dma;
|
||||
|
||||
pm_runtime_set_autosuspend_delay(dev, MSEC_PER_SEC);
|
||||
pm_runtime_use_autosuspend(dev);
|
||||
|
|
@ -648,6 +916,8 @@ static int spi_qup_probe(struct platform_device *pdev)
|
|||
|
||||
disable_pm:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
error_dma:
|
||||
spi_qup_release_dma(master);
|
||||
error:
|
||||
clk_disable_unprepare(cclk);
|
||||
clk_disable_unprepare(iclk);
|
||||
|
|
@ -739,6 +1009,8 @@ static int spi_qup_remove(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
spi_qup_release_dma(master);
|
||||
|
||||
clk_disable_unprepare(controller->cclk);
|
||||
clk_disable_unprepare(controller->iclk);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue