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Code Issues Releases Wiki Activity

- Core Frameworks 

- Change maintainer email address
    - Use acpi_dev_for_each_child() helper to walk the ACPI list
 
  - New Device Support
    - Add support for BCM2711 RPiVid ASB to Broadcom BCM2835
    - Add support for MT8195 dual-core RISC-V MCU to Chrome OS Embedded Controller
    - Add support for Regulator, RTC and Keys to MediaTek MT6357 PMIC
    - Add support for GPIO to X-Powers AXP20x PMIC
    - Add support for MT6331 and MT6332 to MediaTek MT6357 PMIC
    - Add support for Intel Meteor Lake-P PCI to Intel LPSS PCI
 
  - New Functionality
    - Add support for non-ACPI platforms; lpc_ich
 
  - Fix-ups
    - Use platform data instead of hard-coded values; bcm2835-pm
    - Make use of BIT/GENMASK macros; intel_soc_pmic_bxtwc
    - Use dev_err_probe() helper; intel_soc_pmic_chtwc, intel_soc_pmic_bxtwc
    - Use provided generic APIs / helpers; lpc_ich
    - Clean-up .remove() return values; asic3, t7l66xb, tc6387xb, tc6393xb
    - Use correct formatting specifiers; syscon
    - Replace sprintf() with sysfs_emit(); intel_soc_pmic_bxtwc
    - Automatically detect and fill USB endpoint pointers; dln2
    - Use more appropriate dev/platform/spi resources APIs; intel_soc_pmic_bxtwc
    - Make use of pm_sleep_ptr(); intel_soc_pmic_chtwc, intel_soc_pmic_bxtwc
    - Improve error handling; intel_soc_pmic_bxtwc
    - Use core driver API to create groups; intel_soc_pmic_bxtwc
    - Kconfig fix-ups; MFD_SUN6I_PRCM
    - Admin: whitespace/email addresses/etc; max77714, db8500-prcmu, ipaq-micro,
 			intel_soc_pmic_bxtwc
    - Remove duplicate/unused code/functionality; lpc_ich, twl-core, qcom-pm8008,
 			intel_soc_pmic_bxtwc
    - DT fix-ups / conversions; da9063, ti,j721e-system-controller, st,stm32-timers,
 			mt6397, qcom,tcsr, mps,mp2629, qcom-pm8xxx, fsl,imx8qxp-csr
 
  - Bug Fixes
    - Fix of_node reference leak; max77620
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Merge tag 'mfd-next-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "Core Framework:
   - Change maintainer email address
   - Use acpi_dev_for_each_child() helper to walk the ACPI list

  New Device Support:
   - BCM2711 RPiVid ASB in Broadcom BCM2835
   - MT8195 dual-core RISC-V MCU in Chrome OS Embedded Controller
   - Regulator, RTC and Keys in MediaTek MT6357 PMIC
   - GPIO in X-Powers AXP20x PMIC
   - MT6331 and MT6332 in MediaTek MT6357 PMIC
   - Intel Meteor Lake-P PCI in Intel LPSS PCI

  New Functionality:
   - Add support for non-ACPI platforms; lpc_ich

  Fix-ups:
   - Use platform data instead of hard-coded values; bcm2835-pm
   - Make use of BIT/GENMASK macros; intel_soc_pmic_bxtwc
   - Use dev_err_probe() helper; intel_soc_pmic_chtwc,
     intel_soc_pmic_bxtwc
   - Use provided generic APIs / helpers; lpc_ich
   - Clean-up .remove() return values; asic3, t7l66xb, tc6387xb,
     tc6393xb
   - Use correct formatting specifiers; syscon
   - Replace sprintf() with sysfs_emit(); intel_soc_pmic_bxtwc
   - Automatically detect and fill USB endpoint pointers; dln2
   - Use more appropriate dev/platform/spi resources APIs;
     intel_soc_pmic_bxtwc
   - Make use of pm_sleep_ptr(); intel_soc_pmic_chtwc,
     intel_soc_pmic_bxtwc
   - Improve error handling; intel_soc_pmic_bxtwc
   - Use core driver API to create groups; intel_soc_pmic_bxtwc
   - Kconfig fix-ups; MFD_SUN6I_PRCM
   - Admin: whitespace/email addresses/etc; max77714, db8500-prcmu,
     ipaq-micro, intel_soc_pmic_bxtwc
   - Remove duplicate/unused code/functionality; lpc_ich, twl-core,
     qcom-pm8008, intel_soc_pmic_bxtwc
   - DT fix-ups / conversions; da9063, ti,j721e-system-controller,
     st,stm32-timers, mt6397, qcom,tcsr, mps,mp2629, qcom-pm8xxx,
     fsl,imx8qxp-csr

  Bug Fixes:
   - Fix of_node reference leak; max77620"

* tag 'mfd-next-5.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (49 commits)
  dt-bindings: mfd: stm32-timers: Move fixed string node names under 'properties'
  dt-bindings: mfd: st,stm32-timers: Correct 'resets' property name
  dt-bindings: mfd: syscon: Update Lee Jones' email address
  MAINTAINERS: Use Lee Jones' kernel.org address for Syscon submissions
  MAINTAINERS: Use Lee Jones' kernel.org address for MFD submissions
  mfd: sun6i-prcm: Update Kconfig description
  mfd: intel_soc_pmic_bxtwc: Fix spelling in the comment
  mfd: intel_soc_pmic_bxtwc: Drop unneeded casting
  mfd: intel_soc_pmic_bxtwc: Use sysfs_emit() instead of sprintf()
  mfd: intel_soc_pmic_bxtwc: Use bits.h macros for all masks
  mfd: intel_soc_pmic_bxtwc: Drop redundant ACPI_PTR()
  mfd: intel_soc_pmic_bxtwc: Switch from CONFIG_PM_SLEEP guards to pm_sleep_ptr() etc
  mfd: intel_soc_pmic_bxtwc: Extend use of temporary variable for struct device
  mfd: intel_soc_pmic_bxtwc: Use dev_err_probe()
  mfd: intel_soc_pmic_bxtwc: Convert to use platform_get/set_drvdata()
  mfd: intel_soc_pmic_bxtwc: Create sysfs attributes using core driver's facility
  mfd: intel_soc_pmic_bxtwc: Don't shadow error codes in show()/store()
  mfd: intel-lpss: Add Intel Meteor Lake-P PCI IDs
  mfd: mt6397: Add basic support for MT6331+MT6332 PMIC
  mfd: axp20x: Add AXP221/AXP223/AXP809 GPIO cells
  ...
This commit is contained in:
Linus Torvalds 2022-08-06 10:25:16 -07:00
parent 668c3c237f ae4ccaed3a
commit 613b2a82f2
49 changed files with 3569 additions and 766 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

114
Documentation/devicetree/bindings/mfd/da9063.txt
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@ -1,114 +0,0 @@
* Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC)
DA9063 consists of a large and varied group of sub-devices (I2C Only):
Device Supply Names Description
------ ------------ -----------
da9063-regulator : : LDOs & BUCKs
da9063-onkey : : On Key
da9063-rtc : : Real-Time Clock (DA9063 only)
da9063-watchdog : : Watchdog
======
Required properties:
- compatible : Should be "dlg,da9063" or "dlg,da9063l"
- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
modified to match the chip's OTP settings).
- interrupts : IRQ line information.
- interrupt-controller
Sub-nodes:
- regulators : This node defines the settings for the LDOs and BUCKs.
The DA9063(L) regulators are bound using their names listed below:
bcore1 : BUCK CORE1
bcore2 : BUCK CORE2
bpro : BUCK PRO
bmem : BUCK MEM
bio : BUCK IO
bperi : BUCK PERI
ldo1 : LDO_1 (DA9063 only)
ldo2 : LDO_2 (DA9063 only)
ldo3 : LDO_3
ldo4 : LDO_4 (DA9063 only)
ldo5 : LDO_5 (DA9063 only)
ldo6 : LDO_6 (DA9063 only)
ldo7 : LDO_7
ldo8 : LDO_8
ldo9 : LDO_9
ldo10 : LDO_10 (DA9063 only)
ldo11 : LDO_11
The component follows the standard regulator framework and the bindings
details of individual regulator device can be found in:
Documentation/devicetree/bindings/regulator/regulator.txt
- rtc : This node defines settings for the Real-Time Clock associated with
the DA9063 only. The RTC is not present in DA9063L. There are currently
no entries in this binding, however compatible = "dlg,da9063-rtc" should
be added if a node is created.
- onkey : This node defines the OnKey settings for controlling the key
functionality of the device. The node should contain the compatible property
with the value "dlg,da9063-onkey".
Optional onkey properties:
- dlg,disable-key-power : Disable power-down using a long key-press. If this
entry exists the OnKey driver will remove support for the KEY_POWER key
press. If this entry does not exist then by default the key-press
triggered power down is enabled and the OnKey will support both KEY_POWER
and KEY_SLEEP.
- watchdog : This node defines settings for the Watchdog timer associated
with the DA9063 and DA9063L. The node should contain the compatible property
with the value "dlg,da9063-watchdog".
Optional watchdog properties:
- dlg,use-sw-pm: Add this property to disable the watchdog during suspend.
Only use this option if you can't use the watchdog automatic suspend
function during a suspend (see register CONTROL_B).
Example:
pmic0: da9063@58 {
compatible = "dlg,da9063"
reg = <0x58>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
rtc {
compatible = "dlg,da9063-rtc";
};
wdt {
compatible = "dlg,da9063-watchdog";
};
onkey {
compatible = "dlg,da9063-onkey";
dlg,disable-key-power;
};
regulators {
DA9063_BCORE1: bcore1 {
regulator-name = "BCORE1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-min-microamp = <500000>;
regulator-max-microamp = <2000000>;
regulator-boot-on;
};
DA9063_LDO11: ldo11 {
regulator-name = "LDO_11";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
};
};
};

132
Documentation/devicetree/bindings/mfd/dlg,da9063.yaml Normal file
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@ -0,0 +1,132 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/dlg,da9063.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Dialog DA9063/DA9063L Power Management Integrated Circuit (PMIC)
maintainers:
- Steve Twiss <stwiss.opensource@diasemi.com>
description: |
For device-tree bindings of other sub-modules refer to the binding documents
under the respective sub-system directories.
properties:
compatible:
enum:
- dlg,da9063
- dlg,da9063l
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 2
dlg,use-sw-pm:
type: boolean
description:
Disable the watchdog during suspend.
Only use this option if you can't use the watchdog automatic suspend
function during a suspend (see register CONTROL_B).
watchdog:
type: object
$ref: /schemas/watchdog/watchdog.yaml#
unevaluatedProperties: false
properties:
compatible:
const: dlg,da9063-watchdog
rtc:
type: object
$ref: /schemas/rtc/rtc.yaml#
unevaluatedProperties: false
properties:
compatible:
const: dlg,da9063-rtc
onkey:
type: object
$ref: /schemas/input/input.yaml#
unevaluatedProperties: false
properties:
compatible:
const: dlg,da9063-onkey
dlg,disable-key-power:
type: boolean
description: |
Disable power-down using a long key-press.
If this entry does not exist then by default the key-press triggered
power down is enabled and the OnKey will support both KEY_POWER and
KEY_SLEEP.
regulators:
type: object
patternProperties:
"^(ldo[1-11]|bcore[1-2]|bpro|bmem|bio|bperi)$":
$ref: /schemas/regulator/regulator.yaml
unevaluatedProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic@58 {
compatible = "dlg,da9063";
reg = <0x58>;
#interrupt-cells = <2>;
interrupt-parent = <&gpio6>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
rtc {
compatible = "dlg,da9063-rtc";
};
watchdog {
compatible = "dlg,da9063-watchdog";
};
onkey {
compatible = "dlg,da9063-onkey";
dlg,disable-key-power;
};
regulators {
regulator-bcore1 {
regulator-name = "BCORE1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1570000>;
regulator-min-microamp = <500000>;
regulator-max-microamp = <2000000>;
regulator-boot-on;
};
regulator-ldo11 {
regulator-name = "LDO_11";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3600000>;
regulator-boot-on;
};
};
};
};
...

4
Documentation/devicetree/bindings/mfd/mps,mp2629.yaml
View File

@ -18,7 +18,9 @@ description: |
properties: properties:
compatible: compatible:
const: mps,mp2629 enum:
- mps,mp2629
- mps,mp2733
reg: reg:
maxItems: 1 maxItems: 1

8
Documentation/devicetree/bindings/mfd/mt6397.txt
View File

@ -20,6 +20,7 @@ This document describes the binding for MFD device and its sub module.
Required properties: Required properties:
compatible: compatible:
"mediatek,mt6323" for PMIC MT6323 "mediatek,mt6323" for PMIC MT6323
"mediatek,mt6331" for PMIC MT6331 and MT6332
"mediatek,mt6358" for PMIC MT6358 and MT6366 "mediatek,mt6358" for PMIC MT6358 and MT6366
"mediatek,mt6359" for PMIC MT6359 "mediatek,mt6359" for PMIC MT6359
"mediatek,mt6397" for PMIC MT6397 "mediatek,mt6397" for PMIC MT6397
@ -29,6 +30,7 @@ Optional subnodes:
- rtc - rtc
Required properties: Should be one of follows Required properties: Should be one of follows
- compatible: "mediatek,mt6323-rtc" - compatible: "mediatek,mt6323-rtc"
- compatible: "mediatek,mt6331-rtc"
- compatible: "mediatek,mt6358-rtc" - compatible: "mediatek,mt6358-rtc"
- compatible: "mediatek,mt6397-rtc" - compatible: "mediatek,mt6397-rtc"
For details, see ../rtc/rtc-mt6397.txt For details, see ../rtc/rtc-mt6397.txt
@ -52,8 +54,10 @@ Optional subnodes:
see ../leds/leds-mt6323.txt see ../leds/leds-mt6323.txt
- keys - keys
Required properties: Required properties: Should be one of the following
- compatible: "mediatek,mt6397-keys" or "mediatek,mt6323-keys" - compatible: "mediatek,mt6323-keys"
- compatible: "mediatek,mt6331-keys"
- compatible: "mediatek,mt6397-keys"
see ../input/mtk-pmic-keys.txt see ../input/mtk-pmic-keys.txt
- power-controller - power-controller

24
Documentation/devicetree/bindings/mfd/qcom,tcsr.txt
View File

@ -1,24 +0,0 @@
QCOM Top Control and Status Register
Qualcomm devices have a set of registers that provide various control and status
functions for their peripherals. This node is intended to allow access to these
registers via syscon.
Required properties:
- compatible: Should contain:
"qcom,tcsr-ipq6018", "syscon", "simple-mfd" for IPQ6018
"qcom,tcsr-ipq8064", "syscon" for IPQ8064
"qcom,tcsr-apq8064", "syscon" for APQ8064
"qcom,tcsr-msm8660", "syscon" for MSM8660
"qcom,tcsr-msm8953", "syscon" for MSM8953
"qcom,tcsr-msm8960", "syscon" for MSM8960
"qcom,tcsr-msm8974", "syscon" for MSM8974
"qcom,tcsr-apq8084", "syscon" for APQ8084
"qcom,tcsr-msm8916", "syscon" for MSM8916
- reg: Address range for TCSR registers
Example:
tcsr: syscon@1a400000 {
compatible = "qcom,tcsr-msm8960", "syscon";
reg = <0x1a400000 0x100>;
};

50
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml Normal file
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@ -0,0 +1,50 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/qcom,tcsr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Top Control and Status Register
maintainers:
- Bjorn Andersson <bjorn.andersson@linaro.org>
description:
Qualcomm devices have a set of registers that provide various control and
status functions for their peripherals.
properties:
compatible:
oneOf:
- items:
- enum:
- qcom,tcsr-apq8064
- qcom,tcsr-apq8084
- qcom,tcsr-ipq8064
- qcom,tcsr-mdm9615
- qcom,tcsr-msm8660
- qcom,tcsr-msm8916
- qcom,tcsr-msm8953
- qcom,tcsr-msm8960
- qcom,tcsr-msm8974
- const: syscon
- items:
- const: qcom,tcsr-ipq6018
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
syscon@1a400000 {
compatible = "qcom,tcsr-msm8960", "syscon";
reg = <0x1a400000 0x100>;
};

2
Documentation/devicetree/bindings/mfd/qcom-pm8xxx.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm PM8xxx PMIC multi-function devices title: Qualcomm PM8xxx PMIC multi-function devices
maintainers: maintainers:
- Satya Priya <skakit@codeaurora.org> - Satya Priya <quic_c_skakit@quicinc.com>
description: | description: |
The PM8xxx family of Power Management ICs are used to provide regulated The PM8xxx family of Power Management ICs are used to provide regulated

36
Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
View File

@ -58,24 +58,6 @@ properties:
- "#pwm-cells" - "#pwm-cells"
- compatible - compatible
patternProperties:
"^trigger@[0-9]+$":
type: object
properties:
compatible:
const: st,stm32-lptimer-trigger
reg:
description: Identify trigger hardware block.
items:
minimum: 0
maximum: 2
required:
- compatible
- reg
counter: counter:
type: object type: object
@ -96,6 +78,24 @@ patternProperties:
required: required:
- compatible - compatible
patternProperties:
"^trigger@[0-9]+$":
type: object
properties:
compatible:
const: st,stm32-lptimer-trigger
reg:
description: Identify trigger hardware block.
items:
minimum: 0
maximum: 2
required:
- compatible
- reg
required: required:
- "#address-cells" - "#address-cells"
- "#size-cells" - "#size-cells"

37
Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
View File

@ -33,7 +33,7 @@ properties:
items: items:
- const: int - const: int
reset: resets:
maxItems: 1 maxItems: 1
dmas: dmas:
@ -46,6 +46,21 @@ properties:
minItems: 1 minItems: 1
maxItems: 7 maxItems: 7
interrupts:
oneOf:
- maxItems: 1
- maxItems: 4
interrupt-names:
oneOf:
- items:
- const: global
- items:
- const: brk
- const: up
- const: trg-com
- const: cc
"#address-cells": "#address-cells":
const: 1 const: 1
@ -87,6 +102,16 @@ properties:
- "#pwm-cells" - "#pwm-cells"
- compatible - compatible
counter:
type: object
properties:
compatible:
const: st,stm32-timer-counter
required:
- compatible
patternProperties: patternProperties:
"^timer@[0-9]+$": "^timer@[0-9]+$":
type: object type: object
@ -107,16 +132,6 @@ patternProperties:
- compatible - compatible
- reg - reg
counter:
type: object
properties:
compatible:
const: st,stm32-timer-counter
required:
- compatible
required: required:
- compatible - compatible
- reg - reg

2
Documentation/devicetree/bindings/mfd/syscon.yaml
View File

@ -17,7 +17,7 @@ description: |
and access the registers directly. and access the registers directly.
maintainers: maintainers:
- Lee Jones <lee.jones@linaro.org> - Lee Jones <lee@kernel.org>
select: select:
properties: properties:

12
Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
View File

@ -48,6 +48,12 @@ patternProperties:
description: description:
This is the SERDES lane control mux. This is the SERDES lane control mux.
"^clock-controller@[0-9a-f]+$":
type: object
$ref: /schemas/clock/ti,am654-ehrpwm-tbclk.yaml#
description:
Clock provider for TI EHRPWM nodes.
required: required:
- compatible - compatible
- reg - reg
@ -79,5 +85,11 @@ examples:
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>; <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
/* SERDES4 lane0/1/2/3 select */ /* SERDES4 lane0/1/2/3 select */
}; };
clock-controller@4140 {
compatible = "ti,am654-ehrpwm-tbclk", "syscon";
reg = <0x4140 0x18>;
#clock-cells = <1>;
};
}; };
... ...

2
Documentation/devicetree/bindings/trivial-devices.yaml
View File

@ -95,8 +95,6 @@ properties:
- dh,dhcom-board - dh,dhcom-board
# DA9053: flexible system level PMIC with multicore support # DA9053: flexible system level PMIC with multicore support
- dlg,da9053 - dlg,da9053
# DA9063: system PMIC for quad-core application processors
- dlg,da9063
# DMARD05: 3-axis I2C Accelerometer # DMARD05: 3-axis I2C Accelerometer
- domintech,dmard05 - domintech,dmard05
# DMARD06: 3-axis I2C Accelerometer # DMARD06: 3-axis I2C Accelerometer

8
MAINTAINERS
View File

@ -5999,6 +5999,7 @@ W: http://www.dialog-semiconductor.com/products
F: Documentation/devicetree/bindings/input/da90??-onkey.txt F: Documentation/devicetree/bindings/input/da90??-onkey.txt
F: Documentation/devicetree/bindings/input/dlg,da72??.txt F: Documentation/devicetree/bindings/input/dlg,da72??.txt
F: Documentation/devicetree/bindings/mfd/da90*.txt F: Documentation/devicetree/bindings/mfd/da90*.txt
F: Documentation/devicetree/bindings/mfd/da90*.yaml
F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml F: Documentation/devicetree/bindings/regulator/dlg,da9*.yaml
F: Documentation/devicetree/bindings/regulator/da92*.txt F: Documentation/devicetree/bindings/regulator/da92*.txt
F: Documentation/devicetree/bindings/regulator/slg51000.txt F: Documentation/devicetree/bindings/regulator/slg51000.txt
@ -10388,7 +10389,7 @@ F: drivers/gpio/gpio-*cove.c
INTEL PMIC MULTIFUNCTION DEVICE DRIVERS INTEL PMIC MULTIFUNCTION DEVICE DRIVERS
M: Andy Shevchenko <andy@kernel.org> M: Andy Shevchenko <andy@kernel.org>
S: Maintained S: Supported
F: drivers/mfd/intel_soc_pmic* F: drivers/mfd/intel_soc_pmic*
F: include/linux/mfd/intel_soc_pmic* F: include/linux/mfd/intel_soc_pmic*
@ -12401,7 +12402,6 @@ F: Documentation/devicetree/bindings/*/maxim,max77686.yaml
F: Documentation/devicetree/bindings/*/maxim,max77693.yaml F: Documentation/devicetree/bindings/*/maxim,max77693.yaml
F: Documentation/devicetree/bindings/*/maxim,max77843.yaml F: Documentation/devicetree/bindings/*/maxim,max77843.yaml
F: Documentation/devicetree/bindings/clock/maxim,max77686.txt F: Documentation/devicetree/bindings/clock/maxim,max77686.txt
F: Documentation/devicetree/bindings/mfd/max77693.txt
F: drivers/*/*max77843.c F: drivers/*/*max77843.c
F: drivers/*/max14577*.c F: drivers/*/max14577*.c
F: drivers/*/max77686*.c F: drivers/*/max77686*.c
@ -13872,7 +13872,7 @@ F: Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.yaml
F: drivers/media/i2c/mt9v111.c F: drivers/media/i2c/mt9v111.c
MULTIFUNCTION DEVICES (MFD) MULTIFUNCTION DEVICES (MFD)
M: Lee Jones <lee.jones@linaro.org> M: Lee Jones <lee@kernel.org>
S: Supported S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git
F: Documentation/devicetree/bindings/mfd/ F: Documentation/devicetree/bindings/mfd/
@ -19689,7 +19689,7 @@ S: Maintained
F: drivers/mmc/host/sdhci-pci-dwc-mshc.c F: drivers/mmc/host/sdhci-pci-dwc-mshc.c
SYSTEM CONFIGURATION (SYSCON) SYSTEM CONFIGURATION (SYSCON)
M: Lee Jones <lee.jones@linaro.org> M: Lee Jones <lee@kernel.org>
M: Arnd Bergmann <arnd@arndb.de> M: Arnd Bergmann <arnd@arndb.de>
S: Supported S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git

4
arch/arm/mach-pxa/eseries.c
View File

@ -81,11 +81,10 @@ int eseries_tmio_enable(struct platform_device *dev)
return 0; return 0;
} }
int eseries_tmio_disable(struct platform_device *dev) void eseries_tmio_disable(struct platform_device *dev)
{ {
gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0); gpio_set_value(GPIO_ESERIES_TMIO_SUSPEND, 0);
gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0); gpio_set_value(GPIO_ESERIES_TMIO_PCLR, 0);
return 0;
} }
int eseries_tmio_suspend(struct platform_device *dev) int eseries_tmio_suspend(struct platform_device *dev)
@ -134,7 +133,6 @@ static void __init __maybe_unused eseries_register_clks(void)
static struct tc6387xb_platform_data e330_tc6387xb_info = { static struct tc6387xb_platform_data e330_tc6387xb_info = {
.enable = &eseries_tmio_enable, .enable = &eseries_tmio_enable,
.disable = &eseries_tmio_disable,
.suspend = &eseries_tmio_suspend, .suspend = &eseries_tmio_suspend,
.resume = &eseries_tmio_resume, .resume = &eseries_tmio_resume,
}; };

4
arch/arm/mach-pxa/tosa.c
View File

@ -678,13 +678,11 @@ err_req_pclr:
return rc; return rc;
} }
static int tosa_tc6393xb_disable(struct platform_device *dev) static void tosa_tc6393xb_disable(struct platform_device *dev)
{ {
gpio_free(TOSA_GPIO_TC6393XB_L3V_ON); gpio_free(TOSA_GPIO_TC6393XB_L3V_ON);
gpio_free(TOSA_GPIO_TC6393XB_SUSPEND); gpio_free(TOSA_GPIO_TC6393XB_SUSPEND);
gpio_free(TOSA_GPIO_TC6393XB_REST_IN); gpio_free(TOSA_GPIO_TC6393XB_REST_IN);
return 0;
} }
static int tosa_tc6393xb_resume(struct platform_device *dev) static int tosa_tc6393xb_resume(struct platform_device *dev)

5
drivers/mfd/Kconfig
View File

@ -1358,12 +1358,13 @@ config MFD_STA2X11
select REGMAP_MMIO select REGMAP_MMIO
config MFD_SUN6I_PRCM config MFD_SUN6I_PRCM
bool "Allwinner A31 PRCM controller" bool "Allwinner A31/A23/A33 PRCM controller"
depends on ARCH_SUNXI || COMPILE_TEST depends on ARCH_SUNXI || COMPILE_TEST
select MFD_CORE select MFD_CORE
help help
Support for the PRCM (Power/Reset/Clock Management) unit available Support for the PRCM (Power/Reset/Clock Management) unit available
in A31 SoC. in the A31, A23, and A33 SoCs. Other Allwinner SoCs contain similar
hardware, but they do not use this driver.
config MFD_SYSCON config MFD_SYSCON
bool "System Controller Register R/W Based on Regmap" bool "System Controller Register R/W Based on Regmap"

9
drivers/mfd/asic3.c
View File

@ -596,12 +596,11 @@ static __init int asic3_gpio_probe(struct platform_device *pdev,
return gpiochip_add_data(&asic->gpio, asic); return gpiochip_add_data(&asic->gpio, asic);
} }
static int asic3_gpio_remove(struct platform_device *pdev) static void asic3_gpio_remove(struct platform_device *pdev)
{ {
struct asic3 *asic = platform_get_drvdata(pdev); struct asic3 *asic = platform_get_drvdata(pdev);
gpiochip_remove(&asic->gpio); gpiochip_remove(&asic->gpio);
return 0;
} }
static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk) static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
@ -1030,7 +1029,6 @@ static int __init asic3_probe(struct platform_device *pdev)
static int asic3_remove(struct platform_device *pdev) static int asic3_remove(struct platform_device *pdev)
{ {
int ret;
struct asic3 *asic = platform_get_drvdata(pdev); struct asic3 *asic = platform_get_drvdata(pdev);
asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT), asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
@ -1038,9 +1036,8 @@ static int asic3_remove(struct platform_device *pdev)
asic3_mfd_remove(pdev); asic3_mfd_remove(pdev);
ret = asic3_gpio_remove(pdev); asic3_gpio_remove(pdev);
if (ret < 0)
return ret;
asic3_irq_remove(pdev); asic3_irq_remove(pdev);
asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0); asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);

9
drivers/mfd/axp20x.c
View File

@ -619,6 +619,9 @@ static const struct mfd_cell axp20x_cells[] = {
static const struct mfd_cell axp221_cells[] = { static const struct mfd_cell axp221_cells[] = {
{ {
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp221-gpio",
}, {
.name = "axp221-pek", .name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp22x_pek_resources), .num_resources = ARRAY_SIZE(axp22x_pek_resources),
.resources = axp22x_pek_resources, .resources = axp22x_pek_resources,
@ -645,6 +648,9 @@ static const struct mfd_cell axp221_cells[] = {
static const struct mfd_cell axp223_cells[] = { static const struct mfd_cell axp223_cells[] = {
{ {
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp221-gpio",
}, {
.name = "axp221-pek", .name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp22x_pek_resources), .num_resources = ARRAY_SIZE(axp22x_pek_resources),
.resources = axp22x_pek_resources, .resources = axp22x_pek_resources,
@ -785,6 +791,9 @@ static const struct mfd_cell axp806_cells[] = {
static const struct mfd_cell axp809_cells[] = { static const struct mfd_cell axp809_cells[] = {
{ {
.name = "axp20x-gpio",
.of_compatible = "x-powers,axp221-gpio",
}, {
.name = "axp221-pek", .name = "axp221-pek",
.num_resources = ARRAY_SIZE(axp809_pek_resources), .num_resources = ARRAY_SIZE(axp809_pek_resources),
.resources = axp809_pek_resources, .resources = axp809_pek_resources,

5
drivers/mfd/cros_ec_dev.c
View File

@ -64,6 +64,11 @@ static const struct cros_feature_to_name cros_mcu_devices[] = {
.name = CROS_EC_DEV_SCP_NAME, .name = CROS_EC_DEV_SCP_NAME,
.desc = "System Control Processor", .desc = "System Control Processor",
}, },
{
.id = EC_FEATURE_SCP_C1,
.name = CROS_EC_DEV_SCP_C1_NAME,
.desc = "System Control Processor 2nd Core",
},
{ {
.id = EC_FEATURE_TOUCHPAD, .id = EC_FEATURE_TOUCHPAD,
.name = CROS_EC_DEV_TP_NAME, .name = CROS_EC_DEV_TP_NAME,

2
drivers/mfd/db8500-prcmu.c
View File

@ -798,7 +798,7 @@ void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
* @opp: The new ARM operating point to which transition is to be made * @opp: The new ARM operating point to which transition is to be made
* Returns: 0 on success, non-zero on failure * Returns: 0 on success, non-zero on failure
* *
* This function sets the the operating point of the ARM. * This function sets the operating point of the ARM.
*/ */
int db8500_prcmu_set_arm_opp(u8 opp) int db8500_prcmu_set_arm_opp(u8 opp)
{ {

17
drivers/mfd/dln2.c
View File

@ -91,11 +91,6 @@ struct dln2_mod_rx_slots {
spinlock_t lock; spinlock_t lock;
}; };
enum dln2_endpoint {
DLN2_EP_OUT = 0,
DLN2_EP_IN = 1,
};
struct dln2_dev { struct dln2_dev {
struct usb_device *usb_dev; struct usb_device *usb_dev;
struct usb_interface *interface; struct usb_interface *interface;
@ -777,16 +772,12 @@ static int dln2_probe(struct usb_interface *interface,
int ret; int ret;
int i, j; int i, j;
if (hostif->desc.bInterfaceNumber != 0 || if (hostif->desc.bInterfaceNumber != 0)
hostif->desc.bNumEndpoints < 2)
return -ENODEV; return -ENODEV;
epout = &hostif->endpoint[DLN2_EP_OUT].desc; ret = usb_find_common_endpoints(hostif, &epin, &epout, NULL, NULL);
if (!usb_endpoint_is_bulk_out(epout)) if (ret)
return -ENODEV; return ret;
epin = &hostif->endpoint[DLN2_EP_IN].desc;
if (!usb_endpoint_is_bulk_in(epin))
return -ENODEV;
dln2 = kzalloc(sizeof(*dln2), GFP_KERNEL); dln2 = kzalloc(sizeof(*dln2), GFP_KERNEL);
if (!dln2) if (!dln2)

13
drivers/mfd/intel-lpss-pci.c
View File

@ -385,6 +385,19 @@ static const struct pci_device_id intel_lpss_pci_ids[] = {
{ PCI_VDEVICE(INTEL, 0x7afc), (kernel_ulong_t)&bxt_i2c_info }, { PCI_VDEVICE(INTEL, 0x7afc), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7afd), (kernel_ulong_t)&bxt_i2c_info }, { PCI_VDEVICE(INTEL, 0x7afd), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7afe), (kernel_ulong_t)&bxt_uart_info }, { PCI_VDEVICE(INTEL, 0x7afe), (kernel_ulong_t)&bxt_uart_info },
/* MTL-P */
{ PCI_VDEVICE(INTEL, 0x7e25), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7e26), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7e27), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x7e30), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x7e46), (kernel_ulong_t)&bxt_info },
{ PCI_VDEVICE(INTEL, 0x7e50), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e51), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e52), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x7e78), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e79), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e7a), (kernel_ulong_t)&bxt_i2c_info },
{ PCI_VDEVICE(INTEL, 0x7e7b), (kernel_ulong_t)&bxt_i2c_info },
/* LKF */ /* LKF */
{ PCI_VDEVICE(INTEL, 0x98a8), (kernel_ulong_t)&bxt_uart_info }, { PCI_VDEVICE(INTEL, 0x98a8), (kernel_ulong_t)&bxt_uart_info },
{ PCI_VDEVICE(INTEL, 0x98a9), (kernel_ulong_t)&bxt_uart_info }, { PCI_VDEVICE(INTEL, 0x98a9), (kernel_ulong_t)&bxt_uart_info },

194
drivers/mfd/intel_soc_pmic_bxtwc.c
View File

@ -2,10 +2,11 @@
/* /*
* MFD core driver for Intel Broxton Whiskey Cove PMIC * MFD core driver for Intel Broxton Whiskey Cove PMIC
* *
* Copyright (C) 2015 Intel Corporation. All rights reserved. * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
*/ */
#include <linux/acpi.h> #include <linux/acpi.h>
#include <linux/bits.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
@ -18,9 +19,9 @@
#include <asm/intel_scu_ipc.h> #include <asm/intel_scu_ipc.h>
/* PMIC device registers */ /* PMIC device registers */
#define REG_ADDR_MASK 0xFF00 #define REG_ADDR_MASK GENMASK(15, 8)
#define REG_ADDR_SHIFT 8 #define REG_ADDR_SHIFT 8
#define REG_OFFSET_MASK 0xFF #define REG_OFFSET_MASK GENMASK(7, 0)
/* Interrupt Status Registers */ /* Interrupt Status Registers */
#define BXTWC_IRQLVL1 0x4E02 #define BXTWC_IRQLVL1 0x4E02
@ -112,29 +113,29 @@ static const struct regmap_irq bxtwc_regmap_irqs[] = {
}; };
static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = { static const struct regmap_irq bxtwc_regmap_irqs_pwrbtn[] = {
REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, 0x01), REGMAP_IRQ_REG(BXTWC_PWRBTN_IRQ, 0, BIT(0)),
}; };
static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = { static const struct regmap_irq bxtwc_regmap_irqs_bcu[] = {
REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, 0x1f), REGMAP_IRQ_REG(BXTWC_BCU_IRQ, 0, GENMASK(4, 0)),
}; };
static const struct regmap_irq bxtwc_regmap_irqs_adc[] = { static const struct regmap_irq bxtwc_regmap_irqs_adc[] = {
REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, 0xff), REGMAP_IRQ_REG(BXTWC_ADC_IRQ, 0, GENMASK(7, 0)),
}; };
static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = { static const struct regmap_irq bxtwc_regmap_irqs_chgr[] = {
REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, 0x20), REGMAP_IRQ_REG(BXTWC_USBC_IRQ, 0, BIT(5)),
REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, 0x1f), REGMAP_IRQ_REG(BXTWC_CHGR0_IRQ, 0, GENMASK(4, 0)),
REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, 0x1f), REGMAP_IRQ_REG(BXTWC_CHGR1_IRQ, 1, GENMASK(4, 0)),
}; };
static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = { static const struct regmap_irq bxtwc_regmap_irqs_tmu[] = {
REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, 0x06), REGMAP_IRQ_REG(BXTWC_TMU_IRQ, 0, GENMASK(2, 1)),
}; };
static const struct regmap_irq bxtwc_regmap_irqs_crit[] = { static const struct regmap_irq bxtwc_regmap_irqs_crit[] = {
REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, 0x03), REGMAP_IRQ_REG(BXTWC_CRIT_IRQ, 0, GENMASK(1, 0)),
}; };
static struct regmap_irq_chip bxtwc_regmap_irq_chip = { static struct regmap_irq_chip bxtwc_regmap_irq_chip = {
@ -333,17 +334,19 @@ static unsigned long bxtwc_reg_addr;
static ssize_t addr_show(struct device *dev, static ssize_t addr_show(struct device *dev,
struct device_attribute *attr, char *buf) struct device_attribute *attr, char *buf)
{ {
return sprintf(buf, "0x%lx\n", bxtwc_reg_addr); return sysfs_emit(buf, "0x%lx\n", bxtwc_reg_addr);
} }
static ssize_t addr_store(struct device *dev, static ssize_t addr_store(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count) struct device_attribute *attr, const char *buf, size_t count)
{ {
if (kstrtoul(buf, 0, &bxtwc_reg_addr)) { int ret;
dev_err(dev, "Invalid register address\n");
return -EINVAL; ret = kstrtoul(buf, 0, &bxtwc_reg_addr);
} if (ret)
return (ssize_t)count; return ret;
return count;
} }
static ssize_t val_show(struct device *dev, static ssize_t val_show(struct device *dev,
@ -354,12 +357,12 @@ static ssize_t val_show(struct device *dev,
struct intel_soc_pmic *pmic = dev_get_drvdata(dev); struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val); ret = regmap_read(pmic->regmap, bxtwc_reg_addr, &val);
if (ret < 0) { if (ret) {
dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr); dev_err(dev, "Failed to read 0x%lx\n", bxtwc_reg_addr);
return -EIO; return ret;
} }
return sprintf(buf, "0x%02x\n", val); return sysfs_emit(buf, "0x%02x\n", val);
} }
static ssize_t val_store(struct device *dev, static ssize_t val_store(struct device *dev,
@ -377,7 +380,7 @@ static ssize_t val_store(struct device *dev,
if (ret) { if (ret) {
dev_err(dev, "Failed to write value 0x%02x to address 0x%lx", dev_err(dev, "Failed to write value 0x%02x to address 0x%lx",
val, bxtwc_reg_addr); val, bxtwc_reg_addr);
return -EIO; return ret;
} }
return count; return count;
} }
@ -394,6 +397,11 @@ static const struct attribute_group bxtwc_group = {
.attrs = bxtwc_attrs, .attrs = bxtwc_attrs,
}; };
static const struct attribute_group *bxtwc_groups[] = {
&bxtwc_group,
NULL
};
static const struct regmap_config bxtwc_regmap_config = { static const struct regmap_config bxtwc_regmap_config = {
.reg_bits = 16, .reg_bits = 16,
.val_bits = 8, .val_bits = 8,
@ -410,12 +418,9 @@ static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
int irq; int irq;
irq = regmap_irq_get_virq(pdata, pirq); irq = regmap_irq_get_virq(pdata, pirq);
if (irq < 0) { if (irq < 0)
dev_err(pmic->dev, return dev_err_probe(pmic->dev, irq, "Failed to get parent vIRQ(%d) for chip %s\n",
"Failed to get parent vIRQ(%d) for chip %s, ret:%d\n", pirq, chip->name);
pirq, chip->name, irq);
return irq;
}
return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags, return devm_regmap_add_irq_chip(pmic->dev, pmic->regmap, irq, irq_flags,
0, chip, data); 0, chip, data);
@ -423,25 +428,19 @@ static int bxtwc_add_chained_irq_chip(struct intel_soc_pmic *pmic,
static int bxtwc_probe(struct platform_device *pdev) static int bxtwc_probe(struct platform_device *pdev)
{ {
struct device *dev = &pdev->dev;
int ret; int ret;
acpi_handle handle;
acpi_status status; acpi_status status;
unsigned long long hrv; unsigned long long hrv;
struct intel_soc_pmic *pmic; struct intel_soc_pmic *pmic;
handle = ACPI_HANDLE(&pdev->dev); status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
status = acpi_evaluate_integer(handle, "_HRV", NULL, &hrv); if (ACPI_FAILURE(status))
if (ACPI_FAILURE(status)) { return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
dev_err(&pdev->dev, "Failed to get PMIC hardware revision\n"); if (hrv != BROXTON_PMIC_WC_HRV)
return -ENODEV; return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
}
if (hrv != BROXTON_PMIC_WC_HRV) {
dev_err(&pdev->dev, "Invalid PMIC hardware revision: %llu\n",
hrv);
return -ENODEV;
}
pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL); pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic) if (!pmic)
return -ENOMEM; return -ENOMEM;
@ -450,49 +449,39 @@ static int bxtwc_probe(struct platform_device *pdev)
return ret; return ret;
pmic->irq = ret; pmic->irq = ret;
dev_set_drvdata(&pdev->dev, pmic); platform_set_drvdata(pdev, pmic);
pmic->dev = &pdev->dev; pmic->dev = dev;
pmic->scu = devm_intel_scu_ipc_dev_get(&pdev->dev); pmic->scu = devm_intel_scu_ipc_dev_get(dev);
if (!pmic->scu) if (!pmic->scu)
return -EPROBE_DEFER; return -EPROBE_DEFER;
pmic->regmap = devm_regmap_init(&pdev->dev, NULL, pmic, pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bxtwc_regmap_config);
&bxtwc_regmap_config); if (IS_ERR(pmic->regmap))
if (IS_ERR(pmic->regmap)) { return dev_err_probe(dev, PTR_ERR(pmic->regmap), "Failed to initialise regmap\n");
ret = PTR_ERR(pmic->regmap);
dev_err(&pdev->dev, "Failed to initialise regmap: %d\n", ret);
return ret;
}
ret = devm_regmap_add_irq_chip(&pdev->dev, pmic->regmap, pmic->irq, ret = devm_regmap_add_irq_chip(dev, pmic->regmap, pmic->irq,
IRQF_ONESHOT | IRQF_SHARED, IRQF_ONESHOT | IRQF_SHARED,
0, &bxtwc_regmap_irq_chip, 0, &bxtwc_regmap_irq_chip,
&pmic->irq_chip_data); &pmic->irq_chip_data);
if (ret) { if (ret)
dev_err(&pdev->dev, "Failed to add IRQ chip\n"); return dev_err_probe(dev, ret, "Failed to add IRQ chip\n");
return ret;
}
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data, ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_PWRBTN_LVL1_IRQ, BXTWC_PWRBTN_LVL1_IRQ,
IRQF_ONESHOT, IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_pwrbtn, &bxtwc_regmap_irq_chip_pwrbtn,
&pmic->irq_chip_data_pwrbtn); &pmic->irq_chip_data_pwrbtn);
if (ret) { if (ret)
dev_err(&pdev->dev, "Failed to add PWRBTN IRQ chip\n"); return dev_err_probe(dev, ret, "Failed to add PWRBTN IRQ chip\n");
return ret;
}
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data, ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
BXTWC_TMU_LVL1_IRQ, BXTWC_TMU_LVL1_IRQ,
IRQF_ONESHOT, IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_tmu, &bxtwc_regmap_irq_chip_tmu,
&pmic->irq_chip_data_tmu); &pmic->irq_chip_data_tmu);
if (ret) { if (ret)
dev_err(&pdev->dev, "Failed to add TMU IRQ chip\n"); return dev_err_probe(dev, ret, "Failed to add TMU IRQ chip\n");
return ret;
}
/* Add chained IRQ handler for BCU IRQs */ /* Add chained IRQ handler for BCU IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data, ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@ -500,12 +489,8 @@ static int bxtwc_probe(struct platform_device *pdev)
IRQF_ONESHOT, IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_bcu, &bxtwc_regmap_irq_chip_bcu,
&pmic->irq_chip_data_bcu); &pmic->irq_chip_data_bcu);
if (ret)
return dev_err_probe(dev, ret, "Failed to add BUC IRQ chip\n");
if (ret) {
dev_err(&pdev->dev, "Failed to add BUC IRQ chip\n");
return ret;
}
/* Add chained IRQ handler for ADC IRQs */ /* Add chained IRQ handler for ADC IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data, ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@ -513,12 +498,8 @@ static int bxtwc_probe(struct platform_device *pdev)
IRQF_ONESHOT, IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_adc, &bxtwc_regmap_irq_chip_adc,
&pmic->irq_chip_data_adc); &pmic->irq_chip_data_adc);
if (ret)
return dev_err_probe(dev, ret, "Failed to add ADC IRQ chip\n");
if (ret) {
dev_err(&pdev->dev, "Failed to add ADC IRQ chip\n");
return ret;
}
/* Add chained IRQ handler for CHGR IRQs */ /* Add chained IRQ handler for CHGR IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data, ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@ -526,12 +507,8 @@ static int bxtwc_probe(struct platform_device *pdev)
IRQF_ONESHOT, IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_chgr, &bxtwc_regmap_irq_chip_chgr,
&pmic->irq_chip_data_chgr); &pmic->irq_chip_data_chgr);
if (ret)
return dev_err_probe(dev, ret, "Failed to add CHGR IRQ chip\n");
if (ret) {
dev_err(&pdev->dev, "Failed to add CHGR IRQ chip\n");
return ret;
}
/* Add chained IRQ handler for CRIT IRQs */ /* Add chained IRQ handler for CRIT IRQs */
ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data, ret = bxtwc_add_chained_irq_chip(pmic, pmic->irq_chip_data,
@ -539,54 +516,33 @@ static int bxtwc_probe(struct platform_device *pdev)
IRQF_ONESHOT, IRQF_ONESHOT,
&bxtwc_regmap_irq_chip_crit, &bxtwc_regmap_irq_chip_crit,
&pmic->irq_chip_data_crit); &pmic->irq_chip_data_crit);
if (ret)
return dev_err_probe(dev, ret, "Failed to add CRIT IRQ chip\n");
ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, bxt_wc_dev, ARRAY_SIZE(bxt_wc_dev),
if (ret) { NULL, 0, NULL);
dev_err(&pdev->dev, "Failed to add CRIT IRQ chip\n"); if (ret)
return ret; return dev_err_probe(dev, ret, "Failed to add devices\n");
}
ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, bxt_wc_dev,
ARRAY_SIZE(bxt_wc_dev), NULL, 0, NULL);
if (ret) {
dev_err(&pdev->dev, "Failed to add devices\n");
return ret;
}
ret = sysfs_create_group(&pdev->dev.kobj, &bxtwc_group);
if (ret) {
dev_err(&pdev->dev, "Failed to create sysfs group %d\n", ret);
return ret;
}
/* /*
* There is known hw bug. Upon reset BIT 5 of register * There is a known H/W bug. Upon reset, BIT 5 of register
* BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However, * BXTWC_CHGR_LVL1_IRQ is 0 which is the expected value. However,
* later it's set to 1(masked) automatically by hardware. So we * later it's set to 1(masked) automatically by hardware. So we
* have the software workaround here to unmaksed it in order to let * place the software workaround here to unmask it again in order
* charger interrutp work. * to re-enable the charger interrupt.
*/ */
regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, regmap_update_bits(pmic->regmap, BXTWC_MIRQLVL1, BXTWC_MIRQLVL1_MCHGR, 0);
BXTWC_MIRQLVL1_MCHGR, 0);
return 0;
}
static int bxtwc_remove(struct platform_device *pdev)
{
sysfs_remove_group(&pdev->dev.kobj, &bxtwc_group);
return 0; return 0;
} }
static void bxtwc_shutdown(struct platform_device *pdev) static void bxtwc_shutdown(struct platform_device *pdev)
{ {
struct intel_soc_pmic *pmic = dev_get_drvdata(&pdev->dev); struct intel_soc_pmic *pmic = platform_get_drvdata(pdev);
disable_irq(pmic->irq); disable_irq(pmic->irq);
} }
#ifdef CONFIG_PM_SLEEP
static int bxtwc_suspend(struct device *dev) static int bxtwc_suspend(struct device *dev)
{ {
struct intel_soc_pmic *pmic = dev_get_drvdata(dev); struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
@ -603,8 +559,8 @@ static int bxtwc_resume(struct device *dev)
enable_irq(pmic->irq); enable_irq(pmic->irq);
return 0; return 0;
} }
#endif
static SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume); static DEFINE_SIMPLE_DEV_PM_OPS(bxtwc_pm_ops, bxtwc_suspend, bxtwc_resume);
static const struct acpi_device_id bxtwc_acpi_ids[] = { static const struct acpi_device_id bxtwc_acpi_ids[] = {
{ "INT34D3", }, { "INT34D3", },
@ -614,16 +570,16 @@ MODULE_DEVICE_TABLE(acpi, bxtwc_acpi_ids);
static struct platform_driver bxtwc_driver = { static struct platform_driver bxtwc_driver = {
.probe = bxtwc_probe, .probe = bxtwc_probe,
.remove = bxtwc_remove,
.shutdown = bxtwc_shutdown, .shutdown = bxtwc_shutdown,
.driver = { .driver = {
.name = "BXTWC PMIC", .name = "BXTWC PMIC",
.pm = &bxtwc_pm_ops, .pm = pm_sleep_ptr(&bxtwc_pm_ops),
.acpi_match_table = ACPI_PTR(bxtwc_acpi_ids), .acpi_match_table = bxtwc_acpi_ids,
.dev_groups = bxtwc_groups,
}, },
}; };
module_platform_driver(bxtwc_driver); module_platform_driver(bxtwc_driver);
MODULE_LICENSE("GPL v2"); MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Qipeng Zha<qipeng.zha@intel.com>"); MODULE_AUTHOR("Qipeng Zha <qipeng.zha@intel.com>");

27
drivers/mfd/intel_soc_pmic_chtwc.c
View File

@ -179,18 +179,13 @@ static int cht_wc_probe(struct i2c_client *client)
int ret; int ret;
status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv); status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
if (ACPI_FAILURE(status)) { if (ACPI_FAILURE(status))
dev_err(dev, "Failed to get PMIC hardware revision\n"); return dev_err_probe(dev, -ENODEV, "Failed to get PMIC hardware revision\n");
return -ENODEV; if (hrv != CHT_WC_HRV)
} return dev_err_probe(dev, -ENODEV, "Invalid PMIC hardware revision: %llu\n", hrv);
if (hrv != CHT_WC_HRV) {
dev_err(dev, "Invalid PMIC hardware revision: %llu\n", hrv); if (client->irq < 0)
return -ENODEV; return dev_err_probe(dev, -EINVAL, "Invalid IRQ\n");
}
if (client->irq < 0) {
dev_err(dev, "Invalid IRQ\n");
return -EINVAL;
}
pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL); pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
if (!pmic) if (!pmic)
@ -227,7 +222,7 @@ static void cht_wc_shutdown(struct i2c_client *client)
disable_irq(pmic->irq); disable_irq(pmic->irq);
} }
static int __maybe_unused cht_wc_suspend(struct device *dev) static int cht_wc_suspend(struct device *dev)
{ {
struct intel_soc_pmic *pmic = dev_get_drvdata(dev); struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
@ -236,7 +231,7 @@ static int __maybe_unused cht_wc_suspend(struct device *dev)
return 0; return 0;
} }
static int __maybe_unused cht_wc_resume(struct device *dev) static int cht_wc_resume(struct device *dev)
{ {
struct intel_soc_pmic *pmic = dev_get_drvdata(dev); struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
@ -244,7 +239,7 @@ static int __maybe_unused cht_wc_resume(struct device *dev)
return 0; return 0;
} }
static SIMPLE_DEV_PM_OPS(cht_wc_pm_ops, cht_wc_suspend, cht_wc_resume); static DEFINE_SIMPLE_DEV_PM_OPS(cht_wc_pm_ops, cht_wc_suspend, cht_wc_resume);
static const struct i2c_device_id cht_wc_i2c_id[] = { static const struct i2c_device_id cht_wc_i2c_id[] = {
{ } { }
@ -258,7 +253,7 @@ static const struct acpi_device_id cht_wc_acpi_ids[] = {
static struct i2c_driver cht_wc_driver = { static struct i2c_driver cht_wc_driver = {
.driver = { .driver = {
.name = "CHT Whiskey Cove PMIC", .name = "CHT Whiskey Cove PMIC",
.pm = &cht_wc_pm_ops, .pm = pm_sleep_ptr(&cht_wc_pm_ops),
.acpi_match_table = cht_wc_acpi_ids, .acpi_match_table = cht_wc_acpi_ids,
}, },
.probe_new = cht_wc_probe, .probe_new = cht_wc_probe,

2
drivers/mfd/max77620.c
View File

@ -419,9 +419,11 @@ static int max77620_initialise_fps(struct max77620_chip *chip)
ret = max77620_config_fps(chip, fps_child); ret = max77620_config_fps(chip, fps_child);
if (ret < 0) { if (ret < 0) {
of_node_put(fps_child); of_node_put(fps_child);
of_node_put(fps_np);
return ret; return ret;
} }
} }
of_node_put(fps_np);
config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0; config = chip->enable_global_lpm ? MAX77620_ONOFFCNFG2_SLP_LPM_MSK : 0;
ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2, ret = regmap_update_bits(chip->rmap, MAX77620_REG_ONOFFCNFG2,

4
drivers/mfd/max77714.c
View File

@ -3,7 +3,7 @@
* Maxim MAX77714 Core Driver * Maxim MAX77714 Core Driver
* *
* Copyright (C) 2022 Luca Ceresoli * Copyright (C) 2022 Luca Ceresoli
* Author: Luca Ceresoli <luca@lucaceresoli.net> * Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
*/ */
#include <linux/i2c.h> #include <linux/i2c.h>
@ -148,5 +148,5 @@ static struct i2c_driver max77714_driver = {
module_i2c_driver(max77714_driver); module_i2c_driver(max77714_driver);
MODULE_DESCRIPTION("Maxim MAX77714 MFD core driver"); MODULE_DESCRIPTION("Maxim MAX77714 MFD core driver");
MODULE_AUTHOR("Luca Ceresoli <luca@lucaceresoli.net>"); MODULE_AUTHOR("Luca Ceresoli <luca.ceresoli@bootlin.com>");
MODULE_LICENSE("GPL"); MODULE_LICENSE("GPL");

24
drivers/mfd/mt6358-irq.c
View File

@ -3,6 +3,8 @@
// Copyright (c) 2020 MediaTek Inc. // Copyright (c) 2020 MediaTek Inc.
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/mfd/mt6357/core.h>
#include <linux/mfd/mt6357/registers.h>
#include <linux/mfd/mt6358/core.h> #include <linux/mfd/mt6358/core.h>
#include <linux/mfd/mt6358/registers.h> #include <linux/mfd/mt6358/registers.h>
#include <linux/mfd/mt6359/core.h> #include <linux/mfd/mt6359/core.h>
@ -17,6 +19,17 @@
#define MTK_PMIC_REG_WIDTH 16 #define MTK_PMIC_REG_WIDTH 16
static const struct irq_top_t mt6357_ints[] = {
MT6357_TOP_GEN(BUCK),
MT6357_TOP_GEN(LDO),
MT6357_TOP_GEN(PSC),
MT6357_TOP_GEN(SCK),
MT6357_TOP_GEN(BM),
MT6357_TOP_GEN(HK),
MT6357_TOP_GEN(AUD),
MT6357_TOP_GEN(MISC),
};
static const struct irq_top_t mt6358_ints[] = { static const struct irq_top_t mt6358_ints[] = {
MT6358_TOP_GEN(BUCK), MT6358_TOP_GEN(BUCK),
MT6358_TOP_GEN(LDO), MT6358_TOP_GEN(LDO),
@ -39,6 +52,13 @@ static const struct irq_top_t mt6359_ints[] = {
MT6359_TOP_GEN(MISC), MT6359_TOP_GEN(MISC),
}; };
static struct pmic_irq_data mt6357_irqd = {
.num_top = ARRAY_SIZE(mt6357_ints),
.num_pmic_irqs = MT6357_IRQ_NR,
.top_int_status_reg = MT6357_TOP_INT_STATUS0,
.pmic_ints = mt6357_ints,
};
static struct pmic_irq_data mt6358_irqd = { static struct pmic_irq_data mt6358_irqd = {
.num_top = ARRAY_SIZE(mt6358_ints), .num_top = ARRAY_SIZE(mt6358_ints),
.num_pmic_irqs = MT6358_IRQ_NR, .num_pmic_irqs = MT6358_IRQ_NR,
@ -211,6 +231,10 @@ int mt6358_irq_init(struct mt6397_chip *chip)
struct pmic_irq_data *irqd; struct pmic_irq_data *irqd;
switch (chip->chip_id) { switch (chip->chip_id) {
case MT6357_CHIP_ID:
chip->irq_data = &mt6357_irqd;
break;
case MT6358_CHIP_ID: case MT6358_CHIP_ID:
case MT6366_CHIP_ID: case MT6366_CHIP_ID:
chip->irq_data = &mt6358_irqd; chip->irq_data = &mt6358_irqd;

91
drivers/mfd/mt6397-core.c
View File

@ -12,10 +12,14 @@
#include <linux/regmap.h> #include <linux/regmap.h>
#include <linux/mfd/core.h> #include <linux/mfd/core.h>
#include <linux/mfd/mt6323/core.h> #include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6331/core.h>
#include <linux/mfd/mt6357/core.h>
#include <linux/mfd/mt6358/core.h> #include <linux/mfd/mt6358/core.h>
#include <linux/mfd/mt6359/core.h> #include <linux/mfd/mt6359/core.h>
#include <linux/mfd/mt6397/core.h> #include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6323/registers.h> #include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6357/registers.h>
#include <linux/mfd/mt6358/registers.h> #include <linux/mfd/mt6358/registers.h>
#include <linux/mfd/mt6359/registers.h> #include <linux/mfd/mt6359/registers.h>
#include <linux/mfd/mt6397/registers.h> #include <linux/mfd/mt6397/registers.h>
@ -23,6 +27,12 @@
#define MT6323_RTC_BASE 0x8000 #define MT6323_RTC_BASE 0x8000
#define MT6323_RTC_SIZE 0x40 #define MT6323_RTC_SIZE 0x40
#define MT6357_RTC_BASE 0x0588
#define MT6357_RTC_SIZE 0x3c
#define MT6331_RTC_BASE 0x4000
#define MT6331_RTC_SIZE 0x40
#define MT6358_RTC_BASE 0x0588 #define MT6358_RTC_BASE 0x0588
#define MT6358_RTC_SIZE 0x3c #define MT6358_RTC_SIZE 0x3c
@ -37,6 +47,16 @@ static const struct resource mt6323_rtc_resources[] = {
DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC), DEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),
}; };
static const struct resource mt6357_rtc_resources[] = {
DEFINE_RES_MEM(MT6357_RTC_BASE, MT6357_RTC_SIZE),
DEFINE_RES_IRQ(MT6357_IRQ_RTC),
};
static const struct resource mt6331_rtc_resources[] = {
DEFINE_RES_MEM(MT6331_RTC_BASE, MT6331_RTC_SIZE),
DEFINE_RES_IRQ(MT6331_IRQ_STATUS_RTC),
};
static const struct resource mt6358_rtc_resources[] = { static const struct resource mt6358_rtc_resources[] = {
DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE), DEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE),
DEFINE_RES_IRQ(MT6358_IRQ_RTC), DEFINE_RES_IRQ(MT6358_IRQ_RTC),
@ -66,6 +86,18 @@ static const struct resource mt6323_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_FCHRKEY, "homekey"), DEFINE_RES_IRQ_NAMED(MT6323_IRQ_STATUS_FCHRKEY, "homekey"),
}; };
static const struct resource mt6357_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY, "homekey"),
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_PWRKEY_R, "powerkey_r"),
DEFINE_RES_IRQ_NAMED(MT6357_IRQ_HOMEKEY_R, "homekey_r"),
};
static const struct resource mt6331_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6331_IRQ_STATUS_HOMEKEY, "homekey"),
};
static const struct resource mt6397_keys_resources[] = { static const struct resource mt6397_keys_resources[] = {
DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"), DEFINE_RES_IRQ_NAMED(MT6397_IRQ_PWRKEY, "powerkey"),
DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"), DEFINE_RES_IRQ_NAMED(MT6397_IRQ_HOMEKEY, "homekey"),
@ -100,6 +132,43 @@ static const struct mfd_cell mt6323_devs[] = {
}, },
}; };
static const struct mfd_cell mt6357_devs[] = {
{
.name = "mt6357-regulator",
}, {
.name = "mt6357-rtc",
.num_resources = ARRAY_SIZE(mt6357_rtc_resources),
.resources = mt6357_rtc_resources,
.of_compatible = "mediatek,mt6357-rtc",
}, {
.name = "mtk-pmic-keys",
.num_resources = ARRAY_SIZE(mt6357_keys_resources),
.resources = mt6357_keys_resources,
.of_compatible = "mediatek,mt6357-keys"
},
};
/* MT6331 is always used in combination with MT6332 */
static const struct mfd_cell mt6331_mt6332_devs[] = {
{
.name = "mt6331-rtc",
.num_resources = ARRAY_SIZE(mt6331_rtc_resources),
.resources = mt6331_rtc_resources,
.of_compatible = "mediatek,mt6331-rtc",
}, {
.name = "mt6331-regulator",
.of_compatible = "mediatek,mt6331-regulator"
}, {
.name = "mt6332-regulator",
.of_compatible = "mediatek,mt6332-regulator"
}, {
.name = "mtk-pmic-keys",
.num_resources = ARRAY_SIZE(mt6331_keys_resources),
.resources = mt6331_keys_resources,
.of_compatible = "mediatek,mt6331-keys"
},
};
static const struct mfd_cell mt6358_devs[] = { static const struct mfd_cell mt6358_devs[] = {
{ {
.name = "mt6358-regulator", .name = "mt6358-regulator",
@ -179,6 +248,22 @@ static const struct chip_data mt6323_core = {
.irq_init = mt6397_irq_init, .irq_init = mt6397_irq_init,
}; };
static const struct chip_data mt6357_core = {
.cid_addr = MT6357_SWCID,
.cid_shift = 8,
.cells = mt6357_devs,
.cell_size = ARRAY_SIZE(mt6357_devs),
.irq_init = mt6358_irq_init,
};
static const struct chip_data mt6331_mt6332_core = {
.cid_addr = MT6331_HWCID,
.cid_shift = 0,
.cells = mt6331_mt6332_devs,
.cell_size = ARRAY_SIZE(mt6331_mt6332_devs),
.irq_init = mt6397_irq_init,
};
static const struct chip_data mt6358_core = { static const struct chip_data mt6358_core = {
.cid_addr = MT6358_SWCID, .cid_addr = MT6358_SWCID,
.cid_shift = 8, .cid_shift = 8,
@ -261,6 +346,12 @@ static const struct of_device_id mt6397_of_match[] = {
{ {
.compatible = "mediatek,mt6323", .compatible = "mediatek,mt6323",
.data = &mt6323_core, .data = &mt6323_core,
}, {
.compatible = "mediatek,mt6331",
.data = &mt6331_mt6332_core,
}, {
.compatible = "mediatek,mt6357",
.data = &mt6357_core,
}, { }, {
.compatible = "mediatek,mt6358", .compatible = "mediatek,mt6358",
.data = &mt6358_core, .data = &mt6358_core,

9
drivers/mfd/mt6397-irq.c
View File

@ -12,6 +12,8 @@
#include <linux/suspend.h> #include <linux/suspend.h>
#include <linux/mfd/mt6323/core.h> #include <linux/mfd/mt6323/core.h>
#include <linux/mfd/mt6323/registers.h> #include <linux/mfd/mt6323/registers.h>
#include <linux/mfd/mt6331/core.h>
#include <linux/mfd/mt6331/registers.h>
#include <linux/mfd/mt6397/core.h> #include <linux/mfd/mt6397/core.h>
#include <linux/mfd/mt6397/registers.h> #include <linux/mfd/mt6397/registers.h>
@ -172,7 +174,12 @@ int mt6397_irq_init(struct mt6397_chip *chip)
chip->int_status[0] = MT6323_INT_STATUS0; chip->int_status[0] = MT6323_INT_STATUS0;
chip->int_status[1] = MT6323_INT_STATUS1; chip->int_status[1] = MT6323_INT_STATUS1;
break; break;
case MT6331_CHIP_ID:
chip->int_con[0] = MT6331_INT_CON0;
chip->int_con[1] = MT6331_INT_CON1;
chip->int_status[0] = MT6331_INT_STATUS_CON0;
chip->int_status[1] = MT6331_INT_STATUS_CON1;
break;
case MT6391_CHIP_ID: case MT6391_CHIP_ID:
case MT6397_CHIP_ID: case MT6397_CHIP_ID:
chip->int_con[0] = MT6397_INT_CON0; chip->int_con[0] = MT6397_INT_CON0;

53
drivers/mfd/qcom-pm8008.c
View File

@ -54,13 +54,6 @@ enum {
#define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE) #define PM8008_PERIPH_OFFSET(paddr) (paddr - PM8008_PERIPH_0_BASE)
struct pm8008_data {
struct device *dev;
struct regmap *regmap;
int irq;
struct regmap_irq_chip_data *irq_data;
};
static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)}; static unsigned int p0_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_0_BASE)};
static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)}; static unsigned int p1_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_1_BASE)};
static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)}; static unsigned int p2_offs[] = {PM8008_PERIPH_OFFSET(PM8008_PERIPH_2_BASE)};
@ -150,7 +143,7 @@ static struct regmap_config qcom_mfd_regmap_cfg = {
.max_register = 0xFFFF, .max_register = 0xFFFF,
}; };
static int pm8008_init(struct pm8008_data *chip) static int pm8008_init(struct regmap *regmap)
{ {
int rc; int rc;
@ -160,34 +153,31 @@ static int pm8008_init(struct pm8008_data *chip)
* This is required to enable the writing of TYPE registers in * This is required to enable the writing of TYPE registers in
* regmap_irq_sync_unlock(). * regmap_irq_sync_unlock().
*/ */
rc = regmap_write(chip->regmap, rc = regmap_write(regmap, (PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
(PM8008_TEMP_ALARM_ADDR | INT_SET_TYPE_OFFSET),
BIT(0));
if (rc) if (rc)
return rc; return rc;
/* Do the same for GPIO1 and GPIO2 peripherals */ /* Do the same for GPIO1 and GPIO2 peripherals */
rc = regmap_write(chip->regmap, rc = regmap_write(regmap, (PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
(PM8008_GPIO1_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
if (rc) if (rc)
return rc; return rc;
rc = regmap_write(chip->regmap, rc = regmap_write(regmap, (PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
(PM8008_GPIO2_ADDR | INT_SET_TYPE_OFFSET), BIT(0));
return rc; return rc;
} }
static int pm8008_probe_irq_peripherals(struct pm8008_data *chip, static int pm8008_probe_irq_peripherals(struct device *dev,
struct regmap *regmap,
int client_irq) int client_irq)
{ {
int rc, i; int rc, i;
struct regmap_irq_type *type; struct regmap_irq_type *type;
struct regmap_irq_chip_data *irq_data; struct regmap_irq_chip_data *irq_data;
rc = pm8008_init(chip); rc = pm8008_init(regmap);
if (rc) { if (rc) {
dev_err(chip->dev, "Init failed: %d\n", rc); dev_err(dev, "Init failed: %d\n", rc);
return rc; return rc;
} }
@ -207,10 +197,10 @@ static int pm8008_probe_irq_peripherals(struct pm8008_data *chip,
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW); IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW);
} }
rc = devm_regmap_add_irq_chip(chip->dev, chip->regmap, client_irq, rc = devm_regmap_add_irq_chip(dev, regmap, client_irq,
IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data); IRQF_SHARED, 0, &pm8008_irq_chip, &irq_data);
if (rc) { if (rc) {
dev_err(chip->dev, "Failed to add IRQ chip: %d\n", rc); dev_err(dev, "Failed to add IRQ chip: %d\n", rc);
return rc; return rc;
} }
@ -220,26 +210,23 @@ static int pm8008_probe_irq_peripherals(struct pm8008_data *chip,
static int pm8008_probe(struct i2c_client *client) static int pm8008_probe(struct i2c_client *client)
{ {
int rc; int rc;
struct pm8008_data *chip; struct device *dev;
struct regmap *regmap;
chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); dev = &client->dev;
if (!chip) regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
return -ENOMEM; if (!regmap)
chip->dev = &client->dev;
chip->regmap = devm_regmap_init_i2c(client, &qcom_mfd_regmap_cfg);
if (!chip->regmap)
return -ENODEV; return -ENODEV;
i2c_set_clientdata(client, chip); i2c_set_clientdata(client, regmap);
if (of_property_read_bool(chip->dev->of_node, "interrupt-controller")) { if (of_property_read_bool(dev->of_node, "interrupt-controller")) {
rc = pm8008_probe_irq_peripherals(chip, client->irq); rc = pm8008_probe_irq_peripherals(dev, regmap, client->irq);
if (rc) if (rc)
dev_err(chip->dev, "Failed to probe irq periphs: %d\n", rc); dev_err(dev, "Failed to probe irq periphs: %d\n", rc);
} }
return devm_of_platform_populate(chip->dev); return devm_of_platform_populate(dev);
} }
static const struct of_device_id pm8008_match[] = { static const struct of_device_id pm8008_match[] = {

3
drivers/mfd/syscon.c
View File

@ -101,8 +101,7 @@ static struct syscon *of_syscon_register(struct device_node *np, bool check_clk)
} }
} }
syscon_config.name = kasprintf(GFP_KERNEL, "%pOFn@%llx", np, syscon_config.name = kasprintf(GFP_KERNEL, "%pOFn@%pa", np, &res.start);
(u64)res.start);
syscon_config.reg_stride = reg_io_width; syscon_config.reg_stride = reg_io_width;
syscon_config.val_bits = reg_io_width * 8; syscon_config.val_bits = reg_io_width * 8;
syscon_config.max_register = resource_size(&res) - reg_io_width; syscon_config.max_register = resource_size(&res) - reg_io_width;

6
drivers/mfd/t7l66xb.c
View File

@ -397,11 +397,8 @@ err_noirq:
static int t7l66xb_remove(struct platform_device *dev) static int t7l66xb_remove(struct platform_device *dev)
{ {
struct t7l66xb_platform_data *pdata = dev_get_platdata(&dev->dev);
struct t7l66xb *t7l66xb = platform_get_drvdata(dev); struct t7l66xb *t7l66xb = platform_get_drvdata(dev);
int ret;
ret = pdata->disable(dev);
clk_disable_unprepare(t7l66xb->clk48m); clk_disable_unprepare(t7l66xb->clk48m);
clk_put(t7l66xb->clk48m); clk_put(t7l66xb->clk48m);
clk_disable_unprepare(t7l66xb->clk32k); clk_disable_unprepare(t7l66xb->clk32k);
@ -412,8 +409,7 @@ static int t7l66xb_remove(struct platform_device *dev)
mfd_remove_devices(&dev->dev); mfd_remove_devices(&dev->dev);
kfree(t7l66xb); kfree(t7l66xb);
return ret; return 0;
} }
static struct platform_driver t7l66xb_platform_driver = { static struct platform_driver t7l66xb_platform_driver = {

5
drivers/mfd/tc6393xb.c
View File

@ -798,20 +798,19 @@ static int tc6393xb_remove(struct platform_device *dev)
{ {
struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev); struct tc6393xb_platform_data *tcpd = dev_get_platdata(&dev->dev);
struct tc6393xb *tc6393xb = platform_get_drvdata(dev); struct tc6393xb *tc6393xb = platform_get_drvdata(dev);
int ret;
mfd_remove_devices(&dev->dev); mfd_remove_devices(&dev->dev);
tc6393xb_detach_irq(dev); tc6393xb_detach_irq(dev);
ret = tcpd->disable(dev); tcpd->disable(dev);
clk_disable_unprepare(tc6393xb->clk); clk_disable_unprepare(tc6393xb->clk);
iounmap(tc6393xb->scr); iounmap(tc6393xb->scr);
release_resource(&tc6393xb->rscr); release_resource(&tc6393xb->rscr);
clk_put(tc6393xb->clk); clk_put(tc6393xb->clk);
kfree(tc6393xb); kfree(tc6393xb);
return ret; return 0;
} }
#ifdef CONFIG_PM #ifdef CONFIG_PM

323
drivers/mfd/twl-core.c
View File

@ -656,309 +656,6 @@ static inline struct device *add_child(unsigned mod_no, const char *name,
can_wakeup, irq0, irq1); can_wakeup, irq0, irq1);
} }
static struct device *
add_regulator_linked(int num, struct regulator_init_data *pdata,
struct regulator_consumer_supply *consumers,
unsigned num_consumers, unsigned long features)
{
struct twl_regulator_driver_data drv_data;
/* regulator framework demands init_data ... */
if (!pdata)
return NULL;
if (consumers) {
pdata->consumer_supplies = consumers;
pdata->num_consumer_supplies = num_consumers;
}
if (pdata->driver_data) {
/* If we have existing drv_data, just add the flags */
struct twl_regulator_driver_data *tmp;
tmp = pdata->driver_data;
tmp->features |= features;
} else {
/* add new driver data struct, used only during init */
drv_data.features = features;
drv_data.set_voltage = NULL;
drv_data.get_voltage = NULL;
drv_data.data = NULL;
pdata->driver_data = &drv_data;
}
/* NOTE: we currently ignore regulator IRQs, e.g. for short circuits */
return add_numbered_child(TWL_MODULE_PM_MASTER, "twl_reg", num,
pdata, sizeof(*pdata), false, 0, 0);
}
static struct device *
add_regulator(int num, struct regulator_init_data *pdata,
unsigned long features)
{
return add_regulator_linked(num, pdata, NULL, 0, features);
}
/*
* NOTE: We know the first 8 IRQs after pdata->base_irq are
* for the PIH, and the next are for the PWR_INT SIH, since
* that's how twl_init_irq() sets things up.
*/
static int
add_children(struct twl4030_platform_data *pdata, unsigned irq_base,
unsigned long features)
{
struct device *child;
if (IS_ENABLED(CONFIG_GPIO_TWL4030) && pdata->gpio) {
child = add_child(TWL4030_MODULE_GPIO, "twl4030_gpio",
pdata->gpio, sizeof(*pdata->gpio),
false, irq_base + GPIO_INTR_OFFSET, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_KEYBOARD_TWL4030) && pdata->keypad) {
child = add_child(TWL4030_MODULE_KEYPAD, "twl4030_keypad",
pdata->keypad, sizeof(*pdata->keypad),
true, irq_base + KEYPAD_INTR_OFFSET, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_TWL4030_MADC) && pdata->madc &&
twl_class_is_4030()) {
child = add_child(TWL4030_MODULE_MADC, "twl4030_madc",
pdata->madc, sizeof(*pdata->madc),
true, irq_base + MADC_INTR_OFFSET, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_RTC_DRV_TWL4030)) {
/*
* REVISIT platform_data here currently might expose the
* "msecure" line ... but for now we just expect board
* setup to tell the chip "it's always ok to SET_TIME".
* Eventually, Linux might become more aware of such
* HW security concerns, and "least privilege".
*/
child = add_child(TWL_MODULE_RTC, "twl_rtc", NULL, 0,
true, irq_base + RTC_INTR_OFFSET, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_PWM_TWL)) {
child = add_child(TWL_MODULE_PWM, "twl-pwm", NULL, 0,
false, 0, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_PWM_TWL_LED)) {
child = add_child(TWL_MODULE_LED, "twl-pwmled", NULL, 0,
false, 0, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_TWL4030_USB) && pdata->usb &&
twl_class_is_4030()) {
static struct regulator_consumer_supply usb1v5 = {
.supply = "usb1v5",
};
static struct regulator_consumer_supply usb1v8 = {
.supply = "usb1v8",
};
static struct regulator_consumer_supply usb3v1 = {
.supply = "usb3v1",
};
/* First add the regulators so that they can be used by transceiver */
if (IS_ENABLED(CONFIG_REGULATOR_TWL4030)) {
/* this is a template that gets copied */
struct regulator_init_data usb_fixed = {
.constraints.valid_modes_mask =
REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.constraints.valid_ops_mask =
REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
};
child = add_regulator_linked(TWL4030_REG_VUSB1V5,
&usb_fixed, &usb1v5, 1,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator_linked(TWL4030_REG_VUSB1V8,
&usb_fixed, &usb1v8, 1,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator_linked(TWL4030_REG_VUSB3V1,
&usb_fixed, &usb3v1, 1,
features);
if (IS_ERR(child))
return PTR_ERR(child);
}
child = add_child(TWL_MODULE_USB, "twl4030_usb",
pdata->usb, sizeof(*pdata->usb), true,
/* irq0 = USB_PRES, irq1 = USB */
irq_base + USB_PRES_INTR_OFFSET,
irq_base + USB_INTR_OFFSET);
if (IS_ERR(child))
return PTR_ERR(child);
/* we need to connect regulators to this transceiver */
if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && child) {
usb1v5.dev_name = dev_name(child);
usb1v8.dev_name = dev_name(child);
usb3v1.dev_name = dev_name(child);
}
}
if (IS_ENABLED(CONFIG_TWL4030_WATCHDOG) && twl_class_is_4030()) {
child = add_child(TWL_MODULE_PM_RECEIVER, "twl4030_wdt", NULL,
0, false, 0, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_INPUT_TWL4030_PWRBUTTON) && twl_class_is_4030()) {
child = add_child(TWL_MODULE_PM_MASTER, "twl4030_pwrbutton",
NULL, 0, true, irq_base + 8 + 0, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_MFD_TWL4030_AUDIO) && pdata->audio &&
twl_class_is_4030()) {
child = add_child(TWL4030_MODULE_AUDIO_VOICE, "twl4030-audio",
pdata->audio, sizeof(*pdata->audio),
false, 0, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
/* twl4030 regulators */
if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && twl_class_is_4030()) {
child = add_regulator(TWL4030_REG_VPLL1, pdata->vpll1,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VIO, pdata->vio,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VDD1, pdata->vdd1,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VDD2, pdata->vdd2,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VMMC1, pdata->vmmc1,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VDAC, pdata->vdac,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator((features & TWL4030_VAUX2)
? TWL4030_REG_VAUX2_4030
: TWL4030_REG_VAUX2,
pdata->vaux2, features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VINTANA1, pdata->vintana1,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VINTANA2, pdata->vintana2,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VINTDIG, pdata->vintdig,
features);
if (IS_ERR(child))
return PTR_ERR(child);
}
/* maybe add LDOs that are omitted on cost-reduced parts */
if (IS_ENABLED(CONFIG_REGULATOR_TWL4030) && !(features & TPS_SUBSET)
&& twl_class_is_4030()) {
child = add_regulator(TWL4030_REG_VPLL2, pdata->vpll2,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VMMC2, pdata->vmmc2,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VSIM, pdata->vsim,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VAUX1, pdata->vaux1,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VAUX3, pdata->vaux3,
features);
if (IS_ERR(child))
return PTR_ERR(child);
child = add_regulator(TWL4030_REG_VAUX4, pdata->vaux4,
features);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_CHARGER_TWL4030) && pdata->bci &&
!(features & (TPS_SUBSET | TWL5031))) {
child = add_child(TWL_MODULE_MAIN_CHARGE, "twl4030_bci",
pdata->bci, sizeof(*pdata->bci), false,
/* irq0 = CHG_PRES, irq1 = BCI */
irq_base + BCI_PRES_INTR_OFFSET,
irq_base + BCI_INTR_OFFSET);
if (IS_ERR(child))
return PTR_ERR(child);
}
if (IS_ENABLED(CONFIG_TWL4030_POWER) && pdata->power) {
child = add_child(TWL_MODULE_PM_MASTER, "twl4030_power",
pdata->power, sizeof(*pdata->power), false,
0, 0);
if (IS_ERR(child))
return PTR_ERR(child);
}
return 0;
}
/*----------------------------------------------------------------------*/ /*----------------------------------------------------------------------*/
/* /*
@ -987,8 +684,7 @@ static inline int unprotect_pm_master(void)
return e; return e;
} }
static void clocks_init(struct device *dev, static void clocks_init(struct device *dev)
struct twl4030_clock_init_data *clock)
{ {
int e = 0; int e = 0;
struct clk *osc; struct clk *osc;
@ -1018,8 +714,6 @@ static void clocks_init(struct device *dev,
} }
ctrl |= HIGH_PERF_SQ; ctrl |= HIGH_PERF_SQ;
if (clock && clock->ck32k_lowpwr_enable)
ctrl |= CK32K_LOWPWR_EN;
e |= unprotect_pm_master(); e |= unprotect_pm_master();
/* effect->MADC+USB ck en */ /* effect->MADC+USB ck en */
@ -1063,7 +757,6 @@ static struct of_dev_auxdata twl_auxdata_lookup[] = {
static int static int
twl_probe(struct i2c_client *client, const struct i2c_device_id *id) twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
{ {
struct twl4030_platform_data *pdata = dev_get_platdata(&client->dev);
struct device_node *node = client->dev.of_node; struct device_node *node = client->dev.of_node;
struct platform_device *pdev; struct platform_device *pdev;
const struct regmap_config *twl_regmap_config; const struct regmap_config *twl_regmap_config;
@ -1071,7 +764,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
int status; int status;
unsigned i, num_slaves; unsigned i, num_slaves;
if (!node && !pdata) { if (!node) {
dev_err(&client->dev, "no platform data\n"); dev_err(&client->dev, "no platform data\n");
return -EINVAL; return -EINVAL;
} }
@ -1161,7 +854,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
twl_priv->ready = true; twl_priv->ready = true;
/* setup clock framework */ /* setup clock framework */
clocks_init(&client->dev, pdata ? pdata->clock : NULL); clocks_init(&client->dev);
/* read TWL IDCODE Register */ /* read TWL IDCODE Register */
if (twl_class_is_4030()) { if (twl_class_is_4030()) {
@ -1209,14 +902,8 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
TWL4030_DCDC_GLOBAL_CFG); TWL4030_DCDC_GLOBAL_CFG);
} }
if (node) { status = of_platform_populate(node, NULL, twl_auxdata_lookup,
if (pdata) &client->dev);
twl_auxdata_lookup[0].platform_data = pdata->gpio;
status = of_platform_populate(node, NULL, twl_auxdata_lookup,
&client->dev);
} else {
status = add_children(pdata, irq_base, id->driver_data);
}
fail: fail:
if (status < 0) if (status < 0)

4
include/linux/mfd/ipaq-micro.h
View File

@ -75,8 +75,8 @@ struct ipaq_micro_rxdev {
* @id: 4-bit ID of the message * @id: 4-bit ID of the message
* @tx_len: length of TX data * @tx_len: length of TX data
* @tx_data: TX data to send * @tx_data: TX data to send
* @rx_len: length of receieved RX data * @rx_len: length of received RX data
* @rx_data: RX data to recieve * @rx_data: RX data to receive
* @ack: a completion that will be completed when RX is complete * @ack: a completion that will be completed when RX is complete
* @node: list node if message gets queued * @node: list node if message gets queued
*/ */

2
include/linux/mfd/max77714.h
View File

@ -3,7 +3,7 @@
* Maxim MAX77714 Register and data structures definition. * Maxim MAX77714 Register and data structures definition.
* *
* Copyright (C) 2022 Luca Ceresoli * Copyright (C) 2022 Luca Ceresoli
* Author: Luca Ceresoli <luca@lucaceresoli.net> * Author: Luca Ceresoli <luca.ceresoli@bootlin.com>
*/ */
#ifndef __LINUX_MFD_MAX77714_H_ #ifndef __LINUX_MFD_MAX77714_H_

40
include/linux/mfd/mt6331/core.h Normal file
View File

@ -0,0 +1,40 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef __MFD_MT6331_CORE_H__
#define __MFD_MT6331_CORE_H__
enum mt6331_irq_status_numbers {
MT6331_IRQ_STATUS_PWRKEY = 0,
MT6331_IRQ_STATUS_HOMEKEY,
MT6331_IRQ_STATUS_CHRDET,
MT6331_IRQ_STATUS_THR_H,
MT6331_IRQ_STATUS_THR_L,
MT6331_IRQ_STATUS_BAT_H,
MT6331_IRQ_STATUS_BAT_L,
MT6331_IRQ_STATUS_RTC,
MT6331_IRQ_STATUS_AUDIO,
MT6331_IRQ_STATUS_MAD,
MT6331_IRQ_STATUS_ACCDET,
MT6331_IRQ_STATUS_ACCDET_EINT,
MT6331_IRQ_STATUS_ACCDET_NEGV = 12,
MT6331_IRQ_STATUS_VDVFS11_OC = 16,
MT6331_IRQ_STATUS_VDVFS12_OC,
MT6331_IRQ_STATUS_VDVFS13_OC,
MT6331_IRQ_STATUS_VDVFS14_OC,
MT6331_IRQ_STATUS_GPU_OC,
MT6331_IRQ_STATUS_VCORE1_OC,
MT6331_IRQ_STATUS_VCORE2_OC,
MT6331_IRQ_STATUS_VIO18_OC,
MT6331_IRQ_STATUS_LDO_OC,
MT6331_IRQ_STATUS_NR,
};
#define MT6331_IRQ_CON0_BASE MT6331_IRQ_STATUS_PWRKEY
#define MT6331_IRQ_CON0_BITS (MT6331_IRQ_STATUS_ACCDET_NEGV + 1)
#define MT6331_IRQ_CON1_BASE MT6331_IRQ_STATUS_VDVFS11_OC
#define MT6331_IRQ_CON1_BITS (MT6331_IRQ_STATUS_LDO_OC - MT6331_IRQ_STATUS_VDFS11_OC + 1)
#endif /* __MFD_MT6331_CORE_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef __MFD_MT6331_REGISTERS_H__
#define __MFD_MT6331_REGISTERS_H__
/* PMIC Registers */
#define MT6331_STRUP_CON0 0x0
#define MT6331_STRUP_CON2 0x2
#define MT6331_STRUP_CON3 0x4
#define MT6331_STRUP_CON4 0x6
#define MT6331_STRUP_CON5 0x8
#define MT6331_STRUP_CON6 0xA
#define MT6331_STRUP_CON7 0xC
#define MT6331_STRUP_CON8 0xE
#define MT6331_STRUP_CON9 0x10
#define MT6331_STRUP_CON10 0x12
#define MT6331_STRUP_CON11 0x14
#define MT6331_STRUP_CON12 0x16
#define MT6331_STRUP_CON13 0x18
#define MT6331_STRUP_CON14 0x1A
#define MT6331_STRUP_CON15 0x1C
#define MT6331_STRUP_CON16 0x1E
#define MT6331_STRUP_CON17 0x20
#define MT6331_STRUP_CON18 0x22
#define MT6331_HWCID 0x100
#define MT6331_SWCID 0x102
#define MT6331_EXT_PMIC_STATUS 0x104
#define MT6331_TOP_CON 0x106
#define MT6331_TEST_OUT 0x108
#define MT6331_TEST_CON0 0x10A
#define MT6331_TEST_CON1 0x10C
#define MT6331_TESTMODE_SW 0x10E
#define MT6331_EN_STATUS0 0x110
#define MT6331_EN_STATUS1 0x112
#define MT6331_EN_STATUS2 0x114
#define MT6331_OCSTATUS0 0x116
#define MT6331_OCSTATUS1 0x118
#define MT6331_OCSTATUS2 0x11A
#define MT6331_PGSTATUS 0x11C
#define MT6331_TOPSTATUS 0x11E
#define MT6331_TDSEL_CON 0x120
#define MT6331_RDSEL_CON 0x122
#define MT6331_SMT_CON0 0x124
#define MT6331_SMT_CON1 0x126
#define MT6331_SMT_CON2 0x128
#define MT6331_DRV_CON0 0x12A
#define MT6331_DRV_CON1 0x12C
#define MT6331_DRV_CON2 0x12E
#define MT6331_DRV_CON3 0x130
#define MT6331_TOP_STATUS 0x132
#define MT6331_TOP_STATUS_SET 0x134
#define MT6331_TOP_STATUS_CLR 0x136
#define MT6331_TOP_CKPDN_CON0 0x138
#define MT6331_TOP_CKPDN_CON0_SET 0x13A
#define MT6331_TOP_CKPDN_CON0_CLR 0x13C
#define MT6331_TOP_CKPDN_CON1 0x13E
#define MT6331_TOP_CKPDN_CON1_SET 0x140
#define MT6331_TOP_CKPDN_CON1_CLR 0x142
#define MT6331_TOP_CKPDN_CON2 0x144
#define MT6331_TOP_CKPDN_CON2_SET 0x146
#define MT6331_TOP_CKPDN_CON2_CLR 0x148
#define MT6331_TOP_CKSEL_CON 0x14A
#define MT6331_TOP_CKSEL_CON_SET 0x14C
#define MT6331_TOP_CKSEL_CON_CLR 0x14E
#define MT6331_TOP_CKHWEN_CON 0x150
#define MT6331_TOP_CKHWEN_CON_SET 0x152
#define MT6331_TOP_CKHWEN_CON_CLR 0x154
#define MT6331_TOP_CKTST_CON0 0x156
#define MT6331_TOP_CKTST_CON1 0x158
#define MT6331_TOP_CLKSQ 0x15A
#define MT6331_TOP_CLKSQ_SET 0x15C
#define MT6331_TOP_CLKSQ_CLR 0x15E
#define MT6331_TOP_RST_CON 0x160
#define MT6331_TOP_RST_CON_SET 0x162
#define MT6331_TOP_RST_CON_CLR 0x164
#define MT6331_TOP_RST_MISC 0x166
#define MT6331_TOP_RST_MISC_SET 0x168
#define MT6331_TOP_RST_MISC_CLR 0x16A
#define MT6331_INT_CON0 0x16C
#define MT6331_INT_CON0_SET 0x16E
#define MT6331_INT_CON0_CLR 0x170
#define MT6331_INT_CON1 0x172
#define MT6331_INT_CON1_SET 0x174
#define MT6331_INT_CON1_CLR 0x176
#define MT6331_INT_MISC_CON 0x178
#define MT6331_INT_MISC_CON_SET 0x17A
#define MT6331_INT_MISC_CON_CLR 0x17C
#define MT6331_INT_STATUS_CON0 0x17E
#define MT6331_INT_STATUS_CON1 0x180
#define MT6331_OC_GEAR_0 0x182
#define MT6331_FQMTR_CON0 0x184
#define MT6331_FQMTR_CON1 0x186
#define MT6331_FQMTR_CON2 0x188
#define MT6331_RG_SPI_CON 0x18A
#define MT6331_DEW_DIO_EN 0x18C
#define MT6331_DEW_READ_TEST 0x18E
#define MT6331_DEW_WRITE_TEST 0x190
#define MT6331_DEW_CRC_SWRST 0x192
#define MT6331_DEW_CRC_EN 0x194
#define MT6331_DEW_CRC_VAL 0x196
#define MT6331_DEW_DBG_MON_SEL 0x198
#define MT6331_DEW_CIPHER_KEY_SEL 0x19A
#define MT6331_DEW_CIPHER_IV_SEL 0x19C
#define MT6331_DEW_CIPHER_EN 0x19E
#define MT6331_DEW_CIPHER_RDY 0x1A0
#define MT6331_DEW_CIPHER_MODE 0x1A2
#define MT6331_DEW_CIPHER_SWRST 0x1A4
#define MT6331_DEW_RDDMY_NO 0x1A6
#define MT6331_INT_TYPE_CON0 0x1A8
#define MT6331_INT_TYPE_CON0_SET 0x1AA
#define MT6331_INT_TYPE_CON0_CLR 0x1AC
#define MT6331_INT_TYPE_CON1 0x1AE
#define MT6331_INT_TYPE_CON1_SET 0x1B0
#define MT6331_INT_TYPE_CON1_CLR 0x1B2
#define MT6331_INT_STA 0x1B4
#define MT6331_BUCK_ALL_CON0 0x200
#define MT6331_BUCK_ALL_CON1 0x202
#define MT6331_BUCK_ALL_CON2 0x204
#define MT6331_BUCK_ALL_CON3 0x206
#define MT6331_BUCK_ALL_CON4 0x208
#define MT6331_BUCK_ALL_CON5 0x20A
#define MT6331_BUCK_ALL_CON6 0x20C
#define MT6331_BUCK_ALL_CON7 0x20E
#define MT6331_BUCK_ALL_CON8 0x210
#define MT6331_BUCK_ALL_CON9 0x212
#define MT6331_BUCK_ALL_CON10 0x214
#define MT6331_BUCK_ALL_CON11 0x216
#define MT6331_BUCK_ALL_CON12 0x218
#define MT6331_BUCK_ALL_CON13 0x21A
#define MT6331_BUCK_ALL_CON14 0x21C
#define MT6331_BUCK_ALL_CON15 0x21E
#define MT6331_BUCK_ALL_CON16 0x220
#define MT6331_BUCK_ALL_CON17 0x222
#define MT6331_BUCK_ALL_CON18 0x224
#define MT6331_BUCK_ALL_CON19 0x226
#define MT6331_BUCK_ALL_CON20 0x228
#define MT6331_BUCK_ALL_CON21 0x22A
#define MT6331_BUCK_ALL_CON22 0x22C
#define MT6331_BUCK_ALL_CON23 0x22E
#define MT6331_BUCK_ALL_CON24 0x230
#define MT6331_BUCK_ALL_CON25 0x232
#define MT6331_BUCK_ALL_CON26 0x234
#define MT6331_VDVFS11_CON0 0x236
#define MT6331_VDVFS11_CON1 0x238
#define MT6331_VDVFS11_CON2 0x23A
#define MT6331_VDVFS11_CON3 0x23C
#define MT6331_VDVFS11_CON4 0x23E
#define MT6331_VDVFS11_CON5 0x240
#define MT6331_VDVFS11_CON6 0x242
#define MT6331_VDVFS11_CON7 0x244
#define MT6331_VDVFS11_CON8 0x246
#define MT6331_VDVFS11_CON9 0x248
#define MT6331_VDVFS11_CON10 0x24A
#define MT6331_VDVFS11_CON11 0x24C
#define MT6331_VDVFS11_CON12 0x24E
#define MT6331_VDVFS11_CON13 0x250
#define MT6331_VDVFS11_CON14 0x252
#define MT6331_VDVFS11_CON18 0x25A
#define MT6331_VDVFS11_CON19 0x25C
#define MT6331_VDVFS11_CON20 0x25E
#define MT6331_VDVFS11_CON21 0x260
#define MT6331_VDVFS11_CON22 0x262
#define MT6331_VDVFS11_CON23 0x264
#define MT6331_VDVFS11_CON24 0x266
#define MT6331_VDVFS11_CON25 0x268
#define MT6331_VDVFS11_CON26 0x26A
#define MT6331_VDVFS11_CON27 0x26C
#define MT6331_VDVFS12_CON0 0x26E
#define MT6331_VDVFS12_CON1 0x270
#define MT6331_VDVFS12_CON2 0x272
#define MT6331_VDVFS12_CON3 0x274
#define MT6331_VDVFS12_CON4 0x276
#define MT6331_VDVFS12_CON5 0x278
#define MT6331_VDVFS12_CON6 0x27A
#define MT6331_VDVFS12_CON7 0x27C
#define MT6331_VDVFS12_CON8 0x27E
#define MT6331_VDVFS12_CON9 0x280
#define MT6331_VDVFS12_CON10 0x282
#define MT6331_VDVFS12_CON11 0x284
#define MT6331_VDVFS12_CON12 0x286
#define MT6331_VDVFS12_CON13 0x288
#define MT6331_VDVFS12_CON14 0x28A
#define MT6331_VDVFS12_CON18 0x292
#define MT6331_VDVFS12_CON19 0x294
#define MT6331_VDVFS12_CON20 0x296
#define MT6331_VDVFS13_CON0 0x298
#define MT6331_VDVFS13_CON1 0x29A
#define MT6331_VDVFS13_CON2 0x29C
#define MT6331_VDVFS13_CON3 0x29E
#define MT6331_VDVFS13_CON4 0x2A0
#define MT6331_VDVFS13_CON5 0x2A2
#define MT6331_VDVFS13_CON6 0x2A4
#define MT6331_VDVFS13_CON7 0x2A6
#define MT6331_VDVFS13_CON8 0x2A8
#define MT6331_VDVFS13_CON9 0x2AA
#define MT6331_VDVFS13_CON10 0x2AC
#define MT6331_VDVFS13_CON11 0x2AE
#define MT6331_VDVFS13_CON12 0x2B0
#define MT6331_VDVFS13_CON13 0x2B2
#define MT6331_VDVFS13_CON14 0x2B4
#define MT6331_VDVFS13_CON18 0x2BC
#define MT6331_VDVFS13_CON19 0x2BE
#define MT6331_VDVFS13_CON20 0x2C0
#define MT6331_VDVFS14_CON0 0x2C2
#define MT6331_VDVFS14_CON1 0x2C4
#define MT6331_VDVFS14_CON2 0x2C6
#define MT6331_VDVFS14_CON3 0x2C8
#define MT6331_VDVFS14_CON4 0x2CA
#define MT6331_VDVFS14_CON5 0x2CC
#define MT6331_VDVFS14_CON6 0x2CE
#define MT6331_VDVFS14_CON7 0x2D0
#define MT6331_VDVFS14_CON8 0x2D2
#define MT6331_VDVFS14_CON9 0x2D4
#define MT6331_VDVFS14_CON10 0x2D6
#define MT6331_VDVFS14_CON11 0x2D8
#define MT6331_VDVFS14_CON12 0x2DA
#define MT6331_VDVFS14_CON13 0x2DC
#define MT6331_VDVFS14_CON14 0x2DE
#define MT6331_VDVFS14_CON18 0x2E6
#define MT6331_VDVFS14_CON19 0x2E8
#define MT6331_VDVFS14_CON20 0x2EA
#define MT6331_VGPU_CON0 0x300
#define MT6331_VGPU_CON1 0x302
#define MT6331_VGPU_CON2 0x304
#define MT6331_VGPU_CON3 0x306
#define MT6331_VGPU_CON4 0x308
#define MT6331_VGPU_CON5 0x30A
#define MT6331_VGPU_CON6 0x30C
#define MT6331_VGPU_CON7 0x30E
#define MT6331_VGPU_CON8 0x310
#define MT6331_VGPU_CON9 0x312
#define MT6331_VGPU_CON10 0x314
#define MT6331_VGPU_CON11 0x316
#define MT6331_VGPU_CON12 0x318
#define MT6331_VGPU_CON13 0x31A
#define MT6331_VGPU_CON14 0x31C
#define MT6331_VGPU_CON15 0x31E
#define MT6331_VGPU_CON16 0x320
#define MT6331_VGPU_CON17 0x322
#define MT6331_VGPU_CON18 0x324
#define MT6331_VGPU_CON19 0x326
#define MT6331_VGPU_CON20 0x328
#define MT6331_VCORE1_CON0 0x32A
#define MT6331_VCORE1_CON1 0x32C
#define MT6331_VCORE1_CON2 0x32E
#define MT6331_VCORE1_CON3 0x330
#define MT6331_VCORE1_CON4 0x332
#define MT6331_VCORE1_CON5 0x334
#define MT6331_VCORE1_CON6 0x336
#define MT6331_VCORE1_CON7 0x338
#define MT6331_VCORE1_CON8 0x33A
#define MT6331_VCORE1_CON9 0x33C
#define MT6331_VCORE1_CON10 0x33E
#define MT6331_VCORE1_CON11 0x340
#define MT6331_VCORE1_CON12 0x342
#define MT6331_VCORE1_CON13 0x344
#define MT6331_VCORE1_CON14 0x346
#define MT6331_VCORE1_CON15 0x348
#define MT6331_VCORE1_CON16 0x34A
#define MT6331_VCORE1_CON17 0x34C
#define MT6331_VCORE1_CON18 0x34E
#define MT6331_VCORE1_CON19 0x350
#define MT6331_VCORE1_CON20 0x352
#define MT6331_VCORE2_CON0 0x354
#define MT6331_VCORE2_CON1 0x356
#define MT6331_VCORE2_CON2 0x358
#define MT6331_VCORE2_CON3 0x35A
#define MT6331_VCORE2_CON4 0x35C
#define MT6331_VCORE2_CON5 0x35E
#define MT6331_VCORE2_CON6 0x360
#define MT6331_VCORE2_CON7 0x362
#define MT6331_VCORE2_CON8 0x364
#define MT6331_VCORE2_CON9 0x366
#define MT6331_VCORE2_CON10 0x368
#define MT6331_VCORE2_CON11 0x36A
#define MT6331_VCORE2_CON12 0x36C
#define MT6331_VCORE2_CON13 0x36E
#define MT6331_VCORE2_CON14 0x370
#define MT6331_VCORE2_CON15 0x372
#define MT6331_VCORE2_CON16 0x374
#define MT6331_VCORE2_CON17 0x376
#define MT6331_VCORE2_CON18 0x378
#define MT6331_VCORE2_CON19 0x37A
#define MT6331_VCORE2_CON20 0x37C
#define MT6331_VCORE2_CON21 0x37E
#define MT6331_VIO18_CON0 0x380
#define MT6331_VIO18_CON1 0x382
#define MT6331_VIO18_CON2 0x384
#define MT6331_VIO18_CON3 0x386
#define MT6331_VIO18_CON4 0x388
#define MT6331_VIO18_CON5 0x38A
#define MT6331_VIO18_CON6 0x38C
#define MT6331_VIO18_CON7 0x38E
#define MT6331_VIO18_CON8 0x390
#define MT6331_VIO18_CON9 0x392
#define MT6331_VIO18_CON10 0x394
#define MT6331_VIO18_CON11 0x396
#define MT6331_VIO18_CON12 0x398
#define MT6331_VIO18_CON13 0x39A
#define MT6331_VIO18_CON14 0x39C
#define MT6331_VIO18_CON15 0x39E
#define MT6331_VIO18_CON16 0x3A0
#define MT6331_VIO18_CON17 0x3A2
#define MT6331_VIO18_CON18 0x3A4
#define MT6331_VIO18_CON19 0x3A6
#define MT6331_VIO18_CON20 0x3A8
#define MT6331_BUCK_K_CON0 0x3AA
#define MT6331_BUCK_K_CON1 0x3AC
#define MT6331_BUCK_K_CON2 0x3AE
#define MT6331_BUCK_K_CON3 0x3B0
#define MT6331_ZCD_CON0 0x400
#define MT6331_ZCD_CON1 0x402
#define MT6331_ZCD_CON2 0x404
#define MT6331_ZCD_CON3 0x406
#define MT6331_ZCD_CON4 0x408
#define MT6331_ZCD_CON5 0x40A
#define MT6331_ISINK0_CON0 0x40C
#define MT6331_ISINK0_CON1 0x40E
#define MT6331_ISINK0_CON2 0x410
#define MT6331_ISINK0_CON3 0x412
#define MT6331_ISINK0_CON4 0x414
#define MT6331_ISINK1_CON0 0x416
#define MT6331_ISINK1_CON1 0x418
#define MT6331_ISINK1_CON2 0x41A
#define MT6331_ISINK1_CON3 0x41C
#define MT6331_ISINK1_CON4 0x41E
#define MT6331_ISINK2_CON0 0x420
#define MT6331_ISINK2_CON1 0x422
#define MT6331_ISINK2_CON2 0x424
#define MT6331_ISINK2_CON3 0x426
#define MT6331_ISINK2_CON4 0x428
#define MT6331_ISINK3_CON0 0x42A
#define MT6331_ISINK3_CON1 0x42C
#define MT6331_ISINK3_CON2 0x42E
#define MT6331_ISINK3_CON3 0x430
#define MT6331_ISINK3_CON4 0x432
#define MT6331_ISINK_ANA0 0x434
#define MT6331_ISINK_ANA1 0x436
#define MT6331_ISINK_PHASE_DLY 0x438
#define MT6331_ISINK_EN_CTRL 0x43A
#define MT6331_ANALDO_CON0 0x500
#define MT6331_ANALDO_CON1 0x502
#define MT6331_ANALDO_CON2 0x504
#define MT6331_ANALDO_CON3 0x506
#define MT6331_ANALDO_CON4 0x508
#define MT6331_ANALDO_CON5 0x50A
#define MT6331_ANALDO_CON6 0x50C
#define MT6331_ANALDO_CON7 0x50E
#define MT6331_ANALDO_CON8 0x510
#define MT6331_ANALDO_CON9 0x512
#define MT6331_ANALDO_CON10 0x514
#define MT6331_ANALDO_CON11 0x516
#define MT6331_ANALDO_CON12 0x518
#define MT6331_ANALDO_CON13 0x51A
#define MT6331_SYSLDO_CON0 0x51C
#define MT6331_SYSLDO_CON1 0x51E
#define MT6331_SYSLDO_CON2 0x520
#define MT6331_SYSLDO_CON3 0x522
#define MT6331_SYSLDO_CON4 0x524
#define MT6331_SYSLDO_CON5 0x526
#define MT6331_SYSLDO_CON6 0x528
#define MT6331_SYSLDO_CON7 0x52A
#define MT6331_SYSLDO_CON8 0x52C
#define MT6331_SYSLDO_CON9 0x52E
#define MT6331_SYSLDO_CON10 0x530
#define MT6331_SYSLDO_CON11 0x532
#define MT6331_SYSLDO_CON12 0x534
#define MT6331_SYSLDO_CON13 0x536
#define MT6331_SYSLDO_CON14 0x538
#define MT6331_SYSLDO_CON15 0x53A
#define MT6331_SYSLDO_CON16 0x53C
#define MT6331_SYSLDO_CON17 0x53E
#define MT6331_SYSLDO_CON18 0x540
#define MT6331_SYSLDO_CON19 0x542
#define MT6331_SYSLDO_CON20 0x544
#define MT6331_SYSLDO_CON21 0x546
#define MT6331_DIGLDO_CON0 0x548
#define MT6331_DIGLDO_CON1 0x54A
#define MT6331_DIGLDO_CON2 0x54C
#define MT6331_DIGLDO_CON3 0x54E
#define MT6331_DIGLDO_CON4 0x550
#define MT6331_DIGLDO_CON5 0x552
#define MT6331_DIGLDO_CON6 0x554
#define MT6331_DIGLDO_CON7 0x556
#define MT6331_DIGLDO_CON8 0x558
#define MT6331_DIGLDO_CON9 0x55A
#define MT6331_DIGLDO_CON10 0x55C
#define MT6331_DIGLDO_CON11 0x55E
#define MT6331_DIGLDO_CON12 0x560
#define MT6331_DIGLDO_CON13 0x562
#define MT6331_DIGLDO_CON14 0x564
#define MT6331_DIGLDO_CON15 0x566
#define MT6331_DIGLDO_CON16 0x568
#define MT6331_DIGLDO_CON17 0x56A
#define MT6331_DIGLDO_CON18 0x56C
#define MT6331_DIGLDO_CON19 0x56E
#define MT6331_DIGLDO_CON20 0x570
#define MT6331_DIGLDO_CON21 0x572
#define MT6331_DIGLDO_CON22 0x574
#define MT6331_DIGLDO_CON23 0x576
#define MT6331_DIGLDO_CON24 0x578
#define MT6331_DIGLDO_CON25 0x57A
#define MT6331_DIGLDO_CON26 0x57C
#define MT6331_DIGLDO_CON27 0x57E
#define MT6331_DIGLDO_CON28 0x580
#define MT6331_OTP_CON0 0x600
#define MT6331_OTP_CON1 0x602
#define MT6331_OTP_CON2 0x604
#define MT6331_OTP_CON3 0x606
#define MT6331_OTP_CON4 0x608
#define MT6331_OTP_CON5 0x60A
#define MT6331_OTP_CON6 0x60C
#define MT6331_OTP_CON7 0x60E
#define MT6331_OTP_CON8 0x610
#define MT6331_OTP_CON9 0x612
#define MT6331_OTP_CON10 0x614
#define MT6331_OTP_CON11 0x616
#define MT6331_OTP_CON12 0x618
#define MT6331_OTP_CON13 0x61A
#define MT6331_OTP_CON14 0x61C
#define MT6331_OTP_DOUT_0_15 0x61E
#define MT6331_OTP_DOUT_16_31 0x620
#define MT6331_OTP_DOUT_32_47 0x622
#define MT6331_OTP_DOUT_48_63 0x624
#define MT6331_OTP_DOUT_64_79 0x626
#define MT6331_OTP_DOUT_80_95 0x628
#define MT6331_OTP_DOUT_96_111 0x62A
#define MT6331_OTP_DOUT_112_127 0x62C
#define MT6331_OTP_DOUT_128_143 0x62E
#define MT6331_OTP_DOUT_144_159 0x630
#define MT6331_OTP_DOUT_160_175 0x632
#define MT6331_OTP_DOUT_176_191 0x634
#define MT6331_OTP_DOUT_192_207 0x636
#define MT6331_OTP_DOUT_208_223 0x638
#define MT6331_OTP_DOUT_224_239 0x63A
#define MT6331_OTP_DOUT_240_255 0x63C
#define MT6331_OTP_VAL_0_15 0x63E
#define MT6331_OTP_VAL_16_31 0x640
#define MT6331_OTP_VAL_32_47 0x642
#define MT6331_OTP_VAL_48_63 0x644
#define MT6331_OTP_VAL_64_79 0x646
#define MT6331_OTP_VAL_80_95 0x648
#define MT6331_OTP_VAL_96_111 0x64A
#define MT6331_OTP_VAL_112_127 0x64C
#define MT6331_OTP_VAL_128_143 0x64E
#define MT6331_OTP_VAL_144_159 0x650
#define MT6331_OTP_VAL_160_175 0x652
#define MT6331_OTP_VAL_176_191 0x654
#define MT6331_OTP_VAL_192_207 0x656
#define MT6331_OTP_VAL_208_223 0x658
#define MT6331_OTP_VAL_224_239 0x65A
#define MT6331_OTP_VAL_240_255 0x65C
#define MT6331_RTC_MIX_CON0 0x65E
#define MT6331_RTC_MIX_CON1 0x660
#define MT6331_AUDDAC_CFG0 0x662
#define MT6331_AUDBUF_CFG0 0x664
#define MT6331_AUDBUF_CFG1 0x666
#define MT6331_AUDBUF_CFG2 0x668
#define MT6331_AUDBUF_CFG3 0x66A
#define MT6331_AUDBUF_CFG4 0x66C
#define MT6331_AUDBUF_CFG5 0x66E
#define MT6331_AUDBUF_CFG6 0x670
#define MT6331_AUDBUF_CFG7 0x672
#define MT6331_AUDBUF_CFG8 0x674
#define MT6331_IBIASDIST_CFG0 0x676
#define MT6331_AUDCLKGEN_CFG0 0x678
#define MT6331_AUDLDO_CFG0 0x67A
#define MT6331_AUDDCDC_CFG0 0x67C
#define MT6331_AUDDCDC_CFG1 0x67E
#define MT6331_AUDNVREGGLB_CFG0 0x680
#define MT6331_AUD_NCP0 0x682
#define MT6331_AUD_ZCD_CFG0 0x684
#define MT6331_AUDPREAMP_CFG0 0x686
#define MT6331_AUDPREAMP_CFG1 0x688
#define MT6331_AUDPREAMP_CFG2 0x68A
#define MT6331_AUDADC_CFG0 0x68C
#define MT6331_AUDADC_CFG1 0x68E
#define MT6331_AUDADC_CFG2 0x690
#define MT6331_AUDADC_CFG3 0x692
#define MT6331_AUDADC_CFG4 0x694
#define MT6331_AUDADC_CFG5 0x696
#define MT6331_AUDDIGMI_CFG0 0x698
#define MT6331_AUDDIGMI_CFG1 0x69A
#define MT6331_AUDMICBIAS_CFG0 0x69C
#define MT6331_AUDMICBIAS_CFG1 0x69E
#define MT6331_AUDENCSPARE_CFG0 0x6A0
#define MT6331_AUDPREAMPGAIN_CFG0 0x6A2
#define MT6331_AUDMADPLL_CFG0 0x6A4
#define MT6331_AUDMADPLL_CFG1 0x6A6
#define MT6331_AUDMADPLL_CFG2 0x6A8
#define MT6331_AUDLDO_NVREG_CFG0 0x6AA
#define MT6331_AUDLDO_NVREG_CFG1 0x6AC
#define MT6331_AUDLDO_NVREG_CFG2 0x6AE
#define MT6331_AUXADC_ADC0 0x700
#define MT6331_AUXADC_ADC1 0x702
#define MT6331_AUXADC_ADC2 0x704
#define MT6331_AUXADC_ADC3 0x706
#define MT6331_AUXADC_ADC4 0x708
#define MT6331_AUXADC_ADC5 0x70A
#define MT6331_AUXADC_ADC6 0x70C
#define MT6331_AUXADC_ADC7 0x70E
#define MT6331_AUXADC_ADC8 0x710
#define MT6331_AUXADC_ADC9 0x712
#define MT6331_AUXADC_ADC10 0x714
#define MT6331_AUXADC_ADC11 0x716
#define MT6331_AUXADC_ADC12 0x718
#define MT6331_AUXADC_ADC13 0x71A
#define MT6331_AUXADC_ADC14 0x71C
#define MT6331_AUXADC_ADC15 0x71E
#define MT6331_AUXADC_ADC16 0x720
#define MT6331_AUXADC_ADC17 0x722
#define MT6331_AUXADC_ADC18 0x724
#define MT6331_AUXADC_ADC19 0x726
#define MT6331_AUXADC_STA0 0x728
#define MT6331_AUXADC_STA1 0x72A
#define MT6331_AUXADC_RQST0 0x72C
#define MT6331_AUXADC_RQST0_SET 0x72E
#define MT6331_AUXADC_RQST0_CLR 0x730
#define MT6331_AUXADC_RQST1 0x732
#define MT6331_AUXADC_RQST1_SET 0x734
#define MT6331_AUXADC_RQST1_CLR 0x736
#define MT6331_AUXADC_CON0 0x738
#define MT6331_AUXADC_CON1 0x73A
#define MT6331_AUXADC_CON2 0x73C
#define MT6331_AUXADC_CON3 0x73E
#define MT6331_AUXADC_CON4 0x740
#define MT6331_AUXADC_CON5 0x742
#define MT6331_AUXADC_CON6 0x744
#define MT6331_AUXADC_CON7 0x746
#define MT6331_AUXADC_CON8 0x748
#define MT6331_AUXADC_CON9 0x74A
#define MT6331_AUXADC_CON10 0x74C
#define MT6331_AUXADC_CON11 0x74E
#define MT6331_AUXADC_CON12 0x750
#define MT6331_AUXADC_CON13 0x752
#define MT6331_AUXADC_CON14 0x754
#define MT6331_AUXADC_CON15 0x756
#define MT6331_AUXADC_CON16 0x758
#define MT6331_AUXADC_CON17 0x75A
#define MT6331_AUXADC_CON18 0x75C
#define MT6331_AUXADC_CON19 0x75E
#define MT6331_AUXADC_CON20 0x760
#define MT6331_AUXADC_CON21 0x762
#define MT6331_AUXADC_CON22 0x764
#define MT6331_AUXADC_CON23 0x766
#define MT6331_AUXADC_CON24 0x768
#define MT6331_AUXADC_CON25 0x76A
#define MT6331_AUXADC_CON26 0x76C
#define MT6331_AUXADC_CON27 0x76E
#define MT6331_AUXADC_CON28 0x770
#define MT6331_AUXADC_CON29 0x772
#define MT6331_AUXADC_CON30 0x774
#define MT6331_AUXADC_CON31 0x776
#define MT6331_AUXADC_CON32 0x778
#define MT6331_ACCDET_CON0 0x77A
#define MT6331_ACCDET_CON1 0x77C
#define MT6331_ACCDET_CON2 0x77E
#define MT6331_ACCDET_CON3 0x780
#define MT6331_ACCDET_CON4 0x782
#define MT6331_ACCDET_CON5 0x784
#define MT6331_ACCDET_CON6 0x786
#define MT6331_ACCDET_CON7 0x788
#define MT6331_ACCDET_CON8 0x78A
#define MT6331_ACCDET_CON9 0x78C
#define MT6331_ACCDET_CON10 0x78E
#define MT6331_ACCDET_CON11 0x790
#define MT6331_ACCDET_CON12 0x792
#define MT6331_ACCDET_CON13 0x794
#define MT6331_ACCDET_CON14 0x796
#define MT6331_ACCDET_CON15 0x798
#define MT6331_ACCDET_CON16 0x79A
#define MT6331_ACCDET_CON17 0x79C
#define MT6331_ACCDET_CON18 0x79E
#define MT6331_ACCDET_CON19 0x7A0
#define MT6331_ACCDET_CON20 0x7A2
#define MT6331_ACCDET_CON21 0x7A4
#define MT6331_ACCDET_CON22 0x7A6
#define MT6331_ACCDET_CON23 0x7A8
#define MT6331_ACCDET_CON24 0x7AA
#endif /* __MFD_MT6331_REGISTERS_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef __MFD_MT6332_CORE_H__
#define __MFD_MT6332_CORE_H__
enum mt6332_irq_status_numbers {
MT6332_IRQ_STATUS_CHR_COMPLETE = 0,
MT6332_IRQ_STATUS_THERMAL_SD,
MT6332_IRQ_STATUS_THERMAL_REG_IN,
MT6332_IRQ_STATUS_THERMAL_REG_OUT,
MT6332_IRQ_STATUS_OTG_OC,
MT6332_IRQ_STATUS_CHR_OC,
MT6332_IRQ_STATUS_OTG_THERMAL,
MT6332_IRQ_STATUS_CHRIN_SHORT,
MT6332_IRQ_STATUS_DRVCDT_SHORT,
MT6332_IRQ_STATUS_PLUG_IN_FLASH,
MT6332_IRQ_STATUS_CHRWDT_FLAG,
MT6332_IRQ_STATUS_FLASH_EN_TIMEOUT,
MT6332_IRQ_STATUS_FLASH_VLED1_SHORT,
MT6332_IRQ_STATUS_FLASH_VLED1_OPEN = 13,
MT6332_IRQ_STATUS_OV = 16,
MT6332_IRQ_STATUS_BVALID_DET,
MT6332_IRQ_STATUS_VBATON_UNDET,
MT6332_IRQ_STATUS_CHR_PLUG_IN,
MT6332_IRQ_STATUS_CHR_PLUG_OUT,
MT6332_IRQ_STATUS_BC11_TIMEOUT,
MT6332_IRQ_STATUS_FLASH_VLED2_SHORT,
MT6332_IRQ_STATUS_FLASH_VLED2_OPEN = 23,
MT6332_IRQ_STATUS_THR_H = 32,
MT6332_IRQ_STATUS_THR_L,
MT6332_IRQ_STATUS_BAT_H,
MT6332_IRQ_STATUS_BAT_L,
MT6332_IRQ_STATUS_M3_H,
MT6332_IRQ_STATUS_M3_L,
MT6332_IRQ_STATUS_FG_BAT_H,
MT6332_IRQ_STATUS_FG_BAT_L,
MT6332_IRQ_STATUS_FG_CUR_H,
MT6332_IRQ_STATUS_FG_CUR_L,
MT6332_IRQ_STATUS_SPKL_D,
MT6332_IRQ_STATUS_SPKL_AB,
MT6332_IRQ_STATUS_BIF,
MT6332_IRQ_STATUS_VWLED_OC = 45,
MT6332_IRQ_STATUS_VDRAM_OC = 48,
MT6332_IRQ_STATUS_VDVFS2_OC,
MT6332_IRQ_STATUS_VRF1_OC,
MT6332_IRQ_STATUS_VRF2_OC,
MT6332_IRQ_STATUS_VPA_OC,
MT6332_IRQ_STATUS_VSBST_OC,
MT6332_IRQ_STATUS_LDO_OC,
MT6332_IRQ_STATUS_NR,
};
#define MT6332_IRQ_CON0_BASE MT6332_IRQ_STATUS_CHR_COMPLETE
#define MT6332_IRQ_CON0_BITS (MT6332_IRQ_STATUS_FLASH_VLED1_OPEN + 1)
#define MT6332_IRQ_CON1_BASE MT6332_IRQ_STATUS_OV
#define MT6332_IRQ_CON1_BITS (MT6332_IRQ_STATUS_FLASH_VLED2_OPEN - MT6332_IRQ_STATUS_OV + 1)
#define MT6332_IRQ_CON2_BASE MT6332_IRQ_STATUS_THR_H
#define MT6332_IRQ_CON2_BITS (MT6332_IRQ_STATUS_VWLED_OC - MT6332_IRQ_STATUS_THR_H + 1)
#define MT6332_IRQ_CON3_BASE MT6332_IRQ_STATUS_VDRAM_OC
#define MT6332_IRQ_CON3_BITS (MT6332_IRQ_STATUS_LDO_OC - MT6332_IRQ_STATUS_VDRAM_OC + 1)
#endif /* __MFD_MT6332_CORE_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#ifndef __MFD_MT6332_REGISTERS_H__
#define __MFD_MT6332_REGISTERS_H__
/* PMIC Registers */
#define MT6332_HWCID 0x8000
#define MT6332_SWCID 0x8002
#define MT6332_TOP_CON 0x8004
#define MT6332_DDR_VREF_AP_CON 0x8006
#define MT6332_DDR_VREF_DQ_CON 0x8008
#define MT6332_DDR_VREF_CA_CON 0x800A
#define MT6332_TEST_OUT 0x800C
#define MT6332_TEST_CON0 0x800E
#define MT6332_TEST_CON1 0x8010
#define MT6332_TESTMODE_SW 0x8012
#define MT6332_TESTMODE_ANA 0x8014
#define MT6332_TDSEL_CON 0x8016
#define MT6332_RDSEL_CON 0x8018
#define MT6332_SMT_CON0 0x801A
#define MT6332_SMT_CON1 0x801C
#define MT6332_DRV_CON0 0x801E
#define MT6332_DRV_CON1 0x8020
#define MT6332_DRV_CON2 0x8022
#define MT6332_EN_STATUS0 0x8024
#define MT6332_OCSTATUS0 0x8026
#define MT6332_TOP_STATUS 0x8028
#define MT6332_TOP_STATUS_SET 0x802A
#define MT6332_TOP_STATUS_CLR 0x802C
#define MT6332_FLASH_CON0 0x802E
#define MT6332_FLASH_CON1 0x8030
#define MT6332_FLASH_CON2 0x8032
#define MT6332_CORE_CON0 0x8034
#define MT6332_CORE_CON1 0x8036
#define MT6332_CORE_CON2 0x8038
#define MT6332_CORE_CON3 0x803A
#define MT6332_CORE_CON4 0x803C
#define MT6332_CORE_CON5 0x803E
#define MT6332_CORE_CON6 0x8040
#define MT6332_CORE_CON7 0x8042
#define MT6332_CORE_CON8 0x8044
#define MT6332_CORE_CON9 0x8046
#define MT6332_CORE_CON10 0x8048
#define MT6332_CORE_CON11 0x804A
#define MT6332_CORE_CON12 0x804C
#define MT6332_CORE_CON13 0x804E
#define MT6332_CORE_CON14 0x8050
#define MT6332_CORE_CON15 0x8052
#define MT6332_STA_CON0 0x8054
#define MT6332_STA_CON1 0x8056
#define MT6332_STA_CON2 0x8058
#define MT6332_STA_CON3 0x805A
#define MT6332_STA_CON4 0x805C
#define MT6332_STA_CON5 0x805E
#define MT6332_STA_CON6 0x8060
#define MT6332_STA_CON7 0x8062
#define MT6332_CHR_CON0 0x8064
#define MT6332_CHR_CON1 0x8066
#define MT6332_CHR_CON2 0x8068
#define MT6332_CHR_CON3 0x806A
#define MT6332_CHR_CON4 0x806C
#define MT6332_CHR_CON5 0x806E
#define MT6332_CHR_CON6 0x8070
#define MT6332_CHR_CON7 0x8072
#define MT6332_CHR_CON8 0x8074
#define MT6332_CHR_CON9 0x8076
#define MT6332_CHR_CON10 0x8078
#define MT6332_CHR_CON11 0x807A
#define MT6332_CHR_CON12 0x807C
#define MT6332_CHR_CON13 0x807E
#define MT6332_CHR_CON14 0x8080
#define MT6332_CHR_CON15 0x8082
#define MT6332_BOOST_CON0 0x8084
#define MT6332_BOOST_CON1 0x8086
#define MT6332_BOOST_CON2 0x8088
#define MT6332_BOOST_CON3 0x808A
#define MT6332_BOOST_CON4 0x808C
#define MT6332_BOOST_CON5 0x808E
#define MT6332_BOOST_CON6 0x8090
#define MT6332_BOOST_CON7 0x8092
#define MT6332_TOP_CKPDN_CON0 0x8094
#define MT6332_TOP_CKPDN_CON0_SET 0x8096
#define MT6332_TOP_CKPDN_CON0_CLR 0x8098
#define MT6332_TOP_CKPDN_CON1 0x809A
#define MT6332_TOP_CKPDN_CON1_SET 0x809C
#define MT6332_TOP_CKPDN_CON1_CLR 0x809E
#define MT6332_TOP_CKPDN_CON2 0x80A0
#define MT6332_TOP_CKPDN_CON2_SET 0x80A2
#define MT6332_TOP_CKPDN_CON2_CLR 0x80A4
#define MT6332_TOP_CKSEL_CON0 0x80A6
#define MT6332_TOP_CKSEL_CON0_SET 0x80A8
#define MT6332_TOP_CKSEL_CON0_CLR 0x80AA
#define MT6332_TOP_CKSEL_CON1 0x80AC
#define MT6332_TOP_CKSEL_CON1_SET 0x80AE
#define MT6332_TOP_CKSEL_CON1_CLR 0x80B0
#define MT6332_TOP_CKHWEN_CON 0x80B2
#define MT6332_TOP_CKHWEN_CON_SET 0x80B4
#define MT6332_TOP_CKHWEN_CON_CLR 0x80B6
#define MT6332_TOP_CKTST_CON0 0x80B8
#define MT6332_TOP_CKTST_CON1 0x80BA
#define MT6332_TOP_RST_CON 0x80BC
#define MT6332_TOP_RST_CON_SET 0x80BE
#define MT6332_TOP_RST_CON_CLR 0x80C0
#define MT6332_TOP_RST_MISC 0x80C2
#define MT6332_TOP_RST_MISC_SET 0x80C4
#define MT6332_TOP_RST_MISC_CLR 0x80C6
#define MT6332_INT_CON0 0x80C8
#define MT6332_INT_CON0_SET 0x80CA
#define MT6332_INT_CON0_CLR 0x80CC
#define MT6332_INT_CON1 0x80CE
#define MT6332_INT_CON1_SET 0x80D0
#define MT6332_INT_CON1_CLR 0x80D2
#define MT6332_INT_CON2 0x80D4
#define MT6332_INT_CON2_SET 0x80D6
#define MT6332_INT_CON2_CLR 0x80D8
#define MT6332_INT_CON3 0x80DA
#define MT6332_INT_CON3_SET 0x80DC
#define MT6332_INT_CON3_CLR 0x80DE
#define MT6332_CHRWDT_CON0 0x80E0
#define MT6332_CHRWDT_STATUS0 0x80E2
#define MT6332_INT_STATUS0 0x80E4
#define MT6332_INT_STATUS1 0x80E6
#define MT6332_INT_STATUS2 0x80E8
#define MT6332_INT_STATUS3 0x80EA
#define MT6332_OC_GEAR_0 0x80EC
#define MT6332_OC_GEAR_1 0x80EE
#define MT6332_OC_GEAR_2 0x80F0
#define MT6332_INT_MISC_CON 0x80F2
#define MT6332_RG_SPI_CON 0x80F4
#define MT6332_DEW_DIO_EN 0x80F6
#define MT6332_DEW_READ_TEST 0x80F8
#define MT6332_DEW_WRITE_TEST 0x80FA
#define MT6332_DEW_CRC_SWRST 0x80FC
#define MT6332_DEW_CRC_EN 0x80FE
#define MT6332_DEW_CRC_VAL 0x8100
#define MT6332_DEW_DBG_MON_SEL 0x8102
#define MT6332_DEW_CIPHER_KEY_SEL 0x8104
#define MT6332_DEW_CIPHER_IV_SEL 0x8106
#define MT6332_DEW_CIPHER_EN 0x8108
#define MT6332_DEW_CIPHER_RDY 0x810A
#define MT6332_DEW_CIPHER_MODE 0x810C
#define MT6332_DEW_CIPHER_SWRST 0x810E
#define MT6332_DEW_RDDMY_NO 0x8110
#define MT6332_INT_STA 0x8112
#define MT6332_BIF_CON0 0x8114
#define MT6332_BIF_CON1 0x8116
#define MT6332_BIF_CON2 0x8118
#define MT6332_BIF_CON3 0x811A
#define MT6332_BIF_CON4 0x811C
#define MT6332_BIF_CON5 0x811E
#define MT6332_BIF_CON6 0x8120
#define MT6332_BIF_CON7 0x8122
#define MT6332_BIF_CON8 0x8124
#define MT6332_BIF_CON9 0x8126
#define MT6332_BIF_CON10 0x8128
#define MT6332_BIF_CON11 0x812A
#define MT6332_BIF_CON12 0x812C
#define MT6332_BIF_CON13 0x812E
#define MT6332_BIF_CON14 0x8130
#define MT6332_BIF_CON15 0x8132
#define MT6332_BIF_CON16 0x8134
#define MT6332_BIF_CON17 0x8136
#define MT6332_BIF_CON18 0x8138
#define MT6332_BIF_CON19 0x813A
#define MT6332_BIF_CON20 0x813C
#define MT6332_BIF_CON21 0x813E
#define MT6332_BIF_CON22 0x8140
#define MT6332_BIF_CON23 0x8142
#define MT6332_BIF_CON24 0x8144
#define MT6332_BIF_CON25 0x8146
#define MT6332_BIF_CON26 0x8148
#define MT6332_BIF_CON27 0x814A
#define MT6332_BIF_CON28 0x814C
#define MT6332_BIF_CON29 0x814E
#define MT6332_BIF_CON30 0x8150
#define MT6332_BIF_CON31 0x8152
#define MT6332_BIF_CON32 0x8154
#define MT6332_BIF_CON33 0x8156
#define MT6332_BIF_CON34 0x8158
#define MT6332_BIF_CON35 0x815A
#define MT6332_BIF_CON36 0x815C
#define MT6332_BATON_CON0 0x815E
#define MT6332_BIF_CON37 0x8160
#define MT6332_BIF_CON38 0x8162
#define MT6332_CHR_CON16 0x8164
#define MT6332_CHR_CON17 0x8166
#define MT6332_CHR_CON18 0x8168
#define MT6332_CHR_CON19 0x816A
#define MT6332_CHR_CON20 0x816C
#define MT6332_CHR_CON21 0x816E
#define MT6332_CHR_CON22 0x8170
#define MT6332_CHR_CON23 0x8172
#define MT6332_CHR_CON24 0x8174
#define MT6332_CHR_CON25 0x8176
#define MT6332_STA_CON8 0x8178
#define MT6332_BUCK_ALL_CON0 0x8400
#define MT6332_BUCK_ALL_CON1 0x8402
#define MT6332_BUCK_ALL_CON2 0x8404
#define MT6332_BUCK_ALL_CON3 0x8406
#define MT6332_BUCK_ALL_CON4 0x8408
#define MT6332_BUCK_ALL_CON5 0x840A
#define MT6332_BUCK_ALL_CON6 0x840C
#define MT6332_BUCK_ALL_CON7 0x840E
#define MT6332_BUCK_ALL_CON8 0x8410
#define MT6332_BUCK_ALL_CON9 0x8412
#define MT6332_BUCK_ALL_CON10 0x8414
#define MT6332_BUCK_ALL_CON11 0x8416
#define MT6332_BUCK_ALL_CON12 0x8418
#define MT6332_BUCK_ALL_CON13 0x841A
#define MT6332_BUCK_ALL_CON14 0x841C
#define MT6332_BUCK_ALL_CON15 0x841E
#define MT6332_BUCK_ALL_CON16 0x8420
#define MT6332_BUCK_ALL_CON17 0x8422
#define MT6332_BUCK_ALL_CON18 0x8424
#define MT6332_BUCK_ALL_CON19 0x8426
#define MT6332_BUCK_ALL_CON20 0x8428
#define MT6332_BUCK_ALL_CON21 0x842A
#define MT6332_BUCK_ALL_CON22 0x842C
#define MT6332_BUCK_ALL_CON23 0x842E
#define MT6332_BUCK_ALL_CON24 0x8430
#define MT6332_BUCK_ALL_CON25 0x8432
#define MT6332_BUCK_ALL_CON26 0x8434
#define MT6332_BUCK_ALL_CON27 0x8436
#define MT6332_VDRAM_CON0 0x8438
#define MT6332_VDRAM_CON1 0x843A
#define MT6332_VDRAM_CON2 0x843C
#define MT6332_VDRAM_CON3 0x843E
#define MT6332_VDRAM_CON4 0x8440
#define MT6332_VDRAM_CON5 0x8442
#define MT6332_VDRAM_CON6 0x8444
#define MT6332_VDRAM_CON7 0x8446
#define MT6332_VDRAM_CON8 0x8448
#define MT6332_VDRAM_CON9 0x844A
#define MT6332_VDRAM_CON10 0x844C
#define MT6332_VDRAM_CON11 0x844E
#define MT6332_VDRAM_CON12 0x8450
#define MT6332_VDRAM_CON13 0x8452
#define MT6332_VDRAM_CON14 0x8454
#define MT6332_VDRAM_CON15 0x8456
#define MT6332_VDRAM_CON16 0x8458
#define MT6332_VDRAM_CON17 0x845A
#define MT6332_VDRAM_CON18 0x845C
#define MT6332_VDRAM_CON19 0x845E
#define MT6332_VDRAM_CON20 0x8460
#define MT6332_VDRAM_CON21 0x8462
#define MT6332_VDVFS2_CON0 0x8464
#define MT6332_VDVFS2_CON1 0x8466
#define MT6332_VDVFS2_CON2 0x8468
#define MT6332_VDVFS2_CON3 0x846A
#define MT6332_VDVFS2_CON4 0x846C
#define MT6332_VDVFS2_CON5 0x846E
#define MT6332_VDVFS2_CON6 0x8470
#define MT6332_VDVFS2_CON7 0x8472
#define MT6332_VDVFS2_CON8 0x8474
#define MT6332_VDVFS2_CON9 0x8476
#define MT6332_VDVFS2_CON10 0x8478
#define MT6332_VDVFS2_CON11 0x847A
#define MT6332_VDVFS2_CON12 0x847C
#define MT6332_VDVFS2_CON13 0x847E
#define MT6332_VDVFS2_CON14 0x8480
#define MT6332_VDVFS2_CON15 0x8482
#define MT6332_VDVFS2_CON16 0x8484
#define MT6332_VDVFS2_CON17 0x8486
#define MT6332_VDVFS2_CON18 0x8488
#define MT6332_VDVFS2_CON19 0x848A
#define MT6332_VDVFS2_CON20 0x848C
#define MT6332_VDVFS2_CON21 0x848E
#define MT6332_VDVFS2_CON22 0x8490
#define MT6332_VDVFS2_CON23 0x8492
#define MT6332_VDVFS2_CON24 0x8494
#define MT6332_VDVFS2_CON25 0x8496
#define MT6332_VDVFS2_CON26 0x8498
#define MT6332_VDVFS2_CON27 0x849A
#define MT6332_VRF1_CON0 0x849C
#define MT6332_VRF1_CON1 0x849E
#define MT6332_VRF1_CON2 0x84A0
#define MT6332_VRF1_CON3 0x84A2
#define MT6332_VRF1_CON4 0x84A4
#define MT6332_VRF1_CON5 0x84A6
#define MT6332_VRF1_CON6 0x84A8
#define MT6332_VRF1_CON7 0x84AA
#define MT6332_VRF1_CON8 0x84AC
#define MT6332_VRF1_CON9 0x84AE
#define MT6332_VRF1_CON10 0x84B0
#define MT6332_VRF1_CON11 0x84B2
#define MT6332_VRF1_CON12 0x84B4
#define MT6332_VRF1_CON13 0x84B6
#define MT6332_VRF1_CON14 0x84B8
#define MT6332_VRF1_CON15 0x84BA
#define MT6332_VRF1_CON16 0x84BC
#define MT6332_VRF1_CON17 0x84BE
#define MT6332_VRF1_CON18 0x84C0
#define MT6332_VRF1_CON19 0x84C2
#define MT6332_VRF1_CON20 0x84C4
#define MT6332_VRF1_CON21 0x84C6
#define MT6332_VRF2_CON0 0x84C8
#define MT6332_VRF2_CON1 0x84CA
#define MT6332_VRF2_CON2 0x84CC
#define MT6332_VRF2_CON3 0x84CE
#define MT6332_VRF2_CON4 0x84D0
#define MT6332_VRF2_CON5 0x84D2
#define MT6332_VRF2_CON6 0x84D4
#define MT6332_VRF2_CON7 0x84D6
#define MT6332_VRF2_CON8 0x84D8
#define MT6332_VRF2_CON9 0x84DA
#define MT6332_VRF2_CON10 0x84DC
#define MT6332_VRF2_CON11 0x84DE
#define MT6332_VRF2_CON12 0x84E0
#define MT6332_VRF2_CON13 0x84E2
#define MT6332_VRF2_CON14 0x84E4
#define MT6332_VRF2_CON15 0x84E6
#define MT6332_VRF2_CON16 0x84E8
#define MT6332_VRF2_CON17 0x84EA
#define MT6332_VRF2_CON18 0x84EC
#define MT6332_VRF2_CON19 0x84EE
#define MT6332_VRF2_CON20 0x84F0
#define MT6332_VRF2_CON21 0x84F2
#define MT6332_VPA_CON0 0x84F4
#define MT6332_VPA_CON1 0x84F6
#define MT6332_VPA_CON2 0x84F8
#define MT6332_VPA_CON3 0x84FC
#define MT6332_VPA_CON4 0x84FE
#define MT6332_VPA_CON5 0x8500
#define MT6332_VPA_CON6 0x8502
#define MT6332_VPA_CON7 0x8504
#define MT6332_VPA_CON8 0x8506
#define MT6332_VPA_CON9 0x8508
#define MT6332_VPA_CON10 0x850A
#define MT6332_VPA_CON11 0x850C
#define MT6332_VPA_CON12 0x850E
#define MT6332_VPA_CON13 0x8510
#define MT6332_VPA_CON14 0x8512
#define MT6332_VPA_CON15 0x8514
#define MT6332_VPA_CON16 0x8516
#define MT6332_VPA_CON17 0x8518
#define MT6332_VPA_CON18 0x851A
#define MT6332_VPA_CON19 0x851C
#define MT6332_VPA_CON20 0x851E
#define MT6332_VPA_CON21 0x8520
#define MT6332_VPA_CON22 0x8522
#define MT6332_VPA_CON23 0x8524
#define MT6332_VPA_CON24 0x8526
#define MT6332_VPA_CON25 0x8528
#define MT6332_VSBST_CON0 0x852A
#define MT6332_VSBST_CON1 0x852C
#define MT6332_VSBST_CON2 0x852E
#define MT6332_VSBST_CON3 0x8530
#define MT6332_VSBST_CON4 0x8532
#define MT6332_VSBST_CON5 0x8534
#define MT6332_VSBST_CON6 0x8536
#define MT6332_VSBST_CON7 0x8538
#define MT6332_VSBST_CON8 0x853A
#define MT6332_VSBST_CON9 0x853C
#define MT6332_VSBST_CON10 0x853E
#define MT6332_VSBST_CON11 0x8540
#define MT6332_VSBST_CON12 0x8542
#define MT6332_VSBST_CON13 0x8544
#define MT6332_VSBST_CON14 0x8546
#define MT6332_VSBST_CON15 0x8548
#define MT6332_VSBST_CON16 0x854A
#define MT6332_VSBST_CON17 0x854C
#define MT6332_VSBST_CON18 0x854E
#define MT6332_VSBST_CON19 0x8550
#define MT6332_VSBST_CON20 0x8552
#define MT6332_VSBST_CON21 0x8554
#define MT6332_BUCK_K_CON0 0x8556
#define MT6332_BUCK_K_CON1 0x8558
#define MT6332_BUCK_K_CON2 0x855A
#define MT6332_BUCK_K_CON3 0x855C
#define MT6332_BUCK_K_CON4 0x855E
#define MT6332_BUCK_K_CON5 0x8560
#define MT6332_AUXADC_ADC0 0x8800
#define MT6332_AUXADC_ADC1 0x8802
#define MT6332_AUXADC_ADC2 0x8804
#define MT6332_AUXADC_ADC3 0x8806
#define MT6332_AUXADC_ADC4 0x8808
#define MT6332_AUXADC_ADC5 0x880A
#define MT6332_AUXADC_ADC6 0x880C
#define MT6332_AUXADC_ADC7 0x880E
#define MT6332_AUXADC_ADC8 0x8810
#define MT6332_AUXADC_ADC9 0x8812
#define MT6332_AUXADC_ADC10 0x8814
#define MT6332_AUXADC_ADC11 0x8816
#define MT6332_AUXADC_ADC12 0x8818
#define MT6332_AUXADC_ADC13 0x881A
#define MT6332_AUXADC_ADC14 0x881C
#define MT6332_AUXADC_ADC15 0x881E
#define MT6332_AUXADC_ADC16 0x8820
#define MT6332_AUXADC_ADC17 0x8822
#define MT6332_AUXADC_ADC18 0x8824
#define MT6332_AUXADC_ADC19 0x8826
#define MT6332_AUXADC_ADC20 0x8828
#define MT6332_AUXADC_ADC21 0x882A
#define MT6332_AUXADC_ADC22 0x882C
#define MT6332_AUXADC_ADC23 0x882E
#define MT6332_AUXADC_ADC24 0x8830
#define MT6332_AUXADC_ADC25 0x8832
#define MT6332_AUXADC_ADC26 0x8834
#define MT6332_AUXADC_ADC27 0x8836
#define MT6332_AUXADC_ADC28 0x8838
#define MT6332_AUXADC_ADC29 0x883A
#define MT6332_AUXADC_ADC30 0x883C
#define MT6332_AUXADC_ADC31 0x883E
#define MT6332_AUXADC_ADC32 0x8840
#define MT6332_AUXADC_ADC33 0x8842
#define MT6332_AUXADC_ADC34 0x8844
#define MT6332_AUXADC_ADC35 0x8846
#define MT6332_AUXADC_ADC36 0x8848
#define MT6332_AUXADC_ADC37 0x884A
#define MT6332_AUXADC_ADC38 0x884C
#define MT6332_AUXADC_ADC39 0x884E
#define MT6332_AUXADC_ADC40 0x8850
#define MT6332_AUXADC_ADC41 0x8852
#define MT6332_AUXADC_ADC42 0x8854
#define MT6332_AUXADC_ADC43 0x8856
#define MT6332_AUXADC_STA0 0x8858
#define MT6332_AUXADC_STA1 0x885A
#define MT6332_AUXADC_RQST0 0x885C
#define MT6332_AUXADC_RQST0_SET 0x885E
#define MT6332_AUXADC_RQST0_CLR 0x8860
#define MT6332_AUXADC_RQST1 0x8862
#define MT6332_AUXADC_RQST1_SET 0x8864
#define MT6332_AUXADC_RQST1_CLR 0x8866
#define MT6332_AUXADC_CON0 0x8868
#define MT6332_AUXADC_CON1 0x886A
#define MT6332_AUXADC_CON2 0x886C
#define MT6332_AUXADC_CON3 0x886E
#define MT6332_AUXADC_CON4 0x8870
#define MT6332_AUXADC_CON5 0x8872
#define MT6332_AUXADC_CON6 0x8874
#define MT6332_AUXADC_CON7 0x8876
#define MT6332_AUXADC_CON8 0x8878
#define MT6332_AUXADC_CON9 0x887A
#define MT6332_AUXADC_CON10 0x887C
#define MT6332_AUXADC_CON11 0x887E
#define MT6332_AUXADC_CON12 0x8880
#define MT6332_AUXADC_CON13 0x8882
#define MT6332_AUXADC_CON14 0x8884
#define MT6332_AUXADC_CON15 0x8886
#define MT6332_AUXADC_CON16 0x8888
#define MT6332_AUXADC_CON17 0x888A
#define MT6332_AUXADC_CON18 0x888C
#define MT6332_AUXADC_CON19 0x888E
#define MT6332_AUXADC_CON20 0x8890
#define MT6332_AUXADC_CON21 0x8892
#define MT6332_AUXADC_CON22 0x8894
#define MT6332_AUXADC_CON23 0x8896
#define MT6332_AUXADC_CON24 0x8898
#define MT6332_AUXADC_CON25 0x889A
#define MT6332_AUXADC_CON26 0x889C
#define MT6332_AUXADC_CON27 0x889E
#define MT6332_AUXADC_CON28 0x88A0
#define MT6332_AUXADC_CON29 0x88A2
#define MT6332_AUXADC_CON30 0x88A4
#define MT6332_AUXADC_CON31 0x88A6
#define MT6332_AUXADC_CON32 0x88A8
#define MT6332_AUXADC_CON33 0x88AA
#define MT6332_AUXADC_CON34 0x88AC
#define MT6332_AUXADC_CON35 0x88AE
#define MT6332_AUXADC_CON36 0x88B0
#define MT6332_AUXADC_CON37 0x88B2
#define MT6332_AUXADC_CON38 0x88B4
#define MT6332_AUXADC_CON39 0x88B6
#define MT6332_AUXADC_CON40 0x88B8
#define MT6332_AUXADC_CON41 0x88BA
#define MT6332_AUXADC_CON42 0x88BC
#define MT6332_AUXADC_CON43 0x88BE
#define MT6332_AUXADC_CON44 0x88C0
#define MT6332_AUXADC_CON45 0x88C2
#define MT6332_AUXADC_CON46 0x88C4
#define MT6332_AUXADC_CON47 0x88C6
#define MT6332_STRUP_CONA0 0x8C00
#define MT6332_STRUP_CONA1 0x8C02
#define MT6332_STRUP_CONA2 0x8C04
#define MT6332_STRUP_CON0 0x8C06
#define MT6332_STRUP_CON2 0x8C08
#define MT6332_STRUP_CON3 0x8C0A
#define MT6332_STRUP_CON4 0x8C0C
#define MT6332_STRUP_CON5 0x8C0E
#define MT6332_STRUP_CON6 0x8C10
#define MT6332_STRUP_CON7 0x8C12
#define MT6332_STRUP_CON8 0x8C14
#define MT6332_STRUP_CON9 0x8C16
#define MT6332_STRUP_CON10 0x8C18
#define MT6332_STRUP_CON11 0x8C1A
#define MT6332_STRUP_CON12 0x8C1C
#define MT6332_STRUP_CON13 0x8C1E
#define MT6332_STRUP_CON14 0x8C20
#define MT6332_STRUP_CON15 0x8C22
#define MT6332_STRUP_CON16 0x8C24
#define MT6332_STRUP_CON17 0x8C26
#define MT6332_FGADC_CON0 0x8C28
#define MT6332_FGADC_CON1 0x8C2A
#define MT6332_FGADC_CON2 0x8C2C
#define MT6332_FGADC_CON3 0x8C2E
#define MT6332_FGADC_CON4 0x8C30
#define MT6332_FGADC_CON5 0x8C32
#define MT6332_FGADC_CON6 0x8C34
#define MT6332_FGADC_CON7 0x8C36
#define MT6332_FGADC_CON8 0x8C38
#define MT6332_FGADC_CON9 0x8C3A
#define MT6332_FGADC_CON10 0x8C3C
#define MT6332_FGADC_CON11 0x8C3E
#define MT6332_FGADC_CON12 0x8C40
#define MT6332_FGADC_CON13 0x8C42
#define MT6332_FGADC_CON14 0x8C44
#define MT6332_FGADC_CON15 0x8C46
#define MT6332_FGADC_CON16 0x8C48
#define MT6332_FGADC_CON17 0x8C4A
#define MT6332_FGADC_CON18 0x8C4C
#define MT6332_FGADC_CON19 0x8C4E
#define MT6332_FGADC_CON20 0x8C50
#define MT6332_FGADC_CON21 0x8C52
#define MT6332_FGADC_CON22 0x8C54
#define MT6332_OTP_CON0 0x8C56
#define MT6332_OTP_CON1 0x8C58
#define MT6332_OTP_CON2 0x8C5A
#define MT6332_OTP_CON3 0x8C5C
#define MT6332_OTP_CON4 0x8C5E
#define MT6332_OTP_CON5 0x8C60
#define MT6332_OTP_CON6 0x8C62
#define MT6332_OTP_CON7 0x8C64
#define MT6332_OTP_CON8 0x8C66
#define MT6332_OTP_CON9 0x8C68
#define MT6332_OTP_CON10 0x8C6A
#define MT6332_OTP_CON11 0x8C6C
#define MT6332_OTP_CON12 0x8C6E
#define MT6332_OTP_CON13 0x8C70
#define MT6332_OTP_CON14 0x8C72
#define MT6332_OTP_DOUT_0_15 0x8C74
#define MT6332_OTP_DOUT_16_31 0x8C76
#define MT6332_OTP_DOUT_32_47 0x8C78
#define MT6332_OTP_DOUT_48_63 0x8C7A
#define MT6332_OTP_DOUT_64_79 0x8C7C
#define MT6332_OTP_DOUT_80_95 0x8C7E
#define MT6332_OTP_DOUT_96_111 0x8C80
#define MT6332_OTP_DOUT_112_127 0x8C82
#define MT6332_OTP_DOUT_128_143 0x8C84
#define MT6332_OTP_DOUT_144_159 0x8C86
#define MT6332_OTP_DOUT_160_175 0x8C88
#define MT6332_OTP_DOUT_176_191 0x8C8A
#define MT6332_OTP_DOUT_192_207 0x8C8C
#define MT6332_OTP_DOUT_208_223 0x8C8E
#define MT6332_OTP_DOUT_224_239 0x8C90
#define MT6332_OTP_DOUT_240_255 0x8C92
#define MT6332_OTP_VAL_0_15 0x8C94
#define MT6332_OTP_VAL_16_31 0x8C96
#define MT6332_OTP_VAL_32_47 0x8C98
#define MT6332_OTP_VAL_48_63 0x8C9A
#define MT6332_OTP_VAL_64_79 0x8C9C
#define MT6332_OTP_VAL_80_95 0x8C9E
#define MT6332_OTP_VAL_96_111 0x8CA0
#define MT6332_OTP_VAL_112_127 0x8CA2
#define MT6332_OTP_VAL_128_143 0x8CA4
#define MT6332_OTP_VAL_144_159 0x8CA6
#define MT6332_OTP_VAL_160_175 0x8CA8
#define MT6332_OTP_VAL_176_191 0x8CAA
#define MT6332_OTP_VAL_192_207 0x8CAC
#define MT6332_OTP_VAL_208_223 0x8CAE
#define MT6332_OTP_VAL_224_239 0x8CB0
#define MT6332_OTP_VAL_240_255 0x8CB2
#define MT6332_LDO_CON0 0x8CB4
#define MT6332_LDO_CON1 0x8CB6
#define MT6332_LDO_CON2 0x8CB8
#define MT6332_LDO_CON3 0x8CBA
#define MT6332_LDO_CON5 0x8CBC
#define MT6332_LDO_CON6 0x8CBE
#define MT6332_LDO_CON7 0x8CC0
#define MT6332_LDO_CON8 0x8CC2
#define MT6332_LDO_CON9 0x8CC4
#define MT6332_LDO_CON10 0x8CC6
#define MT6332_LDO_CON11 0x8CC8
#define MT6332_LDO_CON12 0x8CCA
#define MT6332_LDO_CON13 0x8CCC
#define MT6332_FQMTR_CON0 0x8CCE
#define MT6332_FQMTR_CON1 0x8CD0
#define MT6332_FQMTR_CON2 0x8CD2
#define MT6332_IWLED_CON0 0x8CD4
#define MT6332_IWLED_DEG 0x8CD6
#define MT6332_IWLED_STATUS 0x8CD8
#define MT6332_IWLED_EN_CTRL 0x8CDA
#define MT6332_IWLED_CON1 0x8CDC
#define MT6332_IWLED_CON2 0x8CDE
#define MT6332_IWLED_TRIM0 0x8CE0
#define MT6332_IWLED_TRIM1 0x8CE2
#define MT6332_IWLED_CON3 0x8CE4
#define MT6332_IWLED_CON4 0x8CE6
#define MT6332_IWLED_CON5 0x8CE8
#define MT6332_IWLED_CON6 0x8CEA
#define MT6332_IWLED_CON7 0x8CEC
#define MT6332_IWLED_CON8 0x8CEE
#define MT6332_IWLED_CON9 0x8CF0
#define MT6332_SPK_CON0 0x8CF2
#define MT6332_SPK_CON1 0x8CF4
#define MT6332_SPK_CON2 0x8CF6
#define MT6332_SPK_CON3 0x8CF8
#define MT6332_SPK_CON4 0x8CFA
#define MT6332_SPK_CON5 0x8CFC
#define MT6332_SPK_CON6 0x8CFE
#define MT6332_SPK_CON7 0x8D00
#define MT6332_SPK_CON8 0x8D02
#define MT6332_SPK_CON9 0x8D04
#define MT6332_SPK_CON10 0x8D06
#define MT6332_SPK_CON11 0x8D08
#define MT6332_SPK_CON12 0x8D0A
#define MT6332_SPK_CON13 0x8D0C
#define MT6332_SPK_CON14 0x8D0E
#define MT6332_SPK_CON15 0x8D10
#define MT6332_SPK_CON16 0x8D12
#define MT6332_TESTI_CON0 0x8D14
#define MT6332_TESTI_CON1 0x8D16
#define MT6332_TESTI_CON2 0x8D18
#define MT6332_TESTI_CON3 0x8D1A
#define MT6332_TESTI_CON4 0x8D1C
#define MT6332_TESTI_CON5 0x8D1E
#define MT6332_TESTI_CON6 0x8D20
#define MT6332_TESTI_MUX_CON0 0x8D22
#define MT6332_TESTI_MUX_CON1 0x8D24
#define MT6332_TESTI_MUX_CON2 0x8D26
#define MT6332_TESTI_MUX_CON3 0x8D28
#define MT6332_TESTI_MUX_CON4 0x8D2A
#define MT6332_TESTI_MUX_CON5 0x8D2C
#define MT6332_TESTI_MUX_CON6 0x8D2E
#define MT6332_TESTO_CON0 0x8D30
#define MT6332_TESTO_CON1 0x8D32
#define MT6332_TEST_OMUX_CON0 0x8D34
#define MT6332_TEST_OMUX_CON1 0x8D36
#define MT6332_DEBUG_CON0 0x8D38
#define MT6332_DEBUG_CON1 0x8D3A
#define MT6332_DEBUG_CON2 0x8D3C
#define MT6332_FGADC_CON23 0x8D3E
#define MT6332_FGADC_CON24 0x8D40
#define MT6332_FGADC_CON25 0x8D42
#define MT6332_TOP_RST_STATUS 0x8D44
#define MT6332_TOP_RST_STATUS_SET 0x8D46
#define MT6332_TOP_RST_STATUS_CLR 0x8D48
#define MT6332_VDVFS2_CON28 0x8D4A
#endif /* __MFD_MT6332_REGISTERS_H__ */

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include/linux/mfd/mt6357/core.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 BayLibre, SAS
* Author: Fabien Parent <fparent@baylibre.com>
*/
#ifndef __MFD_MT6357_CORE_H__
#define __MFD_MT6357_CORE_H__
enum mt6357_irq_top_status_shift {
MT6357_BUCK_TOP = 0,
MT6357_LDO_TOP,
MT6357_PSC_TOP,
MT6357_SCK_TOP,
MT6357_BM_TOP,
MT6357_HK_TOP,
MT6357_XPP_TOP,
MT6357_AUD_TOP,
MT6357_MISC_TOP,
};
enum mt6357_irq_numbers {
MT6357_IRQ_VPROC_OC = 0,
MT6357_IRQ_VCORE_OC,
MT6357_IRQ_VMODEM_OC,
MT6357_IRQ_VS1_OC,
MT6357_IRQ_VPA_OC,
MT6357_IRQ_VCORE_PREOC,
MT6357_IRQ_VFE28_OC = 16,
MT6357_IRQ_VXO22_OC,
MT6357_IRQ_VRF18_OC,
MT6357_IRQ_VRF12_OC,
MT6357_IRQ_VEFUSE_OC,
MT6357_IRQ_VCN33_OC,
MT6357_IRQ_VCN28_OC,
MT6357_IRQ_VCN18_OC,
MT6357_IRQ_VCAMA_OC,
MT6357_IRQ_VCAMD_OC,
MT6357_IRQ_VCAMIO_OC,
MT6357_IRQ_VLDO28_OC,
MT6357_IRQ_VUSB33_OC,
MT6357_IRQ_VAUX18_OC,
MT6357_IRQ_VAUD28_OC,
MT6357_IRQ_VIO28_OC,
MT6357_IRQ_VIO18_OC,
MT6357_IRQ_VSRAM_PROC_OC,
MT6357_IRQ_VSRAM_OTHERS_OC,
MT6357_IRQ_VIBR_OC,
MT6357_IRQ_VDRAM_OC,
MT6357_IRQ_VMC_OC,
MT6357_IRQ_VMCH_OC,
MT6357_IRQ_VEMC_OC,
MT6357_IRQ_VSIM1_OC,
MT6357_IRQ_VSIM2_OC,
MT6357_IRQ_PWRKEY = 48,
MT6357_IRQ_HOMEKEY,
MT6357_IRQ_PWRKEY_R,
MT6357_IRQ_HOMEKEY_R,
MT6357_IRQ_NI_LBAT_INT,
MT6357_IRQ_CHRDET,
MT6357_IRQ_CHRDET_EDGE,
MT6357_IRQ_VCDT_HV_DET,
MT6357_IRQ_WATCHDOG,
MT6357_IRQ_VBATON_UNDET,
MT6357_IRQ_BVALID_DET,
MT6357_IRQ_OV,
MT6357_IRQ_RTC = 64,
MT6357_IRQ_FG_BAT0_H = 80,
MT6357_IRQ_FG_BAT0_L,
MT6357_IRQ_FG_CUR_H,
MT6357_IRQ_FG_CUR_L,
MT6357_IRQ_FG_ZCV,
MT6357_IRQ_BATON_LV = 96,
MT6357_IRQ_BATON_HT,
MT6357_IRQ_BAT_H = 112,
MT6357_IRQ_BAT_L,
MT6357_IRQ_AUXADC_IMP,
MT6357_IRQ_NAG_C_DLTV,
MT6357_IRQ_AUDIO = 128,
MT6357_IRQ_ACCDET = 133,
MT6357_IRQ_ACCDET_EINT0,
MT6357_IRQ_ACCDET_EINT1,
MT6357_IRQ_SPI_CMD_ALERT = 144,
MT6357_IRQ_NR,
};
#define MT6357_IRQ_BUCK_BASE MT6357_IRQ_VPROC_OC
#define MT6357_IRQ_LDO_BASE MT6357_IRQ_VFE28_OC
#define MT6357_IRQ_PSC_BASE MT6357_IRQ_PWRKEY
#define MT6357_IRQ_SCK_BASE MT6357_IRQ_RTC
#define MT6357_IRQ_BM_BASE MT6357_IRQ_FG_BAT0_H
#define MT6357_IRQ_HK_BASE MT6357_IRQ_BAT_H
#define MT6357_IRQ_AUD_BASE MT6357_IRQ_AUDIO
#define MT6357_IRQ_MISC_BASE MT6357_IRQ_SPI_CMD_ALERT
#define MT6357_IRQ_BUCK_BITS (MT6357_IRQ_VCORE_PREOC - MT6357_IRQ_BUCK_BASE + 1)
#define MT6357_IRQ_LDO_BITS (MT6357_IRQ_VSIM2_OC - MT6357_IRQ_LDO_BASE + 1)
#define MT6357_IRQ_PSC_BITS (MT6357_IRQ_VCDT_HV_DET - MT6357_IRQ_PSC_BASE + 1)
#define MT6357_IRQ_SCK_BITS (MT6357_IRQ_RTC - MT6357_IRQ_SCK_BASE + 1)
#define MT6357_IRQ_BM_BITS (MT6357_IRQ_BATON_HT - MT6357_IRQ_BM_BASE + 1)
#define MT6357_IRQ_HK_BITS (MT6357_IRQ_NAG_C_DLTV - MT6357_IRQ_HK_BASE + 1)
#define MT6357_IRQ_AUD_BITS (MT6357_IRQ_ACCDET_EINT1 - MT6357_IRQ_AUD_BASE + 1)
#define MT6357_IRQ_MISC_BITS \
(MT6357_IRQ_SPI_CMD_ALERT - MT6357_IRQ_MISC_BASE + 1)
#define MT6357_TOP_GEN(sp) \
{ \
.hwirq_base = MT6357_IRQ_##sp##_BASE, \
.num_int_regs = \
((MT6357_IRQ_##sp##_BITS - 1) / \
MTK_PMIC_REG_WIDTH) + 1, \
.en_reg = MT6357_##sp##_TOP_INT_CON0, \
.en_reg_shift = 0x6, \
.sta_reg = MT6357_##sp##_TOP_INT_STATUS0, \
.sta_reg_shift = 0x2, \
.top_offset = MT6357_##sp##_TOP, \
}
#endif /* __MFD_MT6357_CORE_H__ */

1574
include/linux/mfd/mt6357/registers.h Normal file
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File diff suppressed because it is too large Load Diff

3
include/linux/mfd/mt6397/core.h
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@ -12,6 +12,9 @@
enum chip_id { enum chip_id {
MT6323_CHIP_ID = 0x23, MT6323_CHIP_ID = 0x23,
MT6331_CHIP_ID = 0x20,
MT6332_CHIP_ID = 0x20,
MT6357_CHIP_ID = 0x57,
MT6358_CHIP_ID = 0x58, MT6358_CHIP_ID = 0x58,
MT6359_CHIP_ID = 0x59, MT6359_CHIP_ID = 0x59,
MT6366_CHIP_ID = 0x66, MT6366_CHIP_ID = 0x66,

1
include/linux/mfd/t7l66xb.h
View File

@ -12,7 +12,6 @@
struct t7l66xb_platform_data { struct t7l66xb_platform_data {
int (*enable)(struct platform_device *dev); int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev); int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev); int (*resume)(struct platform_device *dev);

1
include/linux/mfd/tc6387xb.h
View File

@ -12,7 +12,6 @@
struct tc6387xb_platform_data { struct tc6387xb_platform_data {
int (*enable)(struct platform_device *dev); int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev); int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev); int (*resume)(struct platform_device *dev);
}; };

2
include/linux/mfd/tc6393xb.h
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@ -22,7 +22,7 @@ struct tc6393xb_platform_data {
u16 scr_gper; /* GP Enable */ u16 scr_gper; /* GP Enable */
int (*enable)(struct platform_device *dev); int (*enable)(struct platform_device *dev);
int (*disable)(struct platform_device *dev); void (*disable)(struct platform_device *dev);
int (*suspend)(struct platform_device *dev); int (*suspend)(struct platform_device *dev);
int (*resume)(struct platform_device *dev); int (*resume)(struct platform_device *dev);

55
include/linux/mfd/twl.h
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@ -692,61 +692,6 @@ struct twl4030_audio_data {
unsigned int irq_base; unsigned int irq_base;
}; };
struct twl4030_platform_data {
struct twl4030_clock_init_data *clock;
struct twl4030_bci_platform_data *bci;
struct twl4030_gpio_platform_data *gpio;
struct twl4030_madc_platform_data *madc;
struct twl4030_keypad_data *keypad;
struct twl4030_usb_data *usb;
struct twl4030_power_data *power;
struct twl4030_audio_data *audio;
/* Common LDO regulators for TWL4030/TWL6030 */
struct regulator_init_data *vdac;
struct regulator_init_data *vaux1;
struct regulator_init_data *vaux2;
struct regulator_init_data *vaux3;
struct regulator_init_data *vdd1;
struct regulator_init_data *vdd2;
struct regulator_init_data *vdd3;
/* TWL4030 LDO regulators */
struct regulator_init_data *vpll1;
struct regulator_init_data *vpll2;
struct regulator_init_data *vmmc1;
struct regulator_init_data *vmmc2;
struct regulator_init_data *vsim;
struct regulator_init_data *vaux4;
struct regulator_init_data *vio;
struct regulator_init_data *vintana1;
struct regulator_init_data *vintana2;
struct regulator_init_data *vintdig;
/* TWL6030 LDO regulators */
struct regulator_init_data *vmmc;
struct regulator_init_data *vpp;
struct regulator_init_data *vusim;
struct regulator_init_data *vana;
struct regulator_init_data *vcxio;
struct regulator_init_data *vusb;
struct regulator_init_data *clk32kg;
struct regulator_init_data *v1v8;
struct regulator_init_data *v2v1;
/* TWL6032 LDO regulators */
struct regulator_init_data *ldo1;
struct regulator_init_data *ldo2;
struct regulator_init_data *ldo3;
struct regulator_init_data *ldo4;
struct regulator_init_data *ldo5;
struct regulator_init_data *ldo6;
struct regulator_init_data *ldo7;
struct regulator_init_data *ldoln;
struct regulator_init_data *ldousb;
/* TWL6032 DCDC regulators */
struct regulator_init_data *smps3;
struct regulator_init_data *smps4;
struct regulator_init_data *vio6025;
};
struct twl_regulator_driver_data { struct twl_regulator_driver_data {
int (*set_voltage)(void *data, int target_uV); int (*set_voltage)(void *data, int target_uV);
int (*get_voltage)(void *data); int (*get_voltage)(void *data);

2
include/linux/platform_data/cros_ec_commands.h
View File

@ -1300,6 +1300,8 @@ enum ec_feature_code {
* mux. * mux.
*/ */
EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43, EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
/* The MCU is a System Companion Processor (SCP) 2nd Core. */
EC_FEATURE_SCP_C1 = 45,
}; };
#define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)

1
include/linux/platform_data/cros_ec_proto.h
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@ -19,6 +19,7 @@
#define CROS_EC_DEV_ISH_NAME "cros_ish" #define CROS_EC_DEV_ISH_NAME "cros_ish"
#define CROS_EC_DEV_PD_NAME "cros_pd" #define CROS_EC_DEV_PD_NAME "cros_pd"
#define CROS_EC_DEV_SCP_NAME "cros_scp" #define CROS_EC_DEV_SCP_NAME "cros_scp"
#define CROS_EC_DEV_SCP_C1_NAME "cros_scp_c1"
#define CROS_EC_DEV_TP_NAME "cros_tp" #define CROS_EC_DEV_TP_NAME "cros_tp"
#define CROS_EC_DEV_EC_INDEX 0 #define CROS_EC_DEV_EC_INDEX 0