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drm/amdgpu: fix rb bitmap & cu bitmap calculation
Fix some copy paste typos. Signed-off-by: Flora Cui <Flora.Cui@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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22073fe764
commit
6157bd7a10
4 changed files with 13 additions and 16 deletions
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@ -46,9 +46,6 @@
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#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
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#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
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#define CIK_RB_BITMAP_WIDTH_PER_SH 2
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#define HAWAII_RB_BITMAP_WIDTH_PER_SH 4
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#define AMDGPU_NUM_OF_VMIDS 8
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#define PIPEID(x) ((x) << 0)
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@ -1637,18 +1637,16 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
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int i, j;
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u32 data;
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u32 active_rbs = 0;
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u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
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adev->gfx.config.max_sh_per_se;
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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gfx_v7_0_select_se_sh(adev, i, j);
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data = gfx_v7_0_get_rb_active_bitmap(adev);
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if (adev->asic_type == CHIP_HAWAII)
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active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
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HAWAII_RB_BITMAP_WIDTH_PER_SH);
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else
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active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
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CIK_RB_BITMAP_WIDTH_PER_SH);
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active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
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rb_bitmap_width_per_sh);
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}
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}
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gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
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@ -3820,8 +3818,7 @@ static u32 gfx_v7_0_get_cu_active_bitmap(struct amdgpu_device *adev)
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data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
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data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
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mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_backends_per_se /
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adev->gfx.config.max_sh_per_se);
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mask = gfx_v7_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
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return (~data) & mask;
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}
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@ -5232,6 +5229,8 @@ int gfx_v7_0_get_cu_info(struct amdgpu_device *adev,
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if (!adev || !cu_info)
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return -EINVAL;
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memset(cu_info, 0, sizeof(*cu_info));
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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@ -2615,6 +2615,8 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
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int i, j;
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u32 data;
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u32 active_rbs = 0;
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u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
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adev->gfx.config.max_sh_per_se;
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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@ -2622,7 +2624,7 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
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gfx_v8_0_select_se_sh(adev, i, j);
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data = gfx_v8_0_get_rb_active_bitmap(adev);
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active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
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RB_BITMAP_WIDTH_PER_SH);
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rb_bitmap_width_per_sh);
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}
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}
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gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
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@ -5126,8 +5128,7 @@ static u32 gfx_v8_0_get_cu_active_bitmap(struct amdgpu_device *adev)
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data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
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data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
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mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_backends_per_se /
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adev->gfx.config.max_sh_per_se);
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mask = gfx_v8_0_create_bitmask(adev->gfx.config.max_cu_per_sh);
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return (~data) & mask;
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}
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@ -5141,6 +5142,8 @@ int gfx_v8_0_get_cu_info(struct amdgpu_device *adev,
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if (!adev || !cu_info)
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return -EINVAL;
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memset(cu_info, 0, sizeof(*cu_info));
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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@ -71,8 +71,6 @@
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#define VMID(x) ((x) << 4)
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#define QUEUEID(x) ((x) << 8)
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#define RB_BITMAP_WIDTH_PER_SH 2
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#define MC_SEQ_MISC0__MT__MASK 0xf0000000
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#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
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#define MC_SEQ_MISC0__MT__DDR2 0x20000000
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