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riscv: thead: Rename T-Head PBMT to MAE 

T-Head's vendor extension to set page attributes has the name
MAE (memory attribute extension).
Let's rename it, so it is clear what this referes to.

Link: https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadmae.adoc
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Link: https://lore.kernel.org/r/20240407213236.2121592-2-christoph.muellner@vrull.eu
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Christoph Müllner 2024-04-07 23:32:35 +02:00 committed by Palmer Dabbelt
parent 6613476e22
commit 6179d4a213
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
3 changed files with 19 additions and 19 deletions
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8
arch/riscv/Kconfig.errata
View File

@ -82,14 +82,14 @@ config ERRATA_THEAD
Otherwise, please say "N" here to avoid unnecessary overhead. Otherwise, please say "N" here to avoid unnecessary overhead.
config ERRATA_THEAD_PBMT config ERRATA_THEAD_MAE
bool "Apply T-Head memory type errata" bool "Apply T-Head's memory attribute extension (XTheadMae) errata"
depends on ERRATA_THEAD && 64BIT && MMU depends on ERRATA_THEAD && 64BIT && MMU
select RISCV_ALTERNATIVE_EARLY select RISCV_ALTERNATIVE_EARLY
default y default y
help help
This will apply the memory type errata to handle the non-standard This will apply the memory attribute extension errata to handle the
memory type bits in page-table-entries on T-Head SoCs. non-standard PTE utilization on T-Head SoCs (XTheadMae).
If you don't know what to do here, say "Y". If you don't know what to do here, say "Y".

10
arch/riscv/errata/thead/errata.c
View File

@ -19,10 +19,10 @@
#include <asm/patch.h> #include <asm/patch.h>
#include <asm/vendorid_list.h> #include <asm/vendorid_list.h>
static bool errata_probe_pbmt(unsigned int stage, static bool errata_probe_mae(unsigned int stage,
unsigned long arch_id, unsigned long impid) unsigned long arch_id, unsigned long impid)
{ {
if (!IS_ENABLED(CONFIG_ERRATA_THEAD_PBMT)) if (!IS_ENABLED(CONFIG_ERRATA_THEAD_MAE))
return false; return false;
if (arch_id != 0 || impid != 0) if (arch_id != 0 || impid != 0)
@ -140,8 +140,8 @@ static u32 thead_errata_probe(unsigned int stage,
{ {
u32 cpu_req_errata = 0; u32 cpu_req_errata = 0;
if (errata_probe_pbmt(stage, archid, impid)) if (errata_probe_mae(stage, archid, impid))
cpu_req_errata |= BIT(ERRATA_THEAD_PBMT); cpu_req_errata |= BIT(ERRATA_THEAD_MAE);
errata_probe_cmo(stage, archid, impid); errata_probe_cmo(stage, archid, impid);

20
arch/riscv/include/asm/errata_list.h
View File

@ -23,7 +23,7 @@
#endif #endif
#ifdef CONFIG_ERRATA_THEAD #ifdef CONFIG_ERRATA_THEAD
#define ERRATA_THEAD_PBMT 0 #define ERRATA_THEAD_MAE 0
#define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_PMU 1
#define ERRATA_THEAD_NUMBER 2 #define ERRATA_THEAD_NUMBER 2
#endif #endif
@ -53,20 +53,20 @@ asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
* in the default case. * in the default case.
*/ */
#define ALT_SVPBMT_SHIFT 61 #define ALT_SVPBMT_SHIFT 61
#define ALT_THEAD_PBMT_SHIFT 59 #define ALT_THEAD_MAE_SHIFT 59
#define ALT_SVPBMT(_val, prot) \ #define ALT_SVPBMT(_val, prot) \
asm(ALTERNATIVE_2("li %0, 0\t\nnop", \ asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
"li %0, %1\t\nslli %0,%0,%3", 0, \ "li %0, %1\t\nslli %0,%0,%3", 0, \
RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \ RISCV_ISA_EXT_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \
"li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \ "li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \
ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \
: "=r"(_val) \ : "=r"(_val) \
: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
"I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \ "I"(prot##_THEAD >> ALT_THEAD_MAE_SHIFT), \
"I"(ALT_SVPBMT_SHIFT), \ "I"(ALT_SVPBMT_SHIFT), \
"I"(ALT_THEAD_PBMT_SHIFT)) "I"(ALT_THEAD_MAE_SHIFT))
#ifdef CONFIG_ERRATA_THEAD_PBMT #ifdef CONFIG_ERRATA_THEAD_MAE
/* /*
* IO/NOCACHE memory types are handled together with svpbmt, * IO/NOCACHE memory types are handled together with svpbmt,
* so on T-Head chips, check if no other memory type is set, * so on T-Head chips, check if no other memory type is set,
@ -83,11 +83,11 @@ asm volatile(ALTERNATIVE( \
"slli t3, t3, %3\n\t" \ "slli t3, t3, %3\n\t" \
"or %0, %0, t3\n\t" \ "or %0, %0, t3\n\t" \
"2:", THEAD_VENDOR_ID, \ "2:", THEAD_VENDOR_ID, \
ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \ ERRATA_THEAD_MAE, CONFIG_ERRATA_THEAD_MAE) \
: "+r"(_val) \ : "+r"(_val) \
: "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \ : "I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_MAE_SHIFT), \
"I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \ "I"(_PAGE_PMA_THEAD >> ALT_THEAD_MAE_SHIFT), \
"I"(ALT_THEAD_PBMT_SHIFT) \ "I"(ALT_THEAD_MAE_SHIFT) \
: "t3") : "t3")
#else #else
#define ALT_THEAD_PMA(_val) #define ALT_THEAD_PMA(_val)