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clk: lmk04832: add support for digital delay
The digital delay allows outputs to be delayed from 8 to 1023 VCO cycles. The delay step can be as small as half the period of the clock distribution path. For example, a 3.2-GHz VCO frequency results in 156.25-ps steps. The digital delay value takes effect on the clock output phase after a SYNC event. This is required to support JESD204B subclass 1. Signed-off-by: Liam Beguin <lvb@xiphos.com> Link: https://lore.kernel.org/r/20210423004057.283926-3-liambeguin@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Liam Beguin
Stephen Boyd
parent
3bc61cfd6f
commit
6181baa177
1 changed files with 315 additions and 6 deletions
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@ -37,16 +37,24 @@
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#define LMK04832_REG_CLKOUT_CTRL0(ch) (0x100 + (ch >> 1) * 8)
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#define LMK04832_BIT_DCLK_DIV_LSB GENMASK(7, 0)
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#define LMK04832_REG_CLKOUT_CTRL1(ch) (0x101 + (ch >> 1) * 8)
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#define LMK04832_BIT_DCLKX_Y_DDLY_LSB GENMASK(7, 0)
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#define LMK04832_REG_CLKOUT_CTRL2(ch) (0x102 + (ch >> 1) * 8)
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#define LMK04832_BIT_CLKOUTX_Y_PD BIT(7)
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#define LMK04832_BIT_DCLKX_Y_DDLY_PD BIT(4)
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#define LMK04832_BIT_DCLKX_Y_DDLY_MSB GENMASK(3, 2)
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#define LMK04832_BIT_DCLK_DIV_MSB GENMASK(1, 0)
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#define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8)
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#define LMK04832_BIT_CLKOUT_SRC_MUX BIT(5)
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#define LMK04832_REG_CLKOUT_CTRL3(ch) (0x103 + (ch >> 1) * 8)
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#define LMK04832_BIT_DCLKX_Y_PD BIT(4)
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#define LMK04832_BIT_DCLKX_Y_DCC BIT(2)
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#define LMK04832_BIT_DCLKX_Y_HS BIT(0)
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#define LMK04832_REG_CLKOUT_CTRL4(ch) (0x104 + (ch >> 1) * 8)
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#define LMK04832_BIT_SCLK_PD BIT(4)
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#define LMK04832_BIT_SCLKX_Y_DIS_MODE GENMASK(3, 2)
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#define LMK04832_REG_SCLKX_Y_ADLY(ch) (0x105 + (ch >> 1) * 8)
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#define LMK04832_REG_SCLKX_Y_DDLY(ch) (0x106 + (ch >> 1) * 8)
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#define LMK04832_BIT_SCLKX_Y_DDLY GENMASK(3, 0)
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#define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8)
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#define LMK04832_BIT_CLKOUT_FMT(ch) (ch % 2 ? 0xf0 : 0x0f)
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#define LMK04832_VAL_CLKOUT_FMT_POWERDOWN 0x00
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@ -73,11 +81,19 @@
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#define LMK04832_VAL_VCO_MUX_VCO1 0x01
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#define LMK04832_VAL_VCO_MUX_EXT 0x02
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#define LMK04832_REG_SYSREF_OUT 0x139
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#define LMK04832_BIT_SYSREF_REQ_EN BIT(6)
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#define LMK04832_BIT_SYSREF_MUX GENMASK(1, 0)
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#define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC 0x00
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#define LMK04832_VAL_SYSREF_MUX_RECLK 0x01
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#define LMK04832_VAL_SYSREF_MUX_PULSER 0x02
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#define LMK04832_VAL_SYSREF_MUX_CONTINUOUS 0x03
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#define LMK04832_REG_SYSREF_DIV_MSB 0x13a
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#define LMK04832_BIT_SYSREF_DIV_MSB GENMASK(4, 0)
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#define LMK04832_REG_SYSREF_DIV_LSB 0x13b
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#define LMK04832_REG_SYSREF_DDLY_MSB 0x13c
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#define LMK04832_BIT_SYSREF_DDLY_MSB GENMASK(4, 0)
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#define LMK04832_REG_SYSREF_DDLY_LSB 0x13d
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#define LMK04832_REG_SYSREF_PULSE_CNT 0x13e
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#define LMK04832_REG_FB_CTRL 0x13f
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#define LMK04832_BIT_PLL2_RCLK_MUX BIT(7)
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#define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN 0x00
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@ -96,7 +112,15 @@
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#define LMK04832_BIT_SYSREF_DDLY_PD BIT(1)
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#define LMK04832_BIT_SYSREF_PLSR_PD BIT(0)
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#define LMK04832_REG_SYNC 0x143
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#define LMK04832_BIT_SYNC_CLR BIT(7)
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#define LMK04832_BIT_SYNC_1SHOT_EN BIT(6)
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#define LMK04832_BIT_SYNC_POL BIT(5)
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#define LMK04832_BIT_SYNC_EN BIT(4)
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#define LMK04832_BIT_SYNC_MODE GENMASK(1, 0)
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#define LMK04832_VAL_SYNC_MODE_OFF 0x00
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#define LMK04832_VAL_SYNC_MODE_ON 0x01
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#define LMK04832_VAL_SYNC_MODE_PULSER_PIN 0x02
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#define LMK04832_VAL_SYNC_MODE_PULSER_SPI 0x03
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#define LMK04832_REG_SYNC_DIS 0x144
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/* 0x146 - 0x14a CLKin Control */
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@ -128,6 +152,7 @@
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#define LMK04832_BIT_PLL2_N_0 GENMASK(1, 0)
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#define LMK04832_REG_PLL2_N_1 0x167
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#define LMK04832_REG_PLL2_N_2 0x168
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#define LMK04832_REG_PLL2_DLD_CNT_MSB 0x16a
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#define LMK04832_REG_PLL2_DLD_CNT_LSB 0x16b
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#define LMK04832_REG_PLL2_LD 0x16e
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#define LMK04832_BIT_PLL2_LD_MUX GENMASK(7, 3)
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@ -204,6 +229,11 @@ struct lmk_clkout {
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*
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* @dev: reference to a struct device, linked to the spi_device
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* @regmap: struct regmap instance use to access the chip
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* @sync_mode: operational mode for SYNC signal
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* @sysref_mux: select SYSREF source
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* @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
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* mode.
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* @sysref_ddly: SYSREF digital delay value
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* @oscin: PLL2 input clock
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* @vco: reference to the internal VCO clock
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* @sclk: reference to the internal sysref clock (SCLK)
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@ -218,6 +248,11 @@ struct lmk04832 {
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struct device *dev;
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struct regmap *regmap;
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unsigned int sync_mode;
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unsigned int sysref_mux;
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unsigned int sysref_pulse_cnt;
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unsigned int sysref_ddly;
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struct clk *oscin;
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struct clk_hw vco;
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struct clk_hw sclk;
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@ -614,6 +649,212 @@ static int lmk04832_register_vco(struct lmk04832 *lmk)
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return devm_clk_hw_register(lmk->dev, &lmk->vco);
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}
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static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
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{
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int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
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unsigned int sclkx_y_ddly = 10;
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unsigned int dclkx_y_ddly;
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unsigned int dclkx_y_div;
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unsigned int sysref_ddly;
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unsigned int dclkx_y_hs;
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unsigned int lsb, msb;
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int ret;
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ret = regmap_update_bits(lmk->regmap,
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LMK04832_REG_CLKOUT_CTRL2(id),
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LMK04832_BIT_DCLKX_Y_DDLY_PD,
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FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0));
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if (ret)
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return ret;
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ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb);
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if (ret)
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return ret;
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ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb);
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if (ret)
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return ret;
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sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb;
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ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb);
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if (ret)
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return ret;
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ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb);
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if (ret)
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return ret;
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dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
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ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb);
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if (ret)
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return ret;
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dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb);
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dclkx_y_ddly = sysref_ddly + 1 -
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dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] -
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dclkx_y_hs + sclkx_y_ddly;
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if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) {
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dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n",
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dclkx_y_ddly);
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return -EINVAL;
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}
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ret = regmap_write(lmk->regmap,
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LMK04832_REG_SCLKX_Y_DDLY(id),
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FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly));
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if (ret)
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return ret;
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ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id),
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FIELD_GET(0x00ff, dclkx_y_ddly));
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if (ret)
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return ret;
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dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, "
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"dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n",
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id, sysref_ddly, dclkx_y_ddly,
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dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7],
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dclkx_y_hs, sclkx_y_ddly);
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return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id),
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LMK04832_BIT_DCLKX_Y_DDLY_MSB,
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FIELD_GET(0x0300, dclkx_y_ddly));
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}
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/** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
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* and dclk
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*
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* @lmk: Reference to the lmk device
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*
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* The synchronization sequence:
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* - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
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* (8.3.3.1 How to enable SYSREF)
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* - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
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*
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* Returns 0 or negative errno.
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*/
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static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk)
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{
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int ret;
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int i;
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/* 1. (optional) mute all sysref_outputs during synchronization */
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/* 2. Enable and write device clock digital delay to applicable clocks */
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
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LMK04832_BIT_SYSREF_DDLY_PD,
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FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0));
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if (ret)
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return ret;
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for (i = 0; i < lmk->clk_data->num; i += 2) {
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ret = lmk04832_clkout_set_ddly(lmk, i);
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if (ret)
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return ret;
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}
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/*
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* 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC,
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* and clear SYSREF_REQ_EN (see 6.)
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*/
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
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LMK04832_BIT_SYSREF_REQ_EN |
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LMK04832_BIT_SYSREF_MUX,
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FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) |
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FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
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LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC));
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if (ret)
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return ret;
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
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LMK04832_BIT_SYNC_MODE,
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FIELD_PREP(LMK04832_BIT_SYNC_MODE,
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LMK04832_VAL_SYNC_MODE_ON));
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if (ret)
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return ret;
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/* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */
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ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
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if (ret)
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return ret;
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/*
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* 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock
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* distribution path cycles (VCO cycles), then back to 0. In
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* PLL2-only use case, this will be complete in less than one SPI
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* transaction. If SYSREF local digital delay is not used, this step
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* can be skipped.
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*/
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
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LMK04832_BIT_SYNC_CLR,
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FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01));
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if (ret)
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return ret;
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
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LMK04832_BIT_SYNC_CLR,
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FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
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if (ret)
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return ret;
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/*
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* 6. Toggle SYNC_POL state between inverted and not inverted.
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* If you use an external signal on the SYNC pin instead of toggling
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* SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX
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* does not shift into continuous SYSREF mode.
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*/
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
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LMK04832_BIT_SYNC_POL,
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FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01));
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if (ret)
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return ret;
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
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LMK04832_BIT_SYNC_POL,
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FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
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if (ret)
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return ret;
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/* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */
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ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
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if (ret)
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return ret;
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/* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
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LMK04832_BIT_SYSREF_MUX,
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FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
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lmk->sysref_mux));
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if (ret)
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return ret;
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
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LMK04832_BIT_SYNC_MODE,
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FIELD_PREP(LMK04832_BIT_SYNC_MODE,
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lmk->sync_mode));
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if (ret)
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return ret;
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/*
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* 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs
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* during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state,
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* or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional
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* option.
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*/
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/*
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* 10. (optional) To reduce power consumption, after the synchronization
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* event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the
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* digital delay counters (which are only used immediately after the
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* SYNC pulse to delay the output by some number of VCO counts).
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*/
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return ret;
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}
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static int lmk04832_sclk_is_enabled(struct clk_hw *hw)
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{
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struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
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@ -701,8 +942,16 @@ static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate,
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if (ret)
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return ret;
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return regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
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ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
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FIELD_GET(0x00ff, sysref_div));
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if (ret)
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return ret;
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ret = lmk04832_sclk_sync_sequence(lmk);
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if (ret)
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dev_err(lmk->dev, "SYNC sequence failed\n");
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return ret;
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}
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static const struct clk_ops lmk04832_sclk_ops = {
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@ -731,18 +980,37 @@ static int lmk04832_register_sclk(struct lmk04832 *lmk)
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
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LMK04832_BIT_SYSREF_MUX,
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FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
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LMK04832_VAL_SYSREF_MUX_CONTINUOUS));
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lmk->sysref_mux));
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if (ret)
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return ret;
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ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB,
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FIELD_GET(0x00ff, lmk->sysref_ddly));
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if (ret)
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return ret;
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ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB,
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FIELD_GET(0x1f00, lmk->sysref_ddly));
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if (ret)
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return ret;
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ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT,
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ilog2(lmk->sysref_pulse_cnt));
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if (ret)
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return ret;
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ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
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LMK04832_BIT_SYSREF_DDLY_PD |
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LMK04832_BIT_SYSREF_PLSR_PD,
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LMK04832_BIT_SYSREF_PLSR_PD);
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FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) |
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FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0));
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if (ret)
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return ret;
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||||
|
||||
ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
|
||||
LMK04832_BIT_SYNC_EN, 0xff);
|
||||
ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC,
|
||||
FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) |
|
||||
FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) |
|
||||
FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
@ -862,15 +1130,41 @@ static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC
|
||||
* procedure requires to first program Divide-by-4 and then back to
|
||||
* Divide-by-2 or Divide-by-3 before doing SYNC.
|
||||
*/
|
||||
if (dclk_div == 2 || dclk_div == 3) {
|
||||
ret = regmap_update_bits(lmk->regmap,
|
||||
LMK04832_REG_CLKOUT_CTRL2(dclk->id),
|
||||
LMK04832_BIT_DCLK_DIV_MSB, 0x00);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = regmap_write(lmk->regmap,
|
||||
LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
|
||||
FIELD_GET(0x0ff, dclk_div));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return regmap_update_bits(lmk->regmap,
|
||||
ret = regmap_update_bits(lmk->regmap,
|
||||
LMK04832_REG_CLKOUT_CTRL2(dclk->id),
|
||||
LMK04832_BIT_DCLK_DIV_MSB,
|
||||
FIELD_GET(0x300, dclk_div));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = lmk04832_sclk_sync_sequence(lmk);
|
||||
if (ret)
|
||||
dev_err(lmk->dev, "SYNC sequence failed\n");
|
||||
|
||||
return ret;
|
||||
};
|
||||
|
||||
static const struct clk_ops lmk04832_dclk_ops = {
|
||||
|
|
@ -1153,6 +1447,21 @@ static int lmk04832_probe(struct spi_device *spi)
|
|||
|
||||
device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
|
||||
|
||||
lmk->sysref_ddly = 8;
|
||||
device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);
|
||||
|
||||
lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS;
|
||||
device_property_read_u32(lmk->dev, "ti,sysref-mux",
|
||||
&lmk->sysref_mux);
|
||||
|
||||
lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF;
|
||||
device_property_read_u32(lmk->dev, "ti,sync-mode",
|
||||
&lmk->sync_mode);
|
||||
|
||||
lmk->sysref_pulse_cnt = 4;
|
||||
device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
|
||||
&lmk->sysref_pulse_cnt);
|
||||
|
||||
for_each_child_of_node(lmk->dev->of_node, child) {
|
||||
int reg;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue