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drm/etnaviv: fix power register offset on GC300
Older GC300 revisions have their power registers at an offset of 0x200 rather than 0x100. Add new gpu_read_power and gpu_write_power functions to encapsulate accesses to the power addresses and fix the addresses. Signed-off-by: Doug Brown <doug@schmorgal.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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cc7d3fb446
commit
61a6920bb6
3 changed files with 37 additions and 11 deletions
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@ -83,10 +83,15 @@ static void etnaviv_core_dump_registers(struct core_dump_iterator *iter,
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{
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struct etnaviv_dump_registers *reg = iter->data;
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unsigned int i;
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u32 read_addr;
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for (i = 0; i < ARRAY_SIZE(etnaviv_dump_registers); i++, reg++) {
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read_addr = etnaviv_dump_registers[i];
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if (read_addr >= VIVS_PM_POWER_CONTROLS &&
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read_addr <= VIVS_PM_PULSE_EATER)
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read_addr = gpu_fix_power_address(gpu, read_addr);
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reg->reg = cpu_to_le32(etnaviv_dump_registers[i]);
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reg->value = cpu_to_le32(gpu_read(gpu, etnaviv_dump_registers[i]));
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reg->value = cpu_to_le32(gpu_read(gpu, read_addr));
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}
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etnaviv_core_dump_header(iter, ETDUMP_BUF_REG, reg);
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@ -590,7 +590,7 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
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u32 pmc, ppc;
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/* enable clock gating */
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ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
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ppc = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
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ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
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/* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
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@ -598,9 +598,9 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
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gpu->identity.revision == 0x4302)
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ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
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gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
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gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, ppc);
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pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
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pmc = gpu_read_power(gpu, VIVS_PM_MODULE_CONTROLS);
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/* Disable PA clock gating for GC400+ without bugfix except for GC420 */
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if (gpu->identity.model >= chipModel_GC400 &&
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@ -635,7 +635,7 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
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pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
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pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
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gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
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gpu_write_power(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
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}
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void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
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@ -695,11 +695,11 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
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(gpu->identity.features & chipFeatures_PIPE_3D))
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{
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/* Performance fix: disable internal DFS */
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pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
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pulse_eater = gpu_read_power(gpu, VIVS_PM_PULSE_EATER);
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pulse_eater |= BIT(18);
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}
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gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
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gpu_write_power(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
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}
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static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
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@ -1317,9 +1317,9 @@ static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
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u32 val;
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/* disable clock gating */
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val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
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val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
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val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
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gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
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gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
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/* enable debug register */
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val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
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@ -1350,9 +1350,9 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
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gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
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/* enable clock gating */
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val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
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val = gpu_read_power(gpu, VIVS_PM_POWER_CONTROLS);
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val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
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gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
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gpu_write_power(gpu, VIVS_PM_POWER_CONTROLS, val);
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}
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@ -10,6 +10,7 @@
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#include "etnaviv_gem.h"
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#include "etnaviv_mmu.h"
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#include "etnaviv_drv.h"
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#include "common.xml.h"
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struct etnaviv_gem_submit;
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struct etnaviv_vram_mapping;
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@ -159,6 +160,26 @@ static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
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return readl(gpu->mmio + reg);
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}
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static inline u32 gpu_fix_power_address(struct etnaviv_gpu *gpu, u32 reg)
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{
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/* Power registers in GC300 < 2.0 are offset by 0x100 */
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if (gpu->identity.model == chipModel_GC300 &&
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gpu->identity.revision < 0x2000)
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reg += 0x100;
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return reg;
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}
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static inline void gpu_write_power(struct etnaviv_gpu *gpu, u32 reg, u32 data)
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{
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writel(data, gpu->mmio + gpu_fix_power_address(gpu, reg));
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}
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static inline u32 gpu_read_power(struct etnaviv_gpu *gpu, u32 reg)
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{
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return readl(gpu->mmio + gpu_fix_power_address(gpu, reg));
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}
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int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
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int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
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