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Qualcomm ARM64 DT updates for 5.13

Browse source 
This extends the initial SM8350 description merged in v5.12 with
 CPUfreq, SMMU, UFS, RPMHPD, SPMI, USB and remoteproc support. It adds
 initial PMIC definitions for the 6 PMICs found on the MTP and it
 introduces the new SM8350 Hardware Development Kit (HDK).
 
 SC7180 is further polished, the DisplayPort portion of the QMP phy is
 defined and several new SKUs of the Trogdor devices are introduced.
 
 The new SC7280 platform is introduced, with RPMH, RPMHPD, RPMCC, SPMI,
 CPU idle, SMMU and watchdog defined.
 
 SDM845 gains the camera related nodes and some cleanups.
 
 For SM8250 it brings some cleanups and migrates SPI0 to use GPIO for
 chip select.
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Merge tag 'qcom-arm64-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 DT updates for 5.13

This extends the initial SM8350 description merged in v5.12 with
CPUfreq, SMMU, UFS, RPMHPD, SPMI, USB and remoteproc support. It adds
initial PMIC definitions for the 6 PMICs found on the MTP and it
introduces the new SM8350 Hardware Development Kit (HDK).

SC7180 is further polished, the DisplayPort portion of the QMP phy is
defined and several new SKUs of the Trogdor devices are introduced.

The new SC7280 platform is introduced, with RPMH, RPMHPD, RPMCC, SPMI,
CPU idle, SMMU and watchdog defined.

SDM845 gains the camera related nodes and some cleanups.

For SM8250 it brings some cleanups and migrates SPI0 to use GPIO for
chip select.

* tag 'qcom-arm64-for-5.13' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (79 commits)
  arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CS
  arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CS
  arm64: dts: qcom: sm8250: further split of spi pinctrl config
  arm64: dts: qcom: sm8250: split spi pinctrl config
  arm64: dts: qcom: sdm845-db845c: Enable ov8856 sensor and connect to ISP
  arm64: dts: qcom: sdm845-db845c: Configure regulators for camss node
  arm64: dts: qcom: sdm845: Add CAMSS ISP node
  arm64: dts: qcom: pm8150: Enable RTC
  arm64: dts: qcom: sm8350-mtp: Add PMICs
  arm64: dts: qcom: pmr735B: Add base dts file
  arm64: dts: qcom: pmr735a: Add base dts file
  arm64: dts: qcom: pm8350c: Add base dts file
  arm64: dts: qcom: pm8350b: Add base dts file
  arm64: dts: qcom: pm8350: Add base dts file
  arm64: dts: qcom: pmk8350: Add base dts file
  arm64: dts: qcom: sm8350: Add spmi node
  arm64: dts: qcom: db845c: fix correct powerdown pin for WSA881x
  dt-bindings: arm: qcom: Add SM8350 HDK
  arm64: dts: qcom: sc7180: Drop duplicate dp_hot_plug_det node in trogdor
  arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'
  ...

Link: https://lore.kernel.org/r/20210404164914.712946-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-04-07 14:01:03 +02:00
commit 61bac46eed
45 changed files with 3572 additions and 472 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

18
Documentation/devicetree/bindings/arm/qcom.yaml
View file

@ -37,6 +37,7 @@ description: |
msm8994
msm8996
sc7180
sc7280
sdm630
sdm660
sdm845
@ -136,6 +137,16 @@ properties:
- samsung,a5u-eur
- const: qcom,msm8916
- items:
- enum:
- sony,karin_windy
- sony,karin-row
- sony,satsuki-row
- sony,sumire-row
- sony,suzuran-row
- qcom,msm8994
- const: qcom,apq8094
- items:
- const: qcom,msm8996-mtp
@ -164,6 +175,11 @@ properties:
- qcom,sc7180-idp
- const: qcom,sc7180
- items:
- enum:
- qcom,sc7280-idp
- const: qcom,sc7280
- items:
- enum:
- xiaomi,lavender
@ -176,6 +192,7 @@ properties:
- items:
- enum:
- qcom,ipq6018-cp01
- qcom,ipq6018-cp01-c1
- const: qcom,ipq6018
@ -187,6 +204,7 @@ properties:
- items:
- enum:
- qcom,sm8350-hdk
- qcom,sm8350-mtp
- const: qcom,sm8350

13
arch/arm64/boot/dts/qcom/Makefile
View file

@ -31,6 +31,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r2-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
@ -38,8 +42,16 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r2-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb
@ -59,4 +71,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb

2
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
View file

@ -9,5 +9,5 @@
/ {
model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";
compatible = "qcom,apq8016-sbc", "qcom,apq8016";
};

4
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file

@ -25,10 +25,10 @@ aliases {
chosen { };
memory {
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x80000000 0 0>;
};
reserved-memory {

4
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file

@ -149,10 +149,10 @@ scm {
};
};
memory {
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the reg */
reg = <0 0 0 0>;
reg = <0 0x80000000 0 0>;
};
tcsr_mutex: hwlock {

4
arch/arm64/boot/dts/qcom/pm8150.dtsi
View file

@ -107,13 +107,11 @@ pm8150_adc_tm: adc-tm@3500 {
status = "disabled";
};
pm8150_rtc: rtc@6000 {
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
status = "disabled";
};
pm8150_gpios: gpio@c000 {

25
arch/arm64/boot/dts/qcom/pm8350.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pm8350: pmic@1 {
compatible = "qcom,pm8350", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8350_gpios: gpio@8800 {
compatible = "qcom,pm8350-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

25
arch/arm64/boot/dts/qcom/pm8350b.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pm8350b: pmic@3 {
compatible = "qcom,pm8350b", "qcom,spmi-pmic";
reg = <0x3 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8350b_gpios: gpio@8800 {
compatible = "qcom,pm8350b-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

25
arch/arm64/boot/dts/qcom/pm8350c.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pm8350c: pmic@2 {
compatible = "qcom,pm8350c", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8350c_gpios: gpio@8800 {
compatible = "qcom,pm8350c-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

25
arch/arm64/boot/dts/qcom/pmk8350.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmk8350: pmic@0 {
compatible = "qcom,pmk8350", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmk8350_gpios: gpio@b000 {
compatible = "qcom,pmk8350-gpio";
reg = <0xb000>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

25
arch/arm64/boot/dts/qcom/pmr735a.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmr735a: pmic@4 {
compatible = "qcom,pmr735a", "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmr735a_gpios: gpio@8800 {
compatible = "qcom,pmr735a-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

25
arch/arm64/boot/dts/qcom/pmr735b.dtsi Normal file
View file

@ -0,0 +1,25 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2021, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmr735b: pmic@5 {
compatible = "qcom,pmr735b", "qcom,spmi-pmic";
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmr735b_gpios: gpio@8800 {
compatible = "qcom,pmr735b-gpio";
reg = <0x8800>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

18
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View file

@ -811,10 +811,6 @@ lt9611_rst_pin: lt9611-rst-pin {
};
};
&pm8150_rtc {
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
@ -952,6 +948,9 @@ codec {
/* CAN */
&spi0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs_gpio>;
cs-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
can@0 {
compatible = "microchip,mcp2518fd";
@ -1352,3 +1351,14 @@ &vamacro {
vdd-micb-supply = <&vreg_s4a_1p8>;
qcom,dmic-sample-rate = <600000>;
};
/* PINCTRL - additions to nodes defined in sm8250.dtsi */
&qup_spi0_cs_gpio {
drive-strength = <6>;
bias-disable;
};
&qup_spi0_data_clk {
drive-strength = <6>;
bias-disable;
};

18
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dts Normal file
View file

@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google CoachZ board device tree source
*
* Copyright 2020 Google LLC.
*/
#include "sc7180-trogdor-coachz-r1.dts"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
model = "Google CoachZ (rev1) with LTE";
compatible = "google,coachz-rev1-sku0", "qcom,sc7180";
};
&cros_ec_proximity {
label = "proximity-wifi-lte";
};

154
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts Normal file
View file

@ -0,0 +1,154 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google CoachZ board device tree source
*
* Copyright 2020 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor-coachz.dtsi"
/ {
model = "Google CoachZ (rev1)";
compatible = "google,coachz-rev1", "qcom,sc7180";
};
&tlmm {
gpio-line-names = "HUB_RST_L",
"AP_RAM_ID0",
"AP_SKU_ID2",
"AP_RAM_ID1",
"FP_TO_AP_IRQ_L",
"AP_RAM_ID2",
"UF_CAM_EN",
"WF_CAM_EN",
"TS_RESET_L",
"TS_INT_L",
"FPMCU_BOOT0",
"EDP_BRIJ_IRQ",
"AP_EDP_BKLTEN",
"UF_CAM_MCLK",
"WF_CAM_CLK",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"UF_CAM_SDA",
"UF_CAM_SCL",
"WF_CAM_SDA",
"WF_CAM_SCL",
"WLC_IRQ",
"FP_RST_L",
"AMP_EN",
"WLC_NRST",
"AP_SAR_SENSOR_SDA",
"AP_SAR_SENSOR_SCL",
"",
"",
"WF_CAM_RST_L",
"UF_CAM_RST_L",
"AP_BRD_ID2",
"BRIJ_SUSPEND",
"AP_BRD_ID0",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"",
"",
"",
"H1_AP_INT_ODL",
"",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DIN",
"EN_PP3300_DX_EDP",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"HP_MCLK",
"AP_SKU_ID0",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_SPI_CLK",
"AP_SPI_MOSI",
"AP_SPI_MISO",
/*
* AP_FLASH_WP_L is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_L.
*/
"AP_FLASH_WP_L",
"",
"AP_SPI_CS0_L",
"SD_CD_ODL",
"",
"",
"",
"",
"FPMCU_SEL",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT_L",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"DMIC_CLK_EN",
"HUB_EN",
"",
"AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"AP_SKU_ID1",
"AP_RST_REQ",
"",
"AP_BRD_ID1",
"AP_EC_INT_L",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"EDP_BRIJ_EN",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"AP_TS_PEN_I2C_SDA",
"AP_TS_PEN_I2C_SCL",
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
dmic_clk_en: dmic_clk_en {
pinmux {
pins = "gpio83";
function = "gpio";
};
pinconf {
pins = "gpio83";
drive-strength = <8>;
bias-pull-up;
};
};
};

18
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2-lte.dts Normal file
View file

@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google CoachZ board device tree source
*
* Copyright 2020 Google LLC.
*/
#include "sc7180-trogdor-coachz-r2.dts"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
model = "Google CoachZ (rev2+) with LTE";
compatible = "google,coachz-sku0", "qcom,sc7180";
};
&cros_ec_proximity {
label = "proximity-wifi-lte";
};

15
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r2.dts Normal file
View file

@ -0,0 +1,15 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google CoachZ board device tree source
*
* Copyright 2020 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor-coachz.dtsi"
/ {
model = "Google CoachZ (rev2+)";
compatible = "google,coachz", "qcom,sc7180";
};

240
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi Normal file
View file

@ -0,0 +1,240 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google CoachZ board device tree source
*
* Copyright 2020 Google LLC.
*/
#include "sc7180.dtsi"
ap_ec_spi: &spi6 {};
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
/* Deleted nodes from trogdor.dtsi */
/delete-node/ &alc5682;
/delete-node/ &pp3300_codec;
/ {
/* BOARD-SPECIFIC TOP LEVEL NODES */
adau7002: audio-codec-1 {
compatible = "adi,adau7002";
IOVDD-supply = <&pp1800_l15a>;
#sound-dai-cells = <0>;
};
};
&ap_spi_fp {
status = "okay";
};
&backlight {
pwms = <&cros_ec_pwm 0>;
};
&camcc {
status = "okay";
};
&cros_ec {
cros_ec_proximity: proximity {
compatible = "google,cros-ec-mkbp-proximity";
label = "proximity-wifi";
};
};
ap_ts_pen_1v8: &i2c4 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@5d {
compatible = "goodix,gt7375p";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
interrupt-parent = <&tlmm>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
vdd-supply = <&pp3300_ts>;
};
};
&i2c7 {
status = "disabled";
};
&i2c9 {
status = "disabled";
};
&panel {
compatible = "boe,nv110wtm-n61";
};
&pp3300_dx_edp {
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};
&sdhc_2 {
status = "okay";
};
&sn65dsi86_out {
data-lanes = <0 1 2 3>;
};
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&en_pp3300_dx_edp {
pinmux {
pins = "gpio67";
};
pinconf {
pins = "gpio67";
};
};
&ts_reset_l {
pinconf {
/*
* We want reset state by default and it will be up to the
* driver to disable this when it's ready.
*/
output-low;
};
};
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "HUB_RST_L",
"AP_RAM_ID0",
"AP_SKU_ID2",
"AP_RAM_ID1",
"FP_TO_AP_IRQ_L",
"AP_RAM_ID2",
"UF_CAM_EN",
"WF_CAM_EN",
"TS_RESET_L",
"TS_INT_L",
"FPMCU_BOOT0",
"EDP_BRIJ_IRQ",
"AP_EDP_BKLTEN",
"UF_CAM_MCLK",
"WF_CAM_CLK",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"UF_CAM_SDA",
"UF_CAM_SCL",
"WF_CAM_SDA",
"WF_CAM_SCL",
"WLC_IRQ",
"FP_RST_L",
"AMP_EN",
"WLC_NRST",
"AP_SAR_SENSOR_SDA",
"AP_SAR_SENSOR_SCL",
"",
"",
"WF_CAM_RST_L",
"UF_CAM_RST_L",
"AP_BRD_ID2",
"BRIJ_SUSPEND",
"AP_BRD_ID0",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"",
"",
"",
"H1_AP_INT_ODL",
"",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DIN",
"",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"HP_MCLK",
"AP_SKU_ID0",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_SPI_CLK",
"AP_SPI_MOSI",
"AP_SPI_MISO",
/*
* AP_FLASH_WP_L is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_L.
*/
"AP_FLASH_WP_L",
"EN_PP3300_DX_EDP",
"AP_SPI_CS0_L",
"SD_CD_ODL",
"",
"",
"",
"",
"EN_FP_RAILS",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT_L",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"",
"HUB_EN",
"",
"AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"AP_SKU_ID1",
"AP_RST_REQ",
"",
"AP_BRD_ID1",
"AP_EC_INT_L",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"EDP_BRIJ_EN",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"AP_TS_PEN_I2C_SDA",
"AP_TS_PEN_I2C_SCL",
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
};

34
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts Normal file
View file

@ -0,0 +1,34 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Lazor Limozeen board device tree source
*
* Copyright 2020 Google LLC.
*/
#include "sc7180-trogdor-lazor-limozeen-nots.dts"
/ {
model = "Google Lazor Limozeen without Touchscreen (rev4)";
compatible = "google,lazor-rev4-sku5", "qcom,sc7180";
};
/*
* rev4-sku5 was built with a different trackpad.
*/
/delete-node/&trackpad;
&ap_tp_i2c {
trackpad: trackpad@2c {
compatible = "hid-over-i2c";
reg = <0x2c>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&pp3300_fp_tp>;
hid-descr-addr = <0x20>;
wakeup-source;
};
};

26
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dts Normal file
View file

@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Lazor Limozeen board device tree source
*
* Copyright 2020 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
model = "Google Lazor Limozeen without Touchscreen";
compatible = "google,lazor-sku6", "google,lazor-sku5", "qcom,sc7180";
};
/delete-node/&ap_ts;
&panel {
compatible = "innolux,n116bca-ea1", "innolux,n116bge";
};
&sdhc_2 {
status = "okay";
};

42
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dts Normal file
View file

@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Lazor Limozeen board device tree source
*
* Copyright 2020 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
model = "Google Lazor Limozeen";
compatible = "google,lazor-sku4", "qcom,sc7180";
};
/delete-node/&ap_ts;
&ap_ts_pen_1v8 {
ap_ts: touchscreen@10 {
compatible = "elan,ekth3500";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
interrupt-parent = <&tlmm>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
vcc33-supply = <&pp3300_ts>;
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
};
};
&panel {
compatible = "auo,b116xa01";
};
&sdhc_2 {
status = "okay";
};

9
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
View file

@ -14,6 +14,15 @@ / {
compatible = "google,lazor-rev0", "qcom,sc7180";
};
/*
* Lazor is stuffed with a 47k NTC as charger thermistor which currently is
* not supported by the PM6150 ADC driver. Disable the charger thermal zone
* to avoid using bogus temperature values.
*/
&charger_thermal {
status = "disabled";
};
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;

9
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts
View file

@ -14,6 +14,15 @@ / {
compatible = "google,lazor-rev1", "google,lazor-rev2", "qcom,sc7180";
};
/*
* Lazor is stuffed with a 47k NTC as charger thermistor which currently is
* not supported by the PM6150 ADC driver. Disable the charger thermal zone
* to avoid using bogus temperature values.
*/
&charger_thermal {
status = "disabled";
};
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;

5
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts
View file

@ -5,7 +5,10 @@
* Copyright 2020 Google LLC.
*/
#include "sc7180-trogdor-lazor-r3.dts"
/dts-v1/;
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-lite.dtsi"
/ {
model = "Google Lazor (rev3+) with KB Backlight";

4
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts
View file

@ -5,7 +5,9 @@
* Copyright 2020 Google LLC.
*/
#include "sc7180-trogdor-lazor-r3.dts"
/dts-v1/;
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {

10
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts
View file

@ -8,8 +8,18 @@
/dts-v1/;
#include "sc7180-trogdor-lazor.dtsi"
#include "sc7180-lite.dtsi"
/ {
model = "Google Lazor (rev3+)";
compatible = "google,lazor", "qcom,sc7180";
};
/*
* Lazor is stuffed with a 47k NTC as charger thermistor which currently is
* not supported by the PM6150 ADC driver. Disable the charger thermal zone
* to avoid using bogus temperature values.
*/
&charger_thermal {
status = "disabled";
};

39
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
View file

@ -12,23 +12,6 @@
#include "sc7180-trogdor.dtsi"
/ {
panel: panel {
compatible = "boe,nv133fhm-n62";
power-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
ports {
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
};
&ap_sar_sensor {
semtech,cs0-ground;
semtech,combined-sensors = <3>;
@ -58,8 +41,30 @@ ap_ts: touchscreen@10 {
};
};
&panel {
compatible = "boe,nv133fhm-n62";
};
&trackpad {
interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
};
&wifi {
qcom,ath10k-calibration-variant = "GO_LAZOR";
};
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&trackpad_int_1v8_odl {
pinmux {
pins = "gpio58";
};
pinconf {
pins = "gpio58";
};
};
&ts_reset_l {
pinconf {
/* This pin is not connected on -rev0, pull up to park. */

14
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dts Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Pompom board device tree source
*
* Copyright 2020 Google LLC.
*/
#include "sc7180-trogdor-pompom-r1.dts"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
model = "Google Pompom (rev1) with LTE";
compatible = "google,pompom-rev1-sku0", "qcom,sc7180";
};

26
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts Normal file
View file

@ -0,0 +1,26 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Pompom board device tree source
*
* Copyright 2020 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor-pompom.dtsi"
/ {
model = "Google Pompom (rev1)";
compatible = "google,pompom-rev1", "qcom,sc7180";
};
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
/delete-property/regulator-boot-on;
};
&pp3300_l7c {
regulator-always-on;
regulator-boot-on;
};

14
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dts Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Pompom board device tree source
*
* Copyright 2020 Google LLC.
*/
#include "sc7180-trogdor-pompom-r2.dts"
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
model = "Google Pompom (rev2+) with LTE";
compatible = "google,pompom-sku0", "qcom,sc7180";
};

44
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts Normal file
View file

@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Pompom board device tree source
*
* Copyright 2020 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor-pompom.dtsi"
/ {
model = "Google Pompom (rev2+)";
compatible = "google,pompom", "qcom,sc7180";
};
&keyboard_controller {
function-row-physmap = <
MATRIX_KEY(0x00, 0x02, 0) /* T1 */
MATRIX_KEY(0x03, 0x02, 0) /* T2 */
MATRIX_KEY(0x02, 0x02, 0) /* T3 */
MATRIX_KEY(0x01, 0x02, 0) /* T4 */
MATRIX_KEY(0x03, 0x04, 0) /* T5 */
MATRIX_KEY(0x02, 0x04, 0) /* T6 */
MATRIX_KEY(0x01, 0x04, 0) /* T7 */
MATRIX_KEY(0x02, 0x09, 0) /* T8 */
MATRIX_KEY(0x01, 0x09, 0) /* T9 */
MATRIX_KEY(0x00, 0x04, 0) /* T10 */
>;
linux,keymap = <
MATRIX_KEY(0x00, 0x02, KEY_BACK)
MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
MATRIX_KEY(0x01, 0x02, KEY_SCALE)
MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
MATRIX_KEY(0x02, 0x09, KEY_MUTE)
MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
CROS_STD_MAIN_KEYMAP
>;
};

288
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi Normal file
View file

@ -0,0 +1,288 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Pompom board device tree source
*
* Copyright 2020 Google LLC.
*/
#include "sc7180.dtsi"
ap_ec_spi: &spi6 {};
ap_h1_spi: &spi0 {};
#include "sc7180-trogdor.dtsi"
/ {
thermal-zones {
5v-choke-thermal {
polling-delay-passive = <0>;
polling-delay = <250>;
thermal-sensors = <&pm6150_adc_tm 1>;
trips {
5v-choke-crit {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
};
&alc5682 {
realtek,dmic-clk-driving-high = "true";
};
&cpu6_alert0 {
temperature = <60000>;
};
&cpu6_alert1 {
temperature = <65000>;
};
&cpu6_thermal {
sustainable-power = <948>;
};
&cpu7_alert0 {
temperature = <60000>;
};
&cpu7_alert1 {
temperature = <65000>;
};
&cpu7_thermal {
sustainable-power = <948>;
};
&cpu8_alert0 {
temperature = <60000>;
};
&cpu8_alert1 {
temperature = <65000>;
};
&cpu8_thermal {
sustainable-power = <948>;
};
&cpu9_alert0 {
temperature = <60000>;
};
&cpu9_alert1 {
temperature = <65000>;
};
&cpu9_thermal {
sustainable-power = <948>;
};
&gpio_keys {
status = "okay";
};
ap_ts_pen_1v8: &i2c4 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@10 {
compatible = "hid-over-i2c";
reg = <0x10>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
interrupt-parent = <&tlmm>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <20>;
hid-descr-addr = <0x0001>;
vdd-supply = <&pp3300_ts>;
};
};
&panel {
compatible = "kingdisplay,kd116n21-30nv-a010";
};
&pen_insert {
/* Insert = high, eject = low */
gpios = <&tlmm 52 GPIO_ACTIVE_HIGH>;
};
&pm6150_adc {
5v-choke-thermistor@4e {
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
};
};
&pm6150_adc_tm {
status = "okay";
5v-choke-thermistor@1 {
reg = <1>;
io-channels = <&pm6150_adc ADC5_AMUX_THM2_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
};
&sdhc_2 {
status = "okay";
};
&usb_c1 {
status = "disabled";
};
&wifi {
qcom,ath10k-calibration-variant = "GO_POMPOM";
};
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "TP_INT_ODL",
"AP_RAM_ID0",
"AP_SKU_ID2",
"AP_RAM_ID1",
"",
"AP_RAM_ID2",
"AP_TP_I2C_SDA",
"AP_TP_I2C_SCL",
"TS_RESET_L",
"TS_INT_L",
"",
"EDP_BRIJ_IRQ",
"AP_EDP_BKLTEN",
"",
"",
"EDP_BRIJ_I2C_SDA",
"EDP_BRIJ_I2C_SCL",
"HUB_RST_L",
"",
"",
"",
"",
"",
"AMP_EN",
"P_SENSOR_INT_L",
"AP_SAR_SENSOR_SDA",
"AP_SAR_SENSOR_SCL",
"",
"HP_IRQ",
"",
"EN_PP3300_DX_EDP",
"AP_BRD_ID2",
"BRIJ_SUSPEND",
"AP_BRD_ID0",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"",
"",
"",
"",
"H1_AP_INT_ODL",
"",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"HP_I2C_SDA",
"HP_I2C_SCL",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DIN",
"PEN_PDCT_L",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"HP_MCLK",
"AP_SKU_ID0",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_SPI_CLK",
"AP_SPI_MOSI",
"AP_SPI_MISO",
/*
* AP_FLASH_WP_L is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_L.
*/
"AP_FLASH_WP_L",
"",
"AP_SPI_CS0_L",
"SD_CD_ODL",
"",
"",
"",
"",
"",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RST",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK",
"UIM1_RST",
"",
"EN_PP3300_CODEC",
"EN_PP3300_HUB",
"",
"DMIC_SEL",
"",
"",
"",
"AP_SKU_ID1",
"AP_RST_REQ",
"",
"AP_BRD_ID1",
"AP_EC_INT_R_L",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"EDP_BRIJ_EN",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"AP_TS_PEN_I2C_SDA",
"AP_TS_PEN_I2C_SCL",
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
dmic_sel: dmic-sel {
pinmux {
pins = "gpio86";
function = "gpio";
};
pinconf {
pins = "gpio86";
bias-pull-down;
};
};
};

35
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts
View file

@ -17,21 +17,6 @@
/ {
model = "Google Trogdor (rev1+)";
compatible = "google,trogdor", "qcom,sc7180";
panel: panel {
compatible = "auo,b116xa01";
power-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
ports {
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
};
ap_ts_pen_1v8: &i2c4 {
@ -53,6 +38,10 @@ ap_ts: touchscreen@10 {
};
};
&panel {
compatible = "auo,b116xa01";
};
&pp3300_hub {
/* pp3300_l7c is used to power the USB hub */
/delete-property/regulator-always-on;
@ -68,6 +57,22 @@ &sdhc_2 {
status = "okay";
};
&trackpad {
interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
};
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
&trackpad_int_1v8_odl {
pinmux {
pins = "gpio58";
};
pinconf {
pins = "gpio58";
};
};
/* PINCTRL - board-specific pinctrl */
&tlmm {

162
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View file

@ -6,6 +6,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
@ -15,16 +16,18 @@
/ {
thermal-zones {
charger-thermal {
charger_thermal: charger-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm6150_adc_tm 1>;
thermal-sensors = <&pm6150_adc_tm 0>;
trips {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
charger-crit {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
};
};
};
@ -243,6 +246,7 @@ pen_insert: pen-insert {
gpios = <&tlmm 52 GPIO_ACTIVE_LOW>;
linux,code = <SW_PEN_INSERTED>;
linux,input-type = <EV_SW>;
wakeup-event-action = <EV_ACT_DEASSERTED>;
wakeup-source;
};
};
@ -255,6 +259,21 @@ max98357a: audio-codec-0 {
#sound-dai-cells = <0>;
};
panel: panel {
/* Compatible will be filled in per-board */
power-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
hpd-gpios = <&sn65dsi86_bridge 2 GPIO_ACTIVE_HIGH>;
ports {
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
pwmleds {
compatible = "pwm-leds";
keyboard_backlight: keyboard-backlight {
@ -551,6 +570,10 @@ cr50: tpm@0 {
};
};
&camcc {
status = "disabled";
};
&dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
@ -642,14 +665,14 @@ ap_tp_i2c: &i2c7 {
status = "okay";
clock-frequency = <400000>;
trackpad@15 {
trackpad: trackpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
pinctrl-names = "default";
pinctrl-0 = <&trackpad_int_1v8_odl>;
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&pp3300_fp_tp>;
@ -716,8 +739,8 @@ charger-thermistor@4f {
&pm6150_adc_tm {
status = "okay";
charger-thermistor@1 {
reg = <1>;
charger-thermistor@0 {
reg = <0>;
io-channels = <&pm6150_adc ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
@ -768,17 +791,17 @@ &sdhc_2 {
};
&spi0 {
pinctrl-0 = <&qup_spi0_cs_gpio>;
pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_cs_gpio>;
cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
&spi6 {
pinctrl-0 = <&qup_spi6_cs_gpio>;
pinctrl-0 = <&qup_spi6_cs_gpio_init_high>, <&qup_spi6_cs_gpio>;
cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
};
ap_spi_fp: &spi10 {
pinctrl-0 = <&qup_spi10_cs_gpio>;
pinctrl-0 = <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
cros_ec_fp: ec@0 {
@ -787,7 +810,7 @@ cros_ec_fp: ec@0 {
interrupt-parent = <&tlmm>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&fp_to_ap_irq_l>, <&fp_rst_l>, <&fpmcu_boot0>, <&fpmcu_sel>;
pinctrl-0 = <&fp_to_ap_irq_l>;
spi-max-frequency = <3000000>;
};
};
@ -812,7 +835,6 @@ bluetooth: bluetooth {
vddrf-supply = <&pp1300_l2c>;
vddch0-supply = <&pp3300_l10c>;
max-speed = <3200000>;
clocks = <&rpmhcc RPMH_RF_CLK2>;
};
};
@ -875,6 +897,22 @@ pinconf {
};
};
&pri_mi2s_active {
pinconf {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
drive-strength = <2>;
bias-pull-down;
};
};
&pri_mi2s_mclk_active {
pinconf {
pins = "gpio57";
drive-strength = <2>;
bias-pull-down;
};
};
&qspi_cs0 {
pinconf {
pins = "gpio68";
@ -1015,6 +1053,14 @@ pinconf-rx {
};
};
&sec_mi2s_active {
pinconf {
pins = "gpio49", "gpio50", "gpio51";
drive-strength = <2>;
bias-pull-down;
};
};
/* PINCTRL - board-specific pinctrl */
&pm6150_gpio {
@ -1109,20 +1155,6 @@ pinconf {
};
};
dp_hot_plug_det: dp-hot-plug-det {
pinmux {
pins = "gpio117";
function = "dp_hot";
};
config {
pins = "gpio117";
bias-disable;
input-enable;
drive-strength = <2>;
};
};
edp_brij_en: edp-brij-en {
pinmux {
pins = "gpio104";
@ -1188,48 +1220,6 @@ pinconf {
};
};
fpmcu_boot0: fpmcu-boot0 {
pinmux {
pins = "gpio10";
function = "gpio";
};
pinconf {
pins = "gpio10";
bias-disable;
drive-strength = <2>;
output-low;
};
};
fpmcu_sel: fpmcu-sel {
pinmux {
pins = "gpio22";
function = "gpio";
};
pinconf {
pins = "gpio22";
bias-disable;
drive-strength = <2>;
output-high;
};
};
fp_rst_l: fp-rst-l {
pinmux {
pins = "gpio5";
function = "gpio";
};
pinconf {
pins = "gpio5";
bias-disable;
drive-strength = <2>;
output-high;
};
};
fp_to_ap_irq_l: fp-to-ap-irq-l {
pinmux {
pins = "gpio4";
@ -1245,7 +1235,6 @@ pinconf {
};
};
h1_ap_int_odl: h1-ap-int-odl {
pinmux {
pins = "gpio42";
@ -1339,6 +1328,27 @@ pinconf {
};
};
qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high {
pinconf {
pins = "gpio37";
output-high;
};
};
qup_spi6_cs_gpio_init_high: qup-spi6-cs-gpio-init-high {
pinconf {
pins = "gpio62";
output-high;
};
};
qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high {
pinconf {
pins = "gpio89";
output-high;
};
};
qup_uart3_sleep: qup-uart3-sleep {
pinmux {
pins = "gpio38", "gpio39",
@ -1386,14 +1396,16 @@ pinconf-rx {
};
};
trackpad_int_1v8_odl: trackpad-int-1v8-odl {
/* Named trackpad_int_1v8_odl on earlier revision schematics */
trackpad_int_1v8_odl:
tp_int_odl: tp-int-odl {
pinmux {
pins = "gpio58";
pins = "gpio0";
function = "gpio";
};
pinconf {
pins = "gpio58";
pins = "gpio0";
/* Has external pullup */
bias-disable;

51
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file

@ -1856,12 +1856,6 @@ pinmux {
pins = "gpio49", "gpio50", "gpio51";
function = "mi2s_1";
};
pinconf {
pins = "gpio49", "gpio50", "gpio51";
drive-strength = <8>;
bias-pull-up;
};
};
pri_mi2s_active: pri-mi2s-active {
@ -1869,12 +1863,6 @@ pinmux {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
function = "mi2s_0";
};
pinconf {
pins = "gpio53", "gpio54", "gpio55", "gpio56";
drive-strength = <8>;
bias-pull-up;
};
};
pri_mi2s_mclk_active: pri-mi2s-mclk-active {
@ -1882,12 +1870,6 @@ pinmux {
pins = "gpio57";
function = "lpass_ext";
};
pinconf {
pins = "gpio57";
drive-strength = <8>;
bias-pull-up;
};
};
sdc1_on: sdc1-on {
@ -2770,12 +2752,11 @@ usb_1_hsphy: phy@88e3000 {
};
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sc7180-qmp-usb3-phy";
compatible = "qcom,sc7180-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
<0 0x088e8000 0 0x38>;
reg-names = "reg-base", "dp_com";
<0 0x088e8000 0 0x38>,
<0 0x088ea000 0 0x40>;
status = "disabled";
#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -2790,7 +2771,7 @@ usb_1_qmpphy: phy-wrapper@88e9000 {
<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: phy@88e9200 {
usb_1_ssphy: usb3-phy@88e9200 {
reg = <0 0x088e9200 0 0x128>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x218>,
@ -2803,6 +2784,16 @@ usb_1_ssphy: phy@88e9200 {
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
dp_phy: dp-phy@88ea200 {
reg = <0 0x088ea200 0 0x200>,
<0 0x088ea400 0 0x200>,
<0 0x088eaa00 0 0x200>,
<0 0x088ea600 0 0x200>,
<0 0x088ea800 0 0x200>;
#clock-cells = <1>;
#phy-cells = <0>;
};
};
dc_noc: interconnect@9160000 {
@ -2854,10 +2845,10 @@ usb_1: usb@a6f8800 {
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <150000000>;
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "ss_phy_irq",
"dm_hs_phy_irq", "dp_hs_phy_irq";
@ -3166,8 +3157,8 @@ dispcc: clock-controller@af00000 {
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&dsi_phy 0>,
<&dsi_phy 1>,
<0>,
<0>;
<&dp_phy 0>,
<&dp_phy 1>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk_src",
"dsi0_phy_pll_out_byteclk",
@ -3222,7 +3213,7 @@ aoss_reset: reset-controller@c2a0000 {
#reset-cells = <1>;
};
aoss_qmp: qmp@c300000 {
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sc7180-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

47
arch/arm64/boot/dts/qcom/sc7280-idp.dts Normal file
View file

@ -0,0 +1,47 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* sc7280 IDP board device tree source
*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "sc7280.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
compatible = "qcom,sc7280-idp", "qcom,sc7280";
aliases {
serial0 = &uart5;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&qupv3_id_0 {
status = "okay";
};
&uart5 {
status = "okay";
};
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
&qup_uart5_default {
tx {
pins = "gpio46";
drive-strength = <2>;
bias-disable;
};
rx {
pins = "gpio47";
drive-strength = <2>;
bias-pull-up;
};
};

608
arch/arm64/boot/dts/qcom/sc7280.dtsi Normal file
View file

@ -0,0 +1,608 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* sc7280 SoC device tree source
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
clock-frequency = <76800000>;
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
aop_mem: memory@80800000 {
reg = <0x0 0x80800000 0x0 0x60000>;
no-map;
};
aop_cmd_db_mem: memory@80860000 {
reg = <0x0 0x80860000 0x0 0x20000>;
compatible = "qcom,cmd-db";
no-map;
};
cpucp_mem: memory@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@400 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU5: cpu@500 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU6: cpu@600 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU7: cpu@700 {
device_type = "cpu";
compatible = "arm,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-down";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <549>;
exit-latency-us = <901>;
min-residency-us = <1774>;
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <702>;
exit-latency-us = <915>;
min-residency-us = <4001>;
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-power-down";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <523>;
exit-latency-us = <1244>;
min-residency-us = <2207>;
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <526>;
exit-latency-us = <1854>;
min-residency-us = <5555>;
local-timer-stop;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x40003444>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
min-residency-us = <9926>;
local-timer-stop;
};
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0 0x80000000 0 0>;
};
firmware {
scm {
compatible = "qcom,scm-sc7280", "qcom,scm";
};
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sc7280";
reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
<0>, <0>, <0>, <0>, <0>, <0>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe-clk",
"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
"ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
uart5: serial@994000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 3>, <69 86 1>,
<70 520 54>, <124 609 31>, <155 63 1>,
<156 716 12>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
<0 0x0c600000 0 0x2000000>,
<0 0x0e600000 0 0x100000>,
<0 0x0e700000 0 0xa0000>,
<0 0x0c40a000 0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <4>;
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f100000 0 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
};
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
dma-coherent;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0x17a00000 0 0x10000>, /* GICD */
<0 0x17a60000 0 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
gic-its@17a40000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0 0x17a40000 0 0x20000>;
status = "disabled";
};
};
watchdog@17c10000 {
compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
reg = <0 0x17c10000 0 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0 0x17c20000 0 0x1000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c21000 0 0x1000>,
<0 0x17c22000 0 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c23000 0 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c25000 0 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c27000 0 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c29000 0 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2b000 0 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2d000 0 0x1000>;
status = "disabled";
};
};
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
reg = <0 0x18200000 0 0x10000>,
<0 0x18210000 0 0x10000>,
<0 0x18220000 0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
rpmhpd: power-controller {
compatible = "qcom,sc7280-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_low_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_svs_l2: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
};
rpmhpd_opp_nom: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_turbo: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
rpmhcc: clock-controller {
compatible = "qcom,sc7280-rpmh-clk";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
};

27
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View file

@ -1015,7 +1015,7 @@ swm: swm@c85 {
left_spkr: wsa8810-left{
compatible = "sdw10217201000";
reg = <0 1>;
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrLeft";
#sound-dai-cells = <0>;
@ -1023,7 +1023,7 @@ left_spkr: wsa8810-left{
right_spkr: wsa8810-right{
compatible = "sdw10217201000";
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
reg = <0 2>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrRight";
@ -1108,6 +1108,25 @@ &cci {
status = "okay";
};
&camss {
vdda-supply = <&vreg_l1a_0p875>;
status = "ok";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csiphy0_ep: endpoint {
clock-lanes = <7>;
data-lanes = <0 1 2 3>;
remote-endpoint = <&ov8856_ep>;
};
};
};
};
&cci_i2c0 {
camera@10 {
compatible = "ovti,ov8856";
@ -1137,7 +1156,7 @@ camera@10 {
avdd-supply = <&cam0_avdd_2v8>;
dvdd-supply = <&cam0_dvdd_1v2>;
status = "disable";
status = "ok";
port {
ov8856_ep: endpoint {
@ -1145,7 +1164,7 @@ ov8856_ep: endpoint {
link-frequencies = /bits/ 64
<360000000 180000000>;
data-lanes = <1 2 3 4>;
// remote-endpoint = <&csiphy0_ep>;
remote-endpoint = <&csiphy0_ep>;
};
};
};

139
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file

@ -2382,7 +2382,7 @@ tlmm: pinctrl@3400000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 150>;
gpio-ranges = <&tlmm 0 0 151>;
wakeup-parent = <&pdc_intc>;
cci0_default: cci0-default {
@ -3909,6 +3909,141 @@ videocc: clock-controller@ab00000 {
#reset-cells = <1>;
};
camss: camss@a00000 {
compatible = "qcom,sdm845-camss";
reg = <0 0xacb3000 0 0x1000>,
<0 0xacba000 0 0x1000>,
<0 0xacc8000 0 0x1000>,
<0 0xac65000 0 0x1000>,
<0 0xac66000 0 0x1000>,
<0 0xac67000 0 0x1000>,
<0 0xac68000 0 0x1000>,
<0 0xacaf000 0 0x4000>,
<0 0xacb6000 0 0x4000>,
<0 0xacc4000 0 0x4000>;
reg-names = "csid0",
"csid1",
"csid2",
"csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"vfe0",
"vfe1",
"vfe_lite";
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "csid0",
"csid1",
"csid2",
"csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"vfe0",
"vfe1",
"vfe_lite";
power-domains = <&clock_camcc IFE_0_GDSC>,
<&clock_camcc IFE_1_GDSC>,
<&clock_camcc TITAN_TOP_GDSC>;
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
<&clock_camcc CAM_CC_CPAS_AHB_CLK>,
<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
<&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
<&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY0_CLK>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY1_CLK>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY2_CLK>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
<&clock_camcc CAM_CC_CSIPHY3_CLK>,
<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>,
<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
<&gcc GCC_CAMERA_AHB_CLK>,
<&gcc GCC_CAMERA_AXI_CLK>,
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&clock_camcc CAM_CC_SOC_AHB_CLK>,
<&clock_camcc CAM_CC_IFE_0_AXI_CLK>,
<&clock_camcc CAM_CC_IFE_0_CLK>,
<&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_1_AXI_CLK>,
<&clock_camcc CAM_CC_IFE_1_CLK>,
<&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
<&clock_camcc CAM_CC_IFE_LITE_CLK>,
<&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>;
clock-names = "camnoc_axi",
"cpas_ahb",
"cphy_rx_src",
"csi0",
"csi0_src",
"csi1",
"csi1_src",
"csi2",
"csi2_src",
"csiphy0",
"csiphy0_timer",
"csiphy0_timer_src",
"csiphy1",
"csiphy1_timer",
"csiphy1_timer_src",
"csiphy2",
"csiphy2_timer",
"csiphy2_timer_src",
"csiphy3",
"csiphy3_timer",
"csiphy3_timer_src",
"gcc_camera_ahb",
"gcc_camera_axi",
"slow_ahb_src",
"soc_ahb",
"vfe0_axi",
"vfe0",
"vfe0_cphy_rx",
"vfe0_src",
"vfe1_axi",
"vfe1",
"vfe1_cphy_rx",
"vfe1_src",
"vfe_lite",
"vfe_lite_cphy_rx",
"vfe_lite_src";
iommus = <&apps_smmu 0x0808 0x0>,
<&apps_smmu 0x0810 0x8>,
<&apps_smmu 0x0c08 0x0>,
<&apps_smmu 0x0c10 0x8>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
cci: cci@ac4a000 {
compatible = "qcom,sdm845-cci";
#address-cells = <1>;
@ -4428,7 +4563,7 @@ aoss_reset: reset-controller@c2a0000 {
#reset-cells = <1>;
};
aoss_qmp: qmp@c300000 {
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sdm845-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;

2
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file

@ -914,7 +914,7 @@ tlmm: pinctrl@3100000 {
<0x0 0x03D00000 0x0 0x300000>;
reg-names = "west", "east", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 175>;
gpio-ranges = <&tlmm 0 0 176>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;

4
arch/arm64/boot/dts/qcom/sm8250-mtp.dts
View file

@ -601,10 +601,6 @@ pa-therm2@4f {
};
};
&pm8150_rtc {
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};

586
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file

@ -279,7 +279,7 @@ mmcx_reg: mmcx-reg {
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -548,8 +548,6 @@ spi14: spi@880000 {
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi14_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -576,8 +574,6 @@ spi15: spi@884000 {
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi15_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -604,8 +600,6 @@ spi16: spi@888000 {
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi16_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -632,8 +626,6 @@ spi17: spi@88c000 {
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi17_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -673,8 +665,6 @@ spi18: spi@890000 {
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi18_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -714,8 +704,6 @@ spi19: spi@894000 {
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi19_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -755,8 +743,6 @@ spi0: spi@980000 {
reg = <0 0x00980000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -783,8 +769,6 @@ spi1: spi@984000 {
reg = <0 0x00984000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -811,8 +795,6 @@ spi2: spi@988000 {
reg = <0 0x00988000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -852,8 +834,6 @@ spi3: spi@98c000 {
reg = <0 0x0098c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -880,8 +860,6 @@ spi4: spi@990000 {
reg = <0 0x00990000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -908,8 +886,6 @@ spi5: spi@994000 {
reg = <0 0x00994000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -936,8 +912,6 @@ spi6: spi@998000 {
reg = <0 0x00998000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -977,8 +951,6 @@ spi7: spi@99c000 {
reg = <0 0x0099c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -1018,8 +990,6 @@ spi8: spi@a80000 {
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -1046,8 +1016,6 @@ spi9: spi@a84000 {
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -1074,8 +1042,6 @@ spi10: spi@a88000 {
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -1102,8 +1068,6 @@ spi11: spi@a8c000 {
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -1130,8 +1094,6 @@ spi12: spi@a90000 {
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -1171,8 +1133,6 @@ spi13: spi@a94000 {
reg = <0 0x00a94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi13_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@ -2647,7 +2607,7 @@ tsens1: thermal-sensor@c265000 {
#thermal-sensor-cells = <1>;
};
aoss_qmp: qmp@c300000 {
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8250-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP
@ -2689,7 +2649,7 @@ tlmm: pinctrl@f100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 180>;
gpio-ranges = <&tlmm 0 0 181>;
wakeup-parent = <&pdc>;
pri_mi2s_active: pri-mi2s-active {
@ -2983,304 +2943,324 @@ config {
};
};
qup_spi0_default: qup-spi0-default {
mux {
pins = "gpio28", "gpio29",
"gpio30", "gpio31";
function = "qup0";
};
config {
pins = "gpio28", "gpio29",
"gpio30", "gpio31";
drive-strength = <6>;
bias-disable;
};
qup_spi0_cs: qup-spi0-cs {
pins = "gpio31";
function = "qup0";
};
qup_spi1_default: qup-spi1-default {
mux {
pins = "gpio4", "gpio5",
"gpio6", "gpio7";
function = "qup1";
};
config {
pins = "gpio4", "gpio5",
"gpio6", "gpio7";
drive-strength = <6>;
bias-disable;
};
qup_spi0_cs_gpio: qup-spi0-cs-gpio {
pins = "gpio31";
function = "gpio";
};
qup_spi2_default: qup-spi2-default {
mux {
pins = "gpio115", "gpio116",
"gpio117", "gpio118";
function = "qup2";
};
config {
pins = "gpio115", "gpio116",
"gpio117", "gpio118";
drive-strength = <6>;
bias-disable;
};
qup_spi0_data_clk: qup-spi0-data-clk {
pins = "gpio28", "gpio29",
"gpio30";
function = "qup0";
};
qup_spi3_default: qup-spi3-default {
mux {
pins = "gpio119", "gpio120",
"gpio121", "gpio122";
function = "qup3";
};
config {
pins = "gpio119", "gpio120",
"gpio121", "gpio122";
drive-strength = <6>;
bias-disable;
};
qup_spi1_cs: qup-spi1-cs {
pins = "gpio7";
function = "qup1";
};
qup_spi4_default: qup-spi4-default {
mux {
pins = "gpio8", "gpio9",
"gpio10", "gpio11";
function = "qup4";
};
config {
pins = "gpio8", "gpio9",
"gpio10", "gpio11";
drive-strength = <6>;
bias-disable;
};
qup_spi1_cs_gpio: qup-spi1-cs-gpio {
pins = "gpio7";
function = "gpio";
};
qup_spi5_default: qup-spi5-default {
mux {
pins = "gpio12", "gpio13",
"gpio14", "gpio15";
function = "qup5";
};
config {
pins = "gpio12", "gpio13",
"gpio14", "gpio15";
drive-strength = <6>;
bias-disable;
};
qup_spi1_data_clk: qup-spi1-data-clk {
pins = "gpio4", "gpio5",
"gpio6";
function = "qup1";
};
qup_spi6_default: qup-spi6-default {
mux {
pins = "gpio16", "gpio17",
"gpio18", "gpio19";
function = "qup6";
};
config {
pins = "gpio16", "gpio17",
"gpio18", "gpio19";
drive-strength = <6>;
bias-disable;
};
qup_spi2_cs: qup-spi2-cs {
pins = "gpio118";
function = "qup2";
};
qup_spi7_default: qup-spi7-default {
mux {
pins = "gpio20", "gpio21",
"gpio22", "gpio23";
function = "qup7";
};
config {
pins = "gpio20", "gpio21",
"gpio22", "gpio23";
drive-strength = <6>;
bias-disable;
};
qup_spi2_cs_gpio: qup-spi2-cs-gpio {
pins = "gpio118";
function = "gpio";
};
qup_spi8_default: qup-spi8-default {
mux {
pins = "gpio24", "gpio25",
"gpio26", "gpio27";
function = "qup8";
};
config {
pins = "gpio24", "gpio25",
"gpio26", "gpio27";
drive-strength = <6>;
bias-disable;
};
qup_spi2_data_clk: qup-spi2-data-clk {
pins = "gpio115", "gpio116",
"gpio117";
function = "qup2";
};
qup_spi9_default: qup-spi9-default {
mux {
pins = "gpio125", "gpio126",
"gpio127", "gpio128";
function = "qup9";
};
config {
pins = "gpio125", "gpio126",
"gpio127", "gpio128";
drive-strength = <6>;
bias-disable;
};
qup_spi3_cs: qup-spi3-cs {
pins = "gpio122";
function = "qup3";
};
qup_spi10_default: qup-spi10-default {
mux {
pins = "gpio129", "gpio130",
"gpio131", "gpio132";
function = "qup10";
};
config {
pins = "gpio129", "gpio130",
"gpio131", "gpio132";
drive-strength = <6>;
bias-disable;
};
qup_spi3_cs_gpio: qup-spi3-cs-gpio {
pins = "gpio122";
function = "gpio";
};
qup_spi11_default: qup-spi11-default {
mux {
pins = "gpio60", "gpio61",
"gpio62", "gpio63";
function = "qup11";
};
config {
pins = "gpio60", "gpio61",
"gpio62", "gpio63";
drive-strength = <6>;
bias-disable;
};
qup_spi3_data_clk: qup-spi3-data-clk {
pins = "gpio119", "gpio120",
"gpio121";
function = "qup3";
};
qup_spi12_default: qup-spi12-default {
mux {
pins = "gpio32", "gpio33",
"gpio34", "gpio35";
function = "qup12";
};
config {
pins = "gpio32", "gpio33",
"gpio34", "gpio35";
drive-strength = <6>;
bias-disable;
};
qup_spi4_cs: qup-spi4-cs {
pins = "gpio11";
function = "qup4";
};
qup_spi13_default: qup-spi13-default {
mux {
pins = "gpio36", "gpio37",
"gpio38", "gpio39";
function = "qup13";
};
config {
pins = "gpio36", "gpio37",
"gpio38", "gpio39";
drive-strength = <6>;
bias-disable;
};
qup_spi4_cs_gpio: qup-spi4-cs-gpio {
pins = "gpio11";
function = "gpio";
};
qup_spi14_default: qup-spi14-default {
mux {
pins = "gpio40", "gpio41",
"gpio42", "gpio43";
function = "qup14";
};
config {
pins = "gpio40", "gpio41",
"gpio42", "gpio43";
drive-strength = <6>;
bias-disable;
};
qup_spi4_data_clk: qup-spi4-data-clk {
pins = "gpio8", "gpio9",
"gpio10";
function = "qup4";
};
qup_spi15_default: qup-spi15-default {
mux {
pins = "gpio44", "gpio45",
"gpio46", "gpio47";
function = "qup15";
};
config {
pins = "gpio44", "gpio45",
"gpio46", "gpio47";
drive-strength = <6>;
bias-disable;
};
qup_spi5_cs: qup-spi5-cs {
pins = "gpio15";
function = "qup5";
};
qup_spi16_default: qup-spi16-default {
mux {
pins = "gpio48", "gpio49",
"gpio50", "gpio51";
function = "qup16";
};
config {
pins = "gpio48", "gpio49",
"gpio50", "gpio51";
drive-strength = <6>;
bias-disable;
};
qup_spi5_cs_gpio: qup-spi5-cs-gpio {
pins = "gpio15";
function = "gpio";
};
qup_spi17_default: qup-spi17-default {
mux {
pins = "gpio52", "gpio53",
"gpio54", "gpio55";
function = "qup17";
};
config {
pins = "gpio52", "gpio53",
"gpio54", "gpio55";
drive-strength = <6>;
bias-disable;
};
qup_spi5_data_clk: qup-spi5-data-clk {
pins = "gpio12", "gpio13",
"gpio14";
function = "qup5";
};
qup_spi18_default: qup-spi18-default {
mux {
pins = "gpio56", "gpio57",
"gpio58", "gpio59";
function = "qup18";
};
config {
pins = "gpio56", "gpio57",
"gpio58", "gpio59";
drive-strength = <6>;
bias-disable;
};
qup_spi6_cs: qup-spi6-cs {
pins = "gpio19";
function = "qup6";
};
qup_spi19_default: qup-spi19-default {
mux {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
function = "qup19";
};
qup_spi6_cs_gpio: qup-spi6-cs-gpio {
pins = "gpio19";
function = "gpio";
};
config {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
drive-strength = <6>;
bias-disable;
};
qup_spi6_data_clk: qup-spi6-data-clk {
pins = "gpio16", "gpio17",
"gpio18";
function = "qup6";
};
qup_spi7_cs: qup-spi7-cs {
pins = "gpio23";
function = "qup7";
};
qup_spi7_cs_gpio: qup-spi7-cs-gpio {
pins = "gpio23";
function = "gpio";
};
qup_spi7_data_clk: qup-spi7-data-clk {
pins = "gpio20", "gpio21",
"gpio22";
function = "qup7";
};
qup_spi8_cs: qup-spi8-cs {
pins = "gpio27";
function = "qup8";
};
qup_spi8_cs_gpio: qup-spi8-cs-gpio {
pins = "gpio27";
function = "gpio";
};
qup_spi8_data_clk: qup-spi8-data-clk {
pins = "gpio24", "gpio25",
"gpio26";
function = "qup8";
};
qup_spi9_cs: qup-spi9-cs {
pins = "gpio128";
function = "qup9";
};
qup_spi9_cs_gpio: qup-spi9-cs-gpio {
pins = "gpio128";
function = "gpio";
};
qup_spi9_data_clk: qup-spi9-data-clk {
pins = "gpio125", "gpio126",
"gpio127";
function = "qup9";
};
qup_spi10_cs: qup-spi10-cs {
pins = "gpio132";
function = "qup10";
};
qup_spi10_cs_gpio: qup-spi10-cs-gpio {
pins = "gpio132";
function = "gpio";
};
qup_spi10_data_clk: qup-spi10-data-clk {
pins = "gpio129", "gpio130",
"gpio131";
function = "qup10";
};
qup_spi11_cs: qup-spi11-cs {
pins = "gpio63";
function = "qup11";
};
qup_spi11_cs_gpio: qup-spi11-cs-gpio {
pins = "gpio63";
function = "gpio";
};
qup_spi11_data_clk: qup-spi11-data-clk {
pins = "gpio60", "gpio61",
"gpio62";
function = "qup11";
};
qup_spi12_cs: qup-spi12-cs {
pins = "gpio35";
function = "qup12";
};
qup_spi12_cs_gpio: qup-spi12-cs-gpio {
pins = "gpio35";
function = "gpio";
};
qup_spi12_data_clk: qup-spi12-data-clk {
pins = "gpio32", "gpio33",
"gpio34";
function = "qup12";
};
qup_spi13_cs: qup-spi13-cs {
pins = "gpio39";
function = "qup13";
};
qup_spi13_cs_gpio: qup-spi13-cs-gpio {
pins = "gpio39";
function = "gpio";
};
qup_spi13_data_clk: qup-spi13-data-clk {
pins = "gpio36", "gpio37",
"gpio38";
function = "qup13";
};
qup_spi14_cs: qup-spi14-cs {
pins = "gpio43";
function = "qup14";
};
qup_spi14_cs_gpio: qup-spi14-cs-gpio {
pins = "gpio43";
function = "gpio";
};
qup_spi14_data_clk: qup-spi14-data-clk {
pins = "gpio40", "gpio41",
"gpio42";
function = "qup14";
};
qup_spi15_cs: qup-spi15-cs {
pins = "gpio47";
function = "qup15";
};
qup_spi15_cs_gpio: qup-spi15-cs-gpio {
pins = "gpio47";
function = "gpio";
};
qup_spi15_data_clk: qup-spi15-data-clk {
pins = "gpio44", "gpio45",
"gpio46";
function = "qup15";
};
qup_spi16_cs: qup-spi16-cs {
pins = "gpio51";
function = "qup16";
};
qup_spi16_cs_gpio: qup-spi16-cs-gpio {
pins = "gpio51";
function = "gpio";
};
qup_spi16_data_clk: qup-spi16-data-clk {
pins = "gpio48", "gpio49",
"gpio50";
function = "qup16";
};
qup_spi17_cs: qup-spi17-cs {
pins = "gpio55";
function = "qup17";
};
qup_spi17_cs_gpio: qup-spi17-cs-gpio {
pins = "gpio55";
function = "gpio";
};
qup_spi17_data_clk: qup-spi17-data-clk {
pins = "gpio52", "gpio53",
"gpio54";
function = "qup17";
};
qup_spi18_cs: qup-spi18-cs {
pins = "gpio59";
function = "qup18";
};
qup_spi18_cs_gpio: qup-spi18-cs-gpio {
pins = "gpio59";
function = "gpio";
};
qup_spi18_data_clk: qup-spi18-data-clk {
pins = "gpio56", "gpio57",
"gpio58";
function = "qup18";
};
qup_spi19_cs: qup-spi19-cs {
pins = "gpio3";
function = "qup19";
};
qup_spi19_cs_gpio: qup-spi19-cs-gpio {
pins = "gpio3";
function = "gpio";
};
qup_spi19_data_clk: qup-spi19-data-clk {
pins = "gpio0", "gpio1",
"gpio2";
function = "qup19";
};
qup_uart2_default: qup-uart2-default {
@ -3754,7 +3734,7 @@ timer {
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};

319
arch/arm64/boot/dts/qcom/sm8350-hdk.dts Normal file
View file

@ -0,0 +1,319 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020-2021, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8350.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SM8350 HDK";
compatible = "qcom,sm8350-hdk", "qcom,sm8350";
aliases {
serial0 = &uart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&adsp {
status = "okay";
firmware-name = "qcom/sm8350/adsp.mbn";
};
&apps_rsc {
pm8350-rpmh-regulators {
compatible = "qcom,pm8350-rpmh-regulators";
qcom,pmic-id = "b";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-s11-supply = <&vph_pwr>;
vdd-s12-supply = <&vph_pwr>;
vdd-l1-l4-supply = <&vreg_s11b_0p95>;
vdd-l2-l7-supply = <&vreg_bob>;
vdd-l3-l5-supply = <&vreg_bob>;
vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>;
vreg_s10b_1p8: smps10 {
regulator-name = "vreg_s10b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s11b_0p95: smps11 {
regulator-name = "vreg_s11b_0p95";
regulator-min-microvolt = <952000>;
regulator-max-microvolt = <952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s12b_1p25: smps12 {
regulator-name = "vreg_s12b_1p25";
regulator-min-microvolt = <1256000>;
regulator-max-microvolt = <1256000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1b_0p88: ldo1 {
regulator-name = "vreg_l1b_0p88";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_3p07: ldo2 {
regulator-name = "vreg_l2b_3p07";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b_0p9: ldo3 {
regulator-name = "vreg_l3b_0p9";
regulator-min-microvolt = <904000>;
regulator-max-microvolt = <904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5b_0p88: ldo5 {
regulator-name = "vreg_l5b_0p88";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <888000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
};
vreg_l6b_1p2: ldo6 {
regulator-name = "vreg_l6b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1208000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
};
vreg_l7b_2p96: ldo7 {
regulator-name = "vreg_l7b_2p96";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
};
vreg_l9b_1p2: ldo9 {
regulator-name = "vreg_l9b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
};
};
pm8350c-rpmh-regulators {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l12-supply = <&vreg_s1c_1p86>;
vdd-l2-l8-supply = <&vreg_s1c_1p86>;
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
vdd-l6-l9-l11-supply = <&vreg_bob>;
vdd-l10-supply = <&vreg_s12b_1p25>;
vdd-bob-supply = <&vph_pwr>;
vreg_s1c_1p86: smps1 {
regulator-name = "vreg_s1c_1p86";
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <1880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_bob: bob {
regulator-name = "vreg_bob";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
};
vreg_l1c_1p8: ldo1 {
regulator-name = "vreg_l1c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_1p8: ldo2 {
regulator-name = "vreg_l2c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c_1p8: ldo6 {
regulator-name = "vreg_l6c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c_2p96: ldo9 {
regulator-name = "vreg_l9c_2p96";
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_1p2: ldo10 {
regulator-name = "vreg_l10c_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&cdsp {
status = "okay";
firmware-name = "qcom/sm8350/cdsp.mbn";
};
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
};
&qupv3_id_1 {
status = "okay";
};
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
};
&tlmm {
gpio-reserved-ranges = <52 8>;
};
&uart2 {
status = "okay";
};
&ufs_mem_hc {
status = "okay";
reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b_2p96>;
vcc-max-microamp = <800000>;
vccq-supply = <&vreg_l9b_1p2>;
vccq-max-microamp = <900000>;
};
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5b_0p88>;
vdda-max-microamp = <91600>;
vdda-pll-supply = <&vreg_l6b_1p2>;
vdda-pll-max-microamp = <19000>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
/* TODO: Define USB-C connector properly */
dr_mode = "peripheral";
};
&usb_1_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l5b_0p88>;
vdda18-supply = <&vreg_l1c_1p8>;
vdda33-supply = <&vreg_l2b_3p07>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p88>;
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
pinctrl-names = "default";
pinctrl-0 = <&usb_hub_enabled_state>;
};
&usb_2_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l5b_0p88>;
vdda18-supply = <&vreg_l1c_1p8>;
vdda33-supply = <&vreg_l2b_3p07>;
};
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l5b_0p88>;
};
/* PINCTRL - additions to nodes defined in sm8350.dtsi */
&tlmm {
usb_hub_enabled_state: usb-hub-enabled-state {
pins = "gpio42";
function = "gpio";
drive-strength = <2>;
output-low;
};
};

116
arch/arm64/boot/dts/qcom/sm8350-mtp.dts
View file

@ -5,8 +5,15 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8350.dtsi"
#include "pm8350.dtsi"
#include "pm8350b.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
#include "pmr735a.dtsi"
#include "pmr735b.dtsi"
/ {
model = "Qualcomm Technologies, Inc. sm8350 MTP";
@ -31,6 +38,11 @@ vph_pwr: vph-pwr-regulator {
};
};
&adsp {
status = "okay";
firmware-name = "qcom/sm8350/adsp.mbn";
};
&apps_rsc {
pm8350-rpmh-regulators {
compatible = "qcom,pm8350-rpmh-regulators";
@ -56,57 +68,67 @@ pm8350-rpmh-regulators {
vdd-l8-supply = <&vreg_s2c_0p8>;
vreg_s10b_1p8: smps10 {
regulator-name = "vreg_s10b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_s11b_0p95: smps11 {
regulator-name = "vreg_s11b_0p95";
regulator-min-microvolt = <752000>;
regulator-max-microvolt = <1000000>;
};
vreg_s12b_1p25: smps12 {
regulator-name = "vreg_s12b_1p25";
regulator-min-microvolt = <1224000>;
regulator-max-microvolt = <1360000>;
};
vreg_l1b_0p88: ldo1 {
regulator-name = "vreg_l1b_0p88";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_3p07: ldo2 {
regulator-name = "vreg_l2b_3p07";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b_0p9: ldo3 {
regulator-name = "vreg_l3b_0p9";
regulator-min-microvolt = <904000>;
regulator-max-microvolt = <904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5b_0p88: ldo5 {
regulator-name = "vreg_l3b_0p9";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <888000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b_1p2: ldo6 {
regulator-name = "vreg_l6b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1208000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b_2p96: ldo7 {
regulator-name = "vreg_l7b_2p96";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_1p2: ldo9 {
regulator-name = "vreg_l9b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@ -137,99 +159,116 @@ pm8350c-rpmh-regulators {
vdd-bob-supply = <&vph_pwr>;
vreg_s1c_1p86: smps1 {
regulator-name = "vreg_s1c_1p86";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1952000>;
};
vreg_s2c_0p8: smps2 {
regulator-name = "vreg_s2c_0p8";
regulator-min-microvolt = <640000>;
regulator-max-microvolt = <1000000>;
};
vreg_s10c_1p05: smps10 {
regulator-name = "vreg_s10c_1p05";
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1128000>;
};
vreg_bob: bob {
regulator-name = "vreg_bob";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
};
vreg_l1c_1p8: ldo1 {
regulator-name = "vreg_l1c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_1p8: ldo2 {
regulator-name = "vreg_l2c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_3p0: ldo3 {
regulator-name = "vreg_l3c_3p0";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_uim1: ldo4 {
regulator-name = "vreg_l4c_uim1";
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5c_uim2: ldo5 {
regulator-name = "vreg_l5c_uim2";
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c_1p8: ldo6 {
regulator-name = "vreg_l6c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_3p0: ldo7 {
regulator-name = "vreg_l7c_3p0";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c_1p8: ldo8 {
regulator-name = "vreg_l8c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c_2p96: ldo9 {
regulator-name = "vreg_l9c_2p96";
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10c_1p2: ldo10 {
regulator-name = "vreg_l10c_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11c_2p96: ldo11 {
regulator-name = "vreg_l11c_2p96";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12c_1p8: ldo12 {
regulator-name = "vreg_l12c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c_3p0: ldo13 {
regulator-name = "vreg_l13c_3p0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
@ -237,10 +276,25 @@ vreg_l13c_3p0: ldo13 {
};
};
&cdsp {
status = "okay";
firmware-name = "qcom/sm8350/cdsp.mbn";
};
&mpss {
status = "okay";
firmware-name = "qcom/sm8350/modem.mbn";
};
&qupv3_id_1 {
status = "okay";
};
&slpi {
status = "okay";
firmware-name = "qcom/sm8350/slpi.mbn";
};
&tlmm {
gpio-reserved-ranges = <52 8>;
};
@ -248,3 +302,65 @@ &tlmm {
&uart2 {
status = "okay";
};
&ufs_mem_hc {
status = "okay";
reset-gpios = <&tlmm 203 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b_2p96>;
vcc-max-microamp = <800000>;
vccq-supply = <&vreg_l9b_1p2>;
vccq-max-microamp = <900000>;
};
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5b_0p88>;
vdda-max-microamp = <91600>;
vdda-pll-supply = <&vreg_l6b_1p2>;
vdda-pll-max-microamp = <19000>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
&usb_1_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l5b_0p88>;
vdda18-supply = <&vreg_l1c_1p8>;
vdda33-supply = <&vreg_l2b_3p07>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p88>;
};
&usb_2 {
status = "okay";
};
&usb_2_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l5b_0p88>;
vdda18-supply = <&vreg_l1c_1p8>;
vdda33-supply = <&vreg_l2b_3p07>;
};
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l5b_0p88>;
};

726
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file

@ -1,9 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2020, Linaro Limaited
* Copyright (c) 2020, Linaro Limited
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
@ -43,6 +44,7 @@ CPU0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@ -58,6 +60,7 @@ CPU1: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@ -70,6 +73,7 @@ CPU2: cpu@200 {
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@ -82,6 +86,7 @@ CPU3: cpu@300 {
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@ -94,6 +99,7 @@ CPU4: cpu@400 {
reg = <0x0 0x400>;
enable-method = "psci";
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@ -106,6 +112,7 @@ CPU5: cpu@500 {
reg = <0x0 0x500>;
enable-method = "psci";
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@ -119,6 +126,7 @@ CPU6: cpu@600 {
reg = <0x0 0x600>;
enable-method = "psci";
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@ -131,6 +139,7 @@ CPU7: cpu@700 {
reg = <0x0 0x700>;
enable-method = "psci";
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
@ -153,7 +162,7 @@ memory@80000000 {
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
@ -257,6 +266,15 @@ pil_modem_mem: memory@8b800000 {
no-map;
};
rmtfs_mem: memory@9b800000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x9b800000 0x0 0x280000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
hyp_reserved_mem: memory@d0000000 {
reg = <0x0 0xd0000000 0x0 0x800000>;
no-map;
@ -294,6 +312,102 @@ smem: qcom,smem {
hwlocks = <&tcsr_mutex 3>;
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
smp2p_cdsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_cdsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
smp2p_modem_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_modem_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
smp2p_slpi_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_slpi_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@ -324,8 +438,8 @@ qupv3_id_1: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc 121>,
<&gcc 122>;
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -335,7 +449,7 @@ uart2: serial@98c000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x0098c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc 83>;
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default_state>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
@ -345,12 +459,157 @@ uart2: serial@98c000 {
};
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sm8350-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
#hwlock-cells = <1>;
};
mpss: remoteproc@4080000 {
compatible = "qcom,sm8350-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
<&rpmhpd 0>,
<&rpmhpd 12>;
power-domain-names = "load_state", "cx", "mss";
memory-region = <&pil_modem_mem>;
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
@ -363,7 +622,7 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
aoss_qmp: qmp@c300000 {
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8350-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
@ -374,6 +633,24 @@ aoss_qmp: qmp@c300000 {
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0xc440000 0x0 0x1100>,
<0x0 0xc600000 0x0 0x2000000>,
<0x0 0xe600000 0x0 0x100000>,
<0x0 0xe700000 0x0 0xa0000>,
<0x0 0xc40a000 0x0 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sm8350-tlmm";
reg = <0 0x0f100000 0 0x300000>;
@ -382,7 +659,7 @@ tlmm: pinctrl@f100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 203>;
gpio-ranges = <&tlmm 0 0 204>;
qup_uart3_default_state: qup-uart3-default-state {
rx {
@ -486,6 +763,441 @@ rpmhcc: clock-controller {
clocks = <&xo_board>;
};
rpmhpd: power-controller {
compatible = "qcom,sm8350-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp1 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp5 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_nom: opp6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp8 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp10 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
};
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
<0 0x18592000 0 0x1000>,
<0 0x18593000 0 0x1000>;
reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8350-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
reg = <0 0x01d84000 0 0x3000>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
lanes-per-direction = <2>;
#reset-cells = <1>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
power-domains = <&gcc UFS_PHY_GDSC>;
iommus = <&apps_smmu 0xe0 0x0>;
clock-names =
"ref_clk",
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>;
status = "disabled";
};
ufs_mem_phy: phy@1d87000 {
compatible = "qcom,sm8350-qmp-ufs-phy";
reg = <0 0x01d87000 0 0xe10>;
#address-cells = <2>;
#size-cells = <2>;
#clock-cells = <1>;
ranges;
clock-names = "ref",
"ref_aux";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufs_mem_hc 0>;
reset-names = "ufsphy";
status = "disabled";
ufs_mem_phy_lanes: lanes@1d87400 {
reg = <0 0x01d87400 0 0x108>,
<0 0x01d87600 0 0x1e0>,
<0 0x01d87c00 0 0x1dc>,
<0 0x01d87800 0 0x108>,
<0 0x01d87a00 0 0x1e0>;
#phy-cells = <0>;
#clock-cells = <0>;
};
};
slpi: remoteproc@5c00000 {
compatible = "qcom,sm8350-slpi-pas";
reg = <0 0x05c00000 0 0x4000>;
interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
<&rpmhpd 4>,
<&rpmhpd 5>;
power-domain-names = "load_state", "lcx", "lmx";
memory-region = <&pil_slpi_mem>;
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "slpi";
qcom,remote-pid = <3>;
};
};
cdsp: remoteproc@98900000 {
compatible = "qcom,sm8350-cdsp-pas";
reg = <0 0x098900000 0 0x1400000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
<&rpmhpd 0>,
<&rpmhpd 10>;
power-domain-names = "load_state", "cx", "mxc";
memory-region = <&pil_cdsp_mem>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "cdsp";
qcom,remote-pid = <5>;
};
};
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm8350-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e3000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
};
usb_2_hsphy: phy@88e4000 {
compatible = "qcom,sm8250-usb-hs-phy",
"qcom,usb-snps-hs-7nm-phy";
reg = <0 0x088e4000 0 0x400>;
status = "disabled";
#phy-cells = <0>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "ref";
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
};
usb_1_qmpphy: phy-wrapper@88e9000 {
compatible = "qcom,sm8350-qmp-usb3-phy";
reg = <0 0x088e9000 0 0x200>,
<0 0x088e8000 0 0x20>;
reg-names = "reg-base", "dp_com";
status = "disabled";
#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
clock-names = "aux", "ref_clk_src", "com_aux";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
usb_1_ssphy: phy@88e9200 {
reg = <0 0x088e9200 0 0x200>,
<0 0x088e9400 0 0x200>,
<0 0x088e9c00 0 0x400>,
<0 0x088e9600 0 0x200>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
#phy-cells = <0>;
#clock-cells = <1>;
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_phy_pipe_clk_src";
};
};
usb_2_qmpphy: phy-wrapper@88eb000 {
compatible = "qcom,sm8350-qmp-usb3-uni-phy";
reg = <0 0x088eb000 0 0x200>;
status = "disabled";
#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_EN>,
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux", "ref_clk_src", "ref", "com_aux";
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
<&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
usb_2_ssphy: phy@88ebe00 {
reg = <0 0x088ebe00 0 0x200>,
<0 0x088ec000 0 0x200>,
<0 0x088eb200 0 0x1100>;
#phy-cells = <0>;
#clock-cells = <1>;
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "usb3_uni_phy_pipe_clk_src";
};
};
usb_1: usb@a6f8800 {
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep";
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 14 IRQ_TYPE_EDGE_BOTH>,
<&pdc 15 IRQ_TYPE_EDGE_BOTH>,
<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
power-domains = <&gcc USB30_PRIM_GDSC>;
resets = <&gcc GCC_USB30_PRIM_BCR>;
usb_1_dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
usb_2: usb@a8f8800 {
compatible = "qcom,sm8350-dwc3", "qcom,dwc3";
reg = <0 0x0a8f8800 0 0x400>;
status = "disabled";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
<&gcc GCC_USB3_SEC_CLKREF_EN>;
clock-names = "cfg_noc", "core", "iface", "mock_utmi",
"sleep", "xo";
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>;
assigned-clock-rates = <19200000>, <200000000>;
interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
<&pdc 12 IRQ_TYPE_EDGE_BOTH>,
<&pdc 13 IRQ_TYPE_EDGE_BOTH>,
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
"dm_hs_phy_irq", "ss_phy_irq";
power-domains = <&gcc USB30_SEC_GDSC>;
resets = <&gcc GCC_USB30_SEC_BCR>;
usb_2_dwc3: dwc3@a800000 {
compatible = "snps,dwc3";
reg = <0 0x0a800000 0 0xcd00>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&apps_smmu 0x20 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
phys = <&usb_2_hsphy>, <&usb_2_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
};
adsp: remoteproc@17300000 {
compatible = "qcom,sm8350-adsp-pas";
reg = <0 0x17300000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
<&rpmhpd 4>,
<&rpmhpd 5>;
power-domain-names = "load_state", "lcx", "lmx";
memory-region = <&pil_adsp_mem>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
};
};
};